1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/Timer.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/ADT/Statistic.h"
55 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
56 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
59 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
60 cl::desc("Enable verbose messages in the \"fast\" "
61 "instruction selector"));
63 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
64 cl::desc("Enable abort calls when \"fast\" instruction fails"));
68 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
69 cl::desc("Pop up a window to show dags before the first "
72 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
73 cl::desc("Pop up a window to show dags before legalize types"));
75 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
76 cl::desc("Pop up a window to show dags before legalize"));
78 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the second "
82 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before the post legalize types"
84 " dag combine pass"));
86 ViewISelDAGs("view-isel-dags", cl::Hidden,
87 cl::desc("Pop up a window to show isel dags as they are selected"));
89 ViewSchedDAGs("view-sched-dags", cl::Hidden,
90 cl::desc("Pop up a window to show sched dags as they are processed"));
92 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
93 cl::desc("Pop up a window to show SUnit dags after they are processed"));
95 static const bool ViewDAGCombine1 = false,
96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
97 ViewDAGCombine2 = false,
98 ViewDAGCombineLT = false,
99 ViewISelDAGs = false, ViewSchedDAGs = false,
100 ViewSUnitDAGs = false;
103 //===---------------------------------------------------------------------===//
105 /// RegisterScheduler class - Track the registration of instruction schedulers.
107 //===---------------------------------------------------------------------===//
108 MachinePassRegistry RegisterScheduler::Registry;
110 //===---------------------------------------------------------------------===//
112 /// ISHeuristic command line option for instruction schedulers.
114 //===---------------------------------------------------------------------===//
115 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
116 RegisterPassParser<RegisterScheduler> >
117 ISHeuristic("pre-RA-sched",
118 cl::init(&createDefaultScheduler),
119 cl::desc("Instruction schedulers available (before register"
122 static RegisterScheduler
123 defaultListDAGScheduler("default", "Best scheduler for the target",
124 createDefaultScheduler);
127 //===--------------------------------------------------------------------===//
128 /// createDefaultScheduler - This creates an instruction scheduler appropriate
130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
131 CodeGenOpt::Level OptLevel) {
132 const TargetLowering &TLI = IS->getTargetLowering();
134 if (OptLevel == CodeGenOpt::None)
135 return createFastDAGScheduler(IS, OptLevel);
136 if (TLI.getSchedulingPreference() == Sched::Latency)
137 return createTDListDAGScheduler(IS, OptLevel);
138 if (TLI.getSchedulingPreference() == Sched::RegPressure)
139 return createBURRListDAGScheduler(IS, OptLevel);
140 assert(TLI.getSchedulingPreference() == Sched::Hybrid &&
141 "Unknown sched type!");
142 return createHybridListDAGScheduler(IS, OptLevel);
146 // EmitInstrWithCustomInserter - This method should be implemented by targets
147 // that mark instructions with the 'usesCustomInserter' flag. These
148 // instructions are special in various ways, which require special support to
149 // insert. The specified MachineInstr is created but not inserted into any
150 // basic blocks, and this method is called to expand it into a sequence of
151 // instructions, potentially also creating new basic blocks and control flow.
152 // When new basic blocks are inserted and the edges from MBB to its successors
153 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
156 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
157 MachineBasicBlock *MBB) const {
159 dbgs() << "If a target marks an instruction with "
160 "'usesCustomInserter', it must implement "
161 "TargetLowering::EmitInstrWithCustomInserter!";
167 //===----------------------------------------------------------------------===//
168 // SelectionDAGISel code
169 //===----------------------------------------------------------------------===//
171 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
172 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
173 FuncInfo(new FunctionLoweringInfo(TLI)),
174 CurDAG(new SelectionDAG(tm)),
175 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
181 SelectionDAGISel::~SelectionDAGISel() {
187 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
188 AU.addRequired<AliasAnalysis>();
189 AU.addPreserved<AliasAnalysis>();
190 AU.addRequired<GCModuleInfo>();
191 AU.addPreserved<GCModuleInfo>();
192 MachineFunctionPass::getAnalysisUsage(AU);
195 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
196 /// other function that gcc recognizes as "returning twice". This is used to
197 /// limit code-gen optimizations on the machine function.
199 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
200 static bool FunctionCallsSetJmp(const Function *F) {
201 const Module *M = F->getParent();
202 static const char *ReturnsTwiceFns[] = {
211 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
213 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
214 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
215 if (!Callee->use_empty())
216 for (Value::const_use_iterator
217 I = Callee->use_begin(), E = Callee->use_end();
219 if (const CallInst *CI = dyn_cast<CallInst>(I))
220 if (CI->getParent()->getParent() == F)
225 #undef NUM_RETURNS_TWICE_FNS
228 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
229 // Do some sanity-checking on the command-line options.
230 assert((!EnableFastISelVerbose || EnableFastISel) &&
231 "-fast-isel-verbose requires -fast-isel");
232 assert((!EnableFastISelAbort || EnableFastISel) &&
233 "-fast-isel-abort requires -fast-isel");
235 const Function &Fn = *mf.getFunction();
236 const TargetInstrInfo &TII = *TM.getInstrInfo();
237 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
240 RegInfo = &MF->getRegInfo();
241 AA = &getAnalysis<AliasAnalysis>();
242 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
244 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
247 FuncInfo->set(Fn, *MF);
250 SelectAllBasicBlocks(Fn);
252 // If the first basic block in the function has live ins that need to be
253 // copied into vregs, emit the copies into the top of the block before
254 // emitting the code for the block.
255 MachineBasicBlock *EntryMBB = MF->begin();
256 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
258 DenseMap<unsigned, unsigned> LiveInMap;
259 if (!FuncInfo->ArgDbgValues.empty())
260 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
261 E = RegInfo->livein_end(); LI != E; ++LI)
263 LiveInMap.insert(std::make_pair(LI->first, LI->second));
265 // Insert DBG_VALUE instructions for function arguments to the entry block.
266 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
267 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
268 unsigned Reg = MI->getOperand(0).getReg();
269 if (TargetRegisterInfo::isPhysicalRegister(Reg))
270 EntryMBB->insert(EntryMBB->begin(), MI);
272 MachineInstr *Def = RegInfo->getVRegDef(Reg);
273 MachineBasicBlock::iterator InsertPos = Def;
274 // FIXME: VR def may not be in entry block.
275 Def->getParent()->insert(llvm::next(InsertPos), MI);
278 // If Reg is live-in then update debug info to track its copy in a vreg.
279 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
280 if (LDI != LiveInMap.end()) {
281 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
282 MachineBasicBlock::iterator InsertPos = Def;
283 const MDNode *Variable =
284 MI->getOperand(MI->getNumOperands()-1).getMetadata();
285 unsigned Offset = MI->getOperand(1).getImm();
286 // Def is never a terminator here, so it is ok to increment InsertPos.
287 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
288 TII.get(TargetOpcode::DBG_VALUE))
289 .addReg(LDI->second, RegState::Debug)
290 .addImm(Offset).addMetadata(Variable);
294 // Determine if there are any calls in this machine function.
295 MachineFrameInfo *MFI = MF->getFrameInfo();
296 if (!MFI->hasCalls()) {
297 for (MachineFunction::const_iterator
298 I = MF->begin(), E = MF->end(); I != E; ++I) {
299 const MachineBasicBlock *MBB = I;
300 for (MachineBasicBlock::const_iterator
301 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
302 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
303 if (II->isInlineAsm() || (TID.isCall() && !TID.isReturn())) {
304 MFI->setHasCalls(true);
312 // Determine if there is a call to setjmp in the machine function.
313 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
315 // Release function-specific state. SDB and CurDAG are already cleared
323 SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB,
324 BasicBlock::const_iterator Begin,
325 BasicBlock::const_iterator End,
327 // Lower all of the non-terminator instructions. If a call is emitted
328 // as a tail call, cease emitting nodes for this block. Terminators
329 // are handled below.
330 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
333 // Make sure the root of the DAG is up-to-date.
334 CurDAG->setRoot(SDB->getControlRoot());
335 HadTailCall = SDB->HasTailCall;
338 // Final step, emit the lowered DAG as machine code.
339 return CodeGenAndEmitDAG(BB);
343 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
344 /// nodes from the worklist.
345 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
346 SmallVector<SDNode*, 128> &Worklist;
347 SmallPtrSet<SDNode*, 128> &InWorklist;
349 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
350 SmallPtrSet<SDNode*, 128> &inwl)
351 : Worklist(wl), InWorklist(inwl) {}
353 void RemoveFromWorklist(SDNode *N) {
354 if (!InWorklist.erase(N)) return;
356 SmallVector<SDNode*, 128>::iterator I =
357 std::find(Worklist.begin(), Worklist.end(), N);
358 assert(I != Worklist.end() && "Not in worklist");
360 *I = Worklist.back();
364 virtual void NodeDeleted(SDNode *N, SDNode *E) {
365 RemoveFromWorklist(N);
368 virtual void NodeUpdated(SDNode *N) {
374 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
375 SmallPtrSet<SDNode*, 128> VisitedNodes;
376 SmallVector<SDNode*, 128> Worklist;
378 Worklist.push_back(CurDAG->getRoot().getNode());
385 SDNode *N = Worklist.pop_back_val();
387 // If we've already seen this node, ignore it.
388 if (!VisitedNodes.insert(N))
391 // Otherwise, add all chain operands to the worklist.
392 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
393 if (N->getOperand(i).getValueType() == MVT::Other)
394 Worklist.push_back(N->getOperand(i).getNode());
396 // If this is a CopyToReg with a vreg dest, process it.
397 if (N->getOpcode() != ISD::CopyToReg)
400 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
401 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
404 // Ignore non-scalar or non-integer values.
405 SDValue Src = N->getOperand(2);
406 EVT SrcVT = Src.getValueType();
407 if (!SrcVT.isInteger() || SrcVT.isVector())
410 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
411 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
412 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
414 // Only install this information if it tells us something.
415 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
416 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
417 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
418 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
419 FunctionLoweringInfo::LiveOutInfo &LOI =
420 FuncInfo->LiveOutRegInfo[DestReg];
421 LOI.NumSignBits = NumSignBits;
422 LOI.KnownOne = KnownOne;
423 LOI.KnownZero = KnownZero;
425 } while (!Worklist.empty());
428 MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) {
429 std::string GroupName;
430 if (TimePassesIsEnabled)
431 GroupName = "Instruction Selection and Scheduling";
432 std::string BlockName;
433 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
434 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
436 BlockName = MF->getFunction()->getNameStr() + ":" +
437 BB->getBasicBlock()->getNameStr();
439 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
441 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
443 // Run the DAG combiner in pre-legalize mode.
445 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
446 CurDAG->Combine(Unrestricted, *AA, OptLevel);
449 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump());
451 // Second step, hack on the DAG until it only uses operations and types that
452 // the target supports.
453 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
458 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
459 Changed = CurDAG->LegalizeTypes();
462 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump());
465 if (ViewDAGCombineLT)
466 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
468 // Run the DAG combiner in post-type-legalize mode.
470 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
471 TimePassesIsEnabled);
472 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
475 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n";
480 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
481 Changed = CurDAG->LegalizeVectors();
486 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
487 CurDAG->LegalizeTypes();
490 if (ViewDAGCombineLT)
491 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
493 // Run the DAG combiner in post-type-legalize mode.
495 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
496 TimePassesIsEnabled);
497 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
500 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n";
504 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
507 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
508 CurDAG->Legalize(OptLevel);
511 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump());
513 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
515 // Run the DAG combiner in post-legalize mode.
517 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
518 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
521 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump());
523 if (OptLevel != CodeGenOpt::None)
524 ComputeLiveOutVRegInfo();
526 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
528 // Third, instruction select all of the operations to machine code, adding the
529 // code to the MachineBasicBlock.
531 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
532 DoInstructionSelection();
535 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump());
537 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
539 // Schedule machine code.
540 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
542 NamedRegionTimer T("Instruction Scheduling", GroupName,
543 TimePassesIsEnabled);
544 Scheduler->Run(CurDAG, BB, BB->end());
547 if (ViewSUnitDAGs) Scheduler->viewGraph();
549 // Emit machine code to BB. This can change 'BB' to the last block being
552 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
553 BB = Scheduler->EmitSchedule();
556 // Free the scheduler state.
558 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
559 TimePassesIsEnabled);
563 // Free the SelectionDAG state, now that we're finished with it.
569 void SelectionDAGISel::DoInstructionSelection() {
570 DEBUG(errs() << "===== Instruction selection begins:\n");
574 // Select target instructions for the DAG.
576 // Number all nodes with a topological order and set DAGSize.
577 DAGSize = CurDAG->AssignTopologicalOrder();
579 // Create a dummy node (which is not added to allnodes), that adds
580 // a reference to the root node, preventing it from being deleted,
581 // and tracking any changes of the root.
582 HandleSDNode Dummy(CurDAG->getRoot());
583 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
586 // The AllNodes list is now topological-sorted. Visit the
587 // nodes by starting at the end of the list (the root of the
588 // graph) and preceding back toward the beginning (the entry
590 while (ISelPosition != CurDAG->allnodes_begin()) {
591 SDNode *Node = --ISelPosition;
592 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
593 // but there are currently some corner cases that it misses. Also, this
594 // makes it theoretically possible to disable the DAGCombiner.
595 if (Node->use_empty())
598 SDNode *ResNode = Select(Node);
600 // FIXME: This is pretty gross. 'Select' should be changed to not return
601 // anything at all and this code should be nuked with a tactical strike.
603 // If node should not be replaced, continue with the next one.
604 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
608 ReplaceUses(Node, ResNode);
610 // If after the replacement this node is not used any more,
611 // remove this dead node.
612 if (Node->use_empty()) { // Don't delete EntryToken, etc.
613 ISelUpdater ISU(ISelPosition);
614 CurDAG->RemoveDeadNode(Node, &ISU);
618 CurDAG->setRoot(Dummy.getValue());
621 DEBUG(errs() << "===== Instruction selection ends:\n");
623 PostprocessISelDAG();
626 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
627 /// do other setup for EH landing-pad blocks.
628 void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) {
629 // Add a label to mark the beginning of the landing pad. Deletion of the
630 // landing pad can thus be detected via the MachineModuleInfo.
631 MCSymbol *Label = MF->getMMI().addLandingPad(BB);
633 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
634 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
636 // Mark exception register as live in.
637 unsigned Reg = TLI.getExceptionAddressRegister();
638 if (Reg) BB->addLiveIn(Reg);
640 // Mark exception selector register as live in.
641 Reg = TLI.getExceptionSelectorRegister();
642 if (Reg) BB->addLiveIn(Reg);
644 // FIXME: Hack around an exception handling flaw (PR1508): the personality
645 // function and list of typeids logically belong to the invoke (or, if you
646 // like, the basic block containing the invoke), and need to be associated
647 // with it in the dwarf exception handling tables. Currently however the
648 // information is provided by an intrinsic (eh.selector) that can be moved
649 // to unexpected places by the optimizers: if the unwind edge is critical,
650 // then breaking it can result in the intrinsics being in the successor of
651 // the landing pad, not the landing pad itself. This results
652 // in exceptions not being caught because no typeids are associated with
653 // the invoke. This may not be the only way things can go wrong, but it
654 // is the only way we try to work around for the moment.
655 const BasicBlock *LLVMBB = BB->getBasicBlock();
656 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
658 if (Br && Br->isUnconditional()) { // Critical edge?
659 BasicBlock::const_iterator I, E;
660 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
661 if (isa<EHSelectorInst>(I))
665 // No catch info found - try to extract some from the successor.
666 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
670 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
671 // Initialize the Fast-ISel state, if needed.
672 FastISel *FastIS = 0;
674 FastIS = TLI.createFastISel(*FuncInfo);
676 // Iterate over all basic blocks in the function.
677 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
678 const BasicBlock *LLVMBB = &*I;
679 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB];
681 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
682 BasicBlock::const_iterator const End = LLVMBB->end();
683 BasicBlock::const_iterator BI = Begin;
685 // Lower any arguments needed in this block if this is the entry block.
686 if (LLVMBB == &Fn.getEntryBlock())
687 LowerArguments(LLVMBB);
689 // Setup an EH landing-pad block.
690 if (BB->isLandingPad())
691 PrepareEHLandingPad(BB);
693 // Before doing SelectionDAG ISel, see if FastISel has been requested.
695 // Emit code for any incoming arguments. This must happen before
696 // beginning FastISel on the entry block.
697 if (LLVMBB == &Fn.getEntryBlock()) {
698 CurDAG->setRoot(SDB->getControlRoot());
700 BB = CodeGenAndEmitDAG(BB);
702 FastIS->startNewBlock(BB);
703 // Do FastISel on as many instructions as possible.
704 for (; BI != End; ++BI) {
706 // Defer instructions with no side effects; they'll be emitted
708 if (BI->isSafeToSpeculativelyExecute() &&
709 !FuncInfo->isExportedInst(BI))
713 // Try to select the instruction with FastISel.
714 if (FastIS->SelectInstruction(BI))
717 // Then handle certain instructions as single-LLVM-Instruction blocks.
718 if (isa<CallInst>(BI)) {
719 ++NumFastIselFailures;
720 if (EnableFastISelVerbose || EnableFastISelAbort) {
721 dbgs() << "FastISel missed call: ";
725 if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
726 unsigned &R = FuncInfo->ValueMap[BI];
728 R = FuncInfo->CreateRegs(BI->getType());
731 bool HadTailCall = false;
732 BB = SelectBasicBlock(BB, BI, llvm::next(BI), HadTailCall);
734 // If the call was emitted as a tail call, we're done with the block.
740 // If the instruction was codegen'd with multiple blocks,
741 // inform the FastISel object where to resume inserting.
742 FastIS->setCurrentBlock(BB);
746 // Otherwise, give up on FastISel for the rest of the block.
747 // For now, be a little lenient about non-branch terminators.
748 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
749 ++NumFastIselFailures;
750 if (EnableFastISelVerbose || EnableFastISelAbort) {
751 dbgs() << "FastISel miss: ";
754 if (EnableFastISelAbort)
755 // The "fast" selector couldn't handle something and bailed.
756 // For the purpose of debugging, just abort.
757 llvm_unreachable("FastISel didn't select the entire block");
763 // Run SelectionDAG instruction selection on the remainder of the block
764 // not handled by FastISel. If FastISel is not run, this is the entire
768 BB = SelectBasicBlock(BB, BI, End, HadTailCall);
771 FinishBasicBlock(BB);
772 FuncInfo->PHINodesToUpdate.clear();
779 SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) {
781 DEBUG(dbgs() << "Total amount of phi nodes to update: "
782 << FuncInfo->PHINodesToUpdate.size() << "\n";
783 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
784 dbgs() << "Node " << i << " : ("
785 << FuncInfo->PHINodesToUpdate[i].first
786 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
788 // Next, now that we know what the last MBB the LLVM BB expanded is, update
789 // PHI nodes in successors.
790 if (SDB->SwitchCases.empty() &&
791 SDB->JTCases.empty() &&
792 SDB->BitTestCases.empty()) {
793 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
794 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
795 assert(PHI->isPHI() &&
796 "This is not a machine PHI node that we are updating!");
797 if (!BB->isSuccessor(PHI->getParent()))
800 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
801 PHI->addOperand(MachineOperand::CreateMBB(BB));
806 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
807 // Lower header first, if it wasn't already lowered
808 if (!SDB->BitTestCases[i].Emitted) {
809 // Set the current basic block to the mbb we wish to insert the code into
810 BB = SDB->BitTestCases[i].Parent;
812 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB);
813 CurDAG->setRoot(SDB->getRoot());
815 BB = CodeGenAndEmitDAG(BB);
818 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
819 // Set the current basic block to the mbb we wish to insert the code into
820 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
823 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
824 SDB->BitTestCases[i].Reg,
825 SDB->BitTestCases[i].Cases[j],
828 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
829 SDB->BitTestCases[i].Reg,
830 SDB->BitTestCases[i].Cases[j],
834 CurDAG->setRoot(SDB->getRoot());
836 BB = CodeGenAndEmitDAG(BB);
840 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
842 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
843 MachineBasicBlock *PHIBB = PHI->getParent();
844 assert(PHI->isPHI() &&
845 "This is not a machine PHI node that we are updating!");
846 // This is "default" BB. We have two jumps to it. From "header" BB and
847 // from last "case" BB.
848 if (PHIBB == SDB->BitTestCases[i].Default) {
849 PHI->addOperand(MachineOperand::
850 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
852 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
853 PHI->addOperand(MachineOperand::
854 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
856 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
859 // One of "cases" BB.
860 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
862 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
863 if (cBB->isSuccessor(PHIBB)) {
864 PHI->addOperand(MachineOperand::
865 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
867 PHI->addOperand(MachineOperand::CreateMBB(cBB));
872 SDB->BitTestCases.clear();
874 // If the JumpTable record is filled in, then we need to emit a jump table.
875 // Updating the PHI nodes is tricky in this case, since we need to determine
876 // whether the PHI is a successor of the range check MBB or the jump table MBB
877 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
878 // Lower header first, if it wasn't already lowered
879 if (!SDB->JTCases[i].first.Emitted) {
880 // Set the current basic block to the mbb we wish to insert the code into
881 BB = SDB->JTCases[i].first.HeaderBB;
883 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
885 CurDAG->setRoot(SDB->getRoot());
887 BB = CodeGenAndEmitDAG(BB);
890 // Set the current basic block to the mbb we wish to insert the code into
891 BB = SDB->JTCases[i].second.MBB;
893 SDB->visitJumpTable(SDB->JTCases[i].second);
894 CurDAG->setRoot(SDB->getRoot());
896 BB = CodeGenAndEmitDAG(BB);
899 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
901 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
902 MachineBasicBlock *PHIBB = PHI->getParent();
903 assert(PHI->isPHI() &&
904 "This is not a machine PHI node that we are updating!");
905 // "default" BB. We can go there only from header BB.
906 if (PHIBB == SDB->JTCases[i].second.Default) {
908 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
911 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
913 // JT BB. Just iterate over successors here
914 if (BB->isSuccessor(PHIBB)) {
916 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
918 PHI->addOperand(MachineOperand::CreateMBB(BB));
922 SDB->JTCases.clear();
924 // If the switch block involved a branch to one of the actual successors, we
925 // need to update PHI nodes in that block.
926 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
927 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
928 assert(PHI->isPHI() &&
929 "This is not a machine PHI node that we are updating!");
930 if (BB->isSuccessor(PHI->getParent())) {
932 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
933 PHI->addOperand(MachineOperand::CreateMBB(BB));
937 // If we generated any switch lowering information, build and codegen any
938 // additional DAGs necessary.
939 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
940 // Set the current basic block to the mbb we wish to insert the code into
941 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
943 // Determine the unique successors.
944 SmallVector<MachineBasicBlock *, 2> Succs;
945 Succs.push_back(SDB->SwitchCases[i].TrueBB);
946 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
947 Succs.push_back(SDB->SwitchCases[i].FalseBB);
949 // Emit the code. Note that this could result in ThisBB being split, so
950 // we need to check for updates.
951 SDB->visitSwitchCase(SDB->SwitchCases[i], BB);
952 CurDAG->setRoot(SDB->getRoot());
954 ThisBB = CodeGenAndEmitDAG(BB);
956 // Handle any PHI nodes in successors of this chunk, as if we were coming
957 // from the original BB before switch expansion. Note that PHI nodes can
958 // occur multiple times in PHINodesToUpdate. We have to be very careful to
959 // handle them the right number of times.
960 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
962 // BB may have been removed from the CFG if a branch was constant folded.
963 if (ThisBB->isSuccessor(BB)) {
964 for (MachineBasicBlock::iterator Phi = BB->begin();
965 Phi != BB->end() && Phi->isPHI();
967 // This value for this PHI node is recorded in PHINodesToUpdate.
968 for (unsigned pn = 0; ; ++pn) {
969 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
970 "Didn't find PHI entry!");
971 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
972 Phi->addOperand(MachineOperand::
973 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
975 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
983 SDB->SwitchCases.clear();
987 /// Create the scheduler. If a specific scheduler was specified
988 /// via the SchedulerRegistry, use it, otherwise select the
989 /// one preferred by the target.
991 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
992 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
996 RegisterScheduler::setDefault(Ctor);
999 return Ctor(this, OptLevel);
1002 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1003 return new ScheduleHazardRecognizer();
1006 //===----------------------------------------------------------------------===//
1007 // Helper functions used by the generated instruction selector.
1008 //===----------------------------------------------------------------------===//
1009 // Calls to these methods are generated by tblgen.
1011 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1012 /// the dag combiner simplified the 255, we still want to match. RHS is the
1013 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1014 /// specified in the .td file (e.g. 255).
1015 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1016 int64_t DesiredMaskS) const {
1017 const APInt &ActualMask = RHS->getAPIntValue();
1018 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1020 // If the actual mask exactly matches, success!
1021 if (ActualMask == DesiredMask)
1024 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1025 if (ActualMask.intersects(~DesiredMask))
1028 // Otherwise, the DAG Combiner may have proven that the value coming in is
1029 // either already zero or is not demanded. Check for known zero input bits.
1030 APInt NeededMask = DesiredMask & ~ActualMask;
1031 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1034 // TODO: check to see if missing bits are just not demanded.
1036 // Otherwise, this pattern doesn't match.
1040 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1041 /// the dag combiner simplified the 255, we still want to match. RHS is the
1042 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1043 /// specified in the .td file (e.g. 255).
1044 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1045 int64_t DesiredMaskS) const {
1046 const APInt &ActualMask = RHS->getAPIntValue();
1047 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1049 // If the actual mask exactly matches, success!
1050 if (ActualMask == DesiredMask)
1053 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1054 if (ActualMask.intersects(~DesiredMask))
1057 // Otherwise, the DAG Combiner may have proven that the value coming in is
1058 // either already zero or is not demanded. Check for known zero input bits.
1059 APInt NeededMask = DesiredMask & ~ActualMask;
1061 APInt KnownZero, KnownOne;
1062 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1064 // If all the missing bits in the or are already known to be set, match!
1065 if ((NeededMask & KnownOne) == NeededMask)
1068 // TODO: check to see if missing bits are just not demanded.
1070 // Otherwise, this pattern doesn't match.
1075 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1076 /// by tblgen. Others should not call it.
1077 void SelectionDAGISel::
1078 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1079 std::vector<SDValue> InOps;
1080 std::swap(InOps, Ops);
1082 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1083 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1084 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1085 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3
1087 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1088 if (InOps[e-1].getValueType() == MVT::Flag)
1089 --e; // Don't process a flag operand if it is here.
1092 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1093 if (!InlineAsm::isMemKind(Flags)) {
1094 // Just skip over this operand, copying the operands verbatim.
1095 Ops.insert(Ops.end(), InOps.begin()+i,
1096 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1097 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1099 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1100 "Memory operand with multiple values?");
1101 // Otherwise, this is a memory operand. Ask the target to select it.
1102 std::vector<SDValue> SelOps;
1103 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1104 report_fatal_error("Could not match memory address. Inline asm"
1107 // Add this to the output node.
1109 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1110 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1111 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1116 // Add the flag input back if present.
1117 if (e != InOps.size())
1118 Ops.push_back(InOps.back());
1121 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1124 static SDNode *findFlagUse(SDNode *N) {
1125 unsigned FlagResNo = N->getNumValues()-1;
1126 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1127 SDUse &Use = I.getUse();
1128 if (Use.getResNo() == FlagResNo)
1129 return Use.getUser();
1134 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1135 /// This function recursively traverses up the operand chain, ignoring
1137 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1138 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1139 bool IgnoreChains) {
1140 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1141 // greater than all of its (recursive) operands. If we scan to a point where
1142 // 'use' is smaller than the node we're scanning for, then we know we will
1145 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1146 // happen because we scan down to newly selected nodes in the case of flag
1148 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1151 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1152 // won't fail if we scan it again.
1153 if (!Visited.insert(Use))
1156 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1157 // Ignore chain uses, they are validated by HandleMergeInputChains.
1158 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1161 SDNode *N = Use->getOperand(i).getNode();
1163 if (Use == ImmedUse || Use == Root)
1164 continue; // We are not looking for immediate use.
1169 // Traverse up the operand chain.
1170 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1176 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1177 /// operand node N of U during instruction selection that starts at Root.
1178 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1179 SDNode *Root) const {
1180 if (OptLevel == CodeGenOpt::None) return false;
1181 return N.hasOneUse();
1184 /// IsLegalToFold - Returns true if the specific operand node N of
1185 /// U can be folded during instruction selection that starts at Root.
1186 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1187 CodeGenOpt::Level OptLevel,
1188 bool IgnoreChains) {
1189 if (OptLevel == CodeGenOpt::None) return false;
1191 // If Root use can somehow reach N through a path that that doesn't contain
1192 // U then folding N would create a cycle. e.g. In the following
1193 // diagram, Root can reach N through X. If N is folded into into Root, then
1194 // X is both a predecessor and a successor of U.
1205 // * indicates nodes to be folded together.
1207 // If Root produces a flag, then it gets (even more) interesting. Since it
1208 // will be "glued" together with its flag use in the scheduler, we need to
1209 // check if it might reach N.
1228 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1229 // (call it Fold), then X is a predecessor of FU and a successor of
1230 // Fold. But since Fold and FU are flagged together, this will create
1231 // a cycle in the scheduling graph.
1233 // If the node has flags, walk down the graph to the "lowest" node in the
1235 EVT VT = Root->getValueType(Root->getNumValues()-1);
1236 while (VT == MVT::Flag) {
1237 SDNode *FU = findFlagUse(Root);
1241 VT = Root->getValueType(Root->getNumValues()-1);
1243 // If our query node has a flag result with a use, we've walked up it. If
1244 // the user (which has already been selected) has a chain or indirectly uses
1245 // the chain, our WalkChainUsers predicate will not consider it. Because of
1246 // this, we cannot ignore chains in this predicate.
1247 IgnoreChains = false;
1251 SmallPtrSet<SDNode*, 16> Visited;
1252 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1255 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1256 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1257 SelectInlineAsmMemoryOperands(Ops);
1259 std::vector<EVT> VTs;
1260 VTs.push_back(MVT::Other);
1261 VTs.push_back(MVT::Flag);
1262 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1263 VTs, &Ops[0], Ops.size());
1265 return New.getNode();
1268 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1269 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1272 /// GetVBR - decode a vbr encoding whose top bit is set.
1273 ALWAYS_INLINE static uint64_t
1274 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1275 assert(Val >= 128 && "Not a VBR");
1276 Val &= 127; // Remove first vbr bit.
1281 NextBits = MatcherTable[Idx++];
1282 Val |= (NextBits&127) << Shift;
1284 } while (NextBits & 128);
1290 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1291 /// interior flag and chain results to use the new flag and chain results.
1292 void SelectionDAGISel::
1293 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1294 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1296 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1297 bool isMorphNodeTo) {
1298 SmallVector<SDNode*, 4> NowDeadNodes;
1300 ISelUpdater ISU(ISelPosition);
1302 // Now that all the normal results are replaced, we replace the chain and
1303 // flag results if present.
1304 if (!ChainNodesMatched.empty()) {
1305 assert(InputChain.getNode() != 0 &&
1306 "Matched input chains but didn't produce a chain");
1307 // Loop over all of the nodes we matched that produced a chain result.
1308 // Replace all the chain results with the final chain we ended up with.
1309 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1310 SDNode *ChainNode = ChainNodesMatched[i];
1312 // If this node was already deleted, don't look at it.
1313 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1316 // Don't replace the results of the root node if we're doing a
1318 if (ChainNode == NodeToMatch && isMorphNodeTo)
1321 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1322 if (ChainVal.getValueType() == MVT::Flag)
1323 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1324 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1325 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1327 // If the node became dead and we haven't already seen it, delete it.
1328 if (ChainNode->use_empty() &&
1329 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1330 NowDeadNodes.push_back(ChainNode);
1334 // If the result produces a flag, update any flag results in the matched
1335 // pattern with the flag result.
1336 if (InputFlag.getNode() != 0) {
1337 // Handle any interior nodes explicitly marked.
1338 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1339 SDNode *FRN = FlagResultNodesMatched[i];
1341 // If this node was already deleted, don't look at it.
1342 if (FRN->getOpcode() == ISD::DELETED_NODE)
1345 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1346 "Doesn't have a flag result");
1347 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1350 // If the node became dead and we haven't already seen it, delete it.
1351 if (FRN->use_empty() &&
1352 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1353 NowDeadNodes.push_back(FRN);
1357 if (!NowDeadNodes.empty())
1358 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1360 DEBUG(errs() << "ISEL: Match complete!\n");
1366 CR_LeadsToInteriorNode
1369 /// WalkChainUsers - Walk down the users of the specified chained node that is
1370 /// part of the pattern we're matching, looking at all of the users we find.
1371 /// This determines whether something is an interior node, whether we have a
1372 /// non-pattern node in between two pattern nodes (which prevent folding because
1373 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1374 /// between pattern nodes (in which case the TF becomes part of the pattern).
1376 /// The walk we do here is guaranteed to be small because we quickly get down to
1377 /// already selected nodes "below" us.
1379 WalkChainUsers(SDNode *ChainedNode,
1380 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1381 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1382 ChainResult Result = CR_Simple;
1384 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1385 E = ChainedNode->use_end(); UI != E; ++UI) {
1386 // Make sure the use is of the chain, not some other value we produce.
1387 if (UI.getUse().getValueType() != MVT::Other) continue;
1391 // If we see an already-selected machine node, then we've gone beyond the
1392 // pattern that we're selecting down into the already selected chunk of the
1394 if (User->isMachineOpcode() ||
1395 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1398 if (User->getOpcode() == ISD::CopyToReg ||
1399 User->getOpcode() == ISD::CopyFromReg ||
1400 User->getOpcode() == ISD::INLINEASM ||
1401 User->getOpcode() == ISD::EH_LABEL) {
1402 // If their node ID got reset to -1 then they've already been selected.
1403 // Treat them like a MachineOpcode.
1404 if (User->getNodeId() == -1)
1408 // If we have a TokenFactor, we handle it specially.
1409 if (User->getOpcode() != ISD::TokenFactor) {
1410 // If the node isn't a token factor and isn't part of our pattern, then it
1411 // must be a random chained node in between two nodes we're selecting.
1412 // This happens when we have something like:
1417 // Because we structurally match the load/store as a read/modify/write,
1418 // but the call is chained between them. We cannot fold in this case
1419 // because it would induce a cycle in the graph.
1420 if (!std::count(ChainedNodesInPattern.begin(),
1421 ChainedNodesInPattern.end(), User))
1422 return CR_InducesCycle;
1424 // Otherwise we found a node that is part of our pattern. For example in:
1428 // This would happen when we're scanning down from the load and see the
1429 // store as a user. Record that there is a use of ChainedNode that is
1430 // part of the pattern and keep scanning uses.
1431 Result = CR_LeadsToInteriorNode;
1432 InteriorChainedNodes.push_back(User);
1436 // If we found a TokenFactor, there are two cases to consider: first if the
1437 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1438 // uses of the TF are in our pattern) we just want to ignore it. Second,
1439 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1445 // | \ DAG's like cheese
1448 // [TokenFactor] [Op]
1455 // In this case, the TokenFactor becomes part of our match and we rewrite it
1456 // as a new TokenFactor.
1458 // To distinguish these two cases, do a recursive walk down the uses.
1459 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1461 // If the uses of the TokenFactor are just already-selected nodes, ignore
1462 // it, it is "below" our pattern.
1464 case CR_InducesCycle:
1465 // If the uses of the TokenFactor lead to nodes that are not part of our
1466 // pattern that are not selected, folding would turn this into a cycle,
1468 return CR_InducesCycle;
1469 case CR_LeadsToInteriorNode:
1470 break; // Otherwise, keep processing.
1473 // Okay, we know we're in the interesting interior case. The TokenFactor
1474 // is now going to be considered part of the pattern so that we rewrite its
1475 // uses (it may have uses that are not part of the pattern) with the
1476 // ultimate chain result of the generated code. We will also add its chain
1477 // inputs as inputs to the ultimate TokenFactor we create.
1478 Result = CR_LeadsToInteriorNode;
1479 ChainedNodesInPattern.push_back(User);
1480 InteriorChainedNodes.push_back(User);
1487 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1488 /// operation for when the pattern matched at least one node with a chains. The
1489 /// input vector contains a list of all of the chained nodes that we match. We
1490 /// must determine if this is a valid thing to cover (i.e. matching it won't
1491 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1492 /// be used as the input node chain for the generated nodes.
1494 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1495 SelectionDAG *CurDAG) {
1496 // Walk all of the chained nodes we've matched, recursively scanning down the
1497 // users of the chain result. This adds any TokenFactor nodes that are caught
1498 // in between chained nodes to the chained and interior nodes list.
1499 SmallVector<SDNode*, 3> InteriorChainedNodes;
1500 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1501 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1502 InteriorChainedNodes) == CR_InducesCycle)
1503 return SDValue(); // Would induce a cycle.
1506 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1507 // that we are interested in. Form our input TokenFactor node.
1508 SmallVector<SDValue, 3> InputChains;
1509 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1510 // Add the input chain of this node to the InputChains list (which will be
1511 // the operands of the generated TokenFactor) if it's not an interior node.
1512 SDNode *N = ChainNodesMatched[i];
1513 if (N->getOpcode() != ISD::TokenFactor) {
1514 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1517 // Otherwise, add the input chain.
1518 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1519 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1520 InputChains.push_back(InChain);
1524 // If we have a token factor, we want to add all inputs of the token factor
1525 // that are not part of the pattern we're matching.
1526 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1527 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1528 N->getOperand(op).getNode()))
1529 InputChains.push_back(N->getOperand(op));
1534 if (InputChains.size() == 1)
1535 return InputChains[0];
1536 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1537 MVT::Other, &InputChains[0], InputChains.size());
1540 /// MorphNode - Handle morphing a node in place for the selector.
1541 SDNode *SelectionDAGISel::
1542 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1543 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1544 // It is possible we're using MorphNodeTo to replace a node with no
1545 // normal results with one that has a normal result (or we could be
1546 // adding a chain) and the input could have flags and chains as well.
1547 // In this case we need to shift the operands down.
1548 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1549 // than the old isel though.
1550 int OldFlagResultNo = -1, OldChainResultNo = -1;
1552 unsigned NTMNumResults = Node->getNumValues();
1553 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1554 OldFlagResultNo = NTMNumResults-1;
1555 if (NTMNumResults != 1 &&
1556 Node->getValueType(NTMNumResults-2) == MVT::Other)
1557 OldChainResultNo = NTMNumResults-2;
1558 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1559 OldChainResultNo = NTMNumResults-1;
1561 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1562 // that this deletes operands of the old node that become dead.
1563 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1565 // MorphNodeTo can operate in two ways: if an existing node with the
1566 // specified operands exists, it can just return it. Otherwise, it
1567 // updates the node in place to have the requested operands.
1569 // If we updated the node in place, reset the node ID. To the isel,
1570 // this should be just like a newly allocated machine node.
1574 unsigned ResNumResults = Res->getNumValues();
1575 // Move the flag if needed.
1576 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1577 (unsigned)OldFlagResultNo != ResNumResults-1)
1578 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1579 SDValue(Res, ResNumResults-1));
1581 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1584 // Move the chain reference if needed.
1585 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1586 (unsigned)OldChainResultNo != ResNumResults-1)
1587 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1588 SDValue(Res, ResNumResults-1));
1590 // Otherwise, no replacement happened because the node already exists. Replace
1591 // Uses of the old node with the new one.
1593 CurDAG->ReplaceAllUsesWith(Node, Res);
1598 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1599 ALWAYS_INLINE static bool
1600 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1601 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1602 // Accept if it is exactly the same as a previously recorded node.
1603 unsigned RecNo = MatcherTable[MatcherIndex++];
1604 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1605 return N == RecordedNodes[RecNo];
1608 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1609 ALWAYS_INLINE static bool
1610 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1611 SelectionDAGISel &SDISel) {
1612 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1615 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1616 ALWAYS_INLINE static bool
1617 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1618 SelectionDAGISel &SDISel, SDNode *N) {
1619 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1622 ALWAYS_INLINE static bool
1623 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1625 uint16_t Opc = MatcherTable[MatcherIndex++];
1626 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1627 return N->getOpcode() == Opc;
1630 ALWAYS_INLINE static bool
1631 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1632 SDValue N, const TargetLowering &TLI) {
1633 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1634 if (N.getValueType() == VT) return true;
1636 // Handle the case when VT is iPTR.
1637 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1640 ALWAYS_INLINE static bool
1641 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1642 SDValue N, const TargetLowering &TLI,
1644 if (ChildNo >= N.getNumOperands())
1645 return false; // Match fails if out of range child #.
1646 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1650 ALWAYS_INLINE static bool
1651 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1653 return cast<CondCodeSDNode>(N)->get() ==
1654 (ISD::CondCode)MatcherTable[MatcherIndex++];
1657 ALWAYS_INLINE static bool
1658 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1659 SDValue N, const TargetLowering &TLI) {
1660 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1661 if (cast<VTSDNode>(N)->getVT() == VT)
1664 // Handle the case when VT is iPTR.
1665 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1668 ALWAYS_INLINE static bool
1669 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1671 int64_t Val = MatcherTable[MatcherIndex++];
1673 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1675 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1676 return C != 0 && C->getSExtValue() == Val;
1679 ALWAYS_INLINE static bool
1680 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1681 SDValue N, SelectionDAGISel &SDISel) {
1682 int64_t Val = MatcherTable[MatcherIndex++];
1684 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1686 if (N->getOpcode() != ISD::AND) return false;
1688 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1689 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1692 ALWAYS_INLINE static bool
1693 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1694 SDValue N, SelectionDAGISel &SDISel) {
1695 int64_t Val = MatcherTable[MatcherIndex++];
1697 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1699 if (N->getOpcode() != ISD::OR) return false;
1701 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1702 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1705 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1706 /// scope, evaluate the current node. If the current predicate is known to
1707 /// fail, set Result=true and return anything. If the current predicate is
1708 /// known to pass, set Result=false and return the MatcherIndex to continue
1709 /// with. If the current predicate is unknown, set Result=false and return the
1710 /// MatcherIndex to continue with.
1711 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1712 unsigned Index, SDValue N,
1713 bool &Result, SelectionDAGISel &SDISel,
1714 SmallVectorImpl<SDValue> &RecordedNodes){
1715 switch (Table[Index++]) {
1718 return Index-1; // Could not evaluate this predicate.
1719 case SelectionDAGISel::OPC_CheckSame:
1720 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1722 case SelectionDAGISel::OPC_CheckPatternPredicate:
1723 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1725 case SelectionDAGISel::OPC_CheckPredicate:
1726 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1728 case SelectionDAGISel::OPC_CheckOpcode:
1729 Result = !::CheckOpcode(Table, Index, N.getNode());
1731 case SelectionDAGISel::OPC_CheckType:
1732 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1734 case SelectionDAGISel::OPC_CheckChild0Type:
1735 case SelectionDAGISel::OPC_CheckChild1Type:
1736 case SelectionDAGISel::OPC_CheckChild2Type:
1737 case SelectionDAGISel::OPC_CheckChild3Type:
1738 case SelectionDAGISel::OPC_CheckChild4Type:
1739 case SelectionDAGISel::OPC_CheckChild5Type:
1740 case SelectionDAGISel::OPC_CheckChild6Type:
1741 case SelectionDAGISel::OPC_CheckChild7Type:
1742 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1743 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1745 case SelectionDAGISel::OPC_CheckCondCode:
1746 Result = !::CheckCondCode(Table, Index, N);
1748 case SelectionDAGISel::OPC_CheckValueType:
1749 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1751 case SelectionDAGISel::OPC_CheckInteger:
1752 Result = !::CheckInteger(Table, Index, N);
1754 case SelectionDAGISel::OPC_CheckAndImm:
1755 Result = !::CheckAndImm(Table, Index, N, SDISel);
1757 case SelectionDAGISel::OPC_CheckOrImm:
1758 Result = !::CheckOrImm(Table, Index, N, SDISel);
1766 /// FailIndex - If this match fails, this is the index to continue with.
1769 /// NodeStack - The node stack when the scope was formed.
1770 SmallVector<SDValue, 4> NodeStack;
1772 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1773 unsigned NumRecordedNodes;
1775 /// NumMatchedMemRefs - The number of matched memref entries.
1776 unsigned NumMatchedMemRefs;
1778 /// InputChain/InputFlag - The current chain/flag
1779 SDValue InputChain, InputFlag;
1781 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1782 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1787 SDNode *SelectionDAGISel::
1788 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1789 unsigned TableSize) {
1790 // FIXME: Should these even be selected? Handle these cases in the caller?
1791 switch (NodeToMatch->getOpcode()) {
1794 case ISD::EntryToken: // These nodes remain the same.
1795 case ISD::BasicBlock:
1797 //case ISD::VALUETYPE:
1798 //case ISD::CONDCODE:
1799 case ISD::HANDLENODE:
1800 case ISD::MDNODE_SDNODE:
1801 case ISD::TargetConstant:
1802 case ISD::TargetConstantFP:
1803 case ISD::TargetConstantPool:
1804 case ISD::TargetFrameIndex:
1805 case ISD::TargetExternalSymbol:
1806 case ISD::TargetBlockAddress:
1807 case ISD::TargetJumpTable:
1808 case ISD::TargetGlobalTLSAddress:
1809 case ISD::TargetGlobalAddress:
1810 case ISD::TokenFactor:
1811 case ISD::CopyFromReg:
1812 case ISD::CopyToReg:
1814 NodeToMatch->setNodeId(-1); // Mark selected.
1816 case ISD::AssertSext:
1817 case ISD::AssertZext:
1818 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1819 NodeToMatch->getOperand(0));
1821 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1822 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1825 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1827 // Set up the node stack with NodeToMatch as the only node on the stack.
1828 SmallVector<SDValue, 8> NodeStack;
1829 SDValue N = SDValue(NodeToMatch, 0);
1830 NodeStack.push_back(N);
1832 // MatchScopes - Scopes used when matching, if a match failure happens, this
1833 // indicates where to continue checking.
1834 SmallVector<MatchScope, 8> MatchScopes;
1836 // RecordedNodes - This is the set of nodes that have been recorded by the
1838 SmallVector<SDValue, 8> RecordedNodes;
1840 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1842 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1844 // These are the current input chain and flag for use when generating nodes.
1845 // Various Emit operations change these. For example, emitting a copytoreg
1846 // uses and updates these.
1847 SDValue InputChain, InputFlag;
1849 // ChainNodesMatched - If a pattern matches nodes that have input/output
1850 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1851 // which ones they are. The result is captured into this list so that we can
1852 // update the chain results when the pattern is complete.
1853 SmallVector<SDNode*, 3> ChainNodesMatched;
1854 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1856 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1857 NodeToMatch->dump(CurDAG);
1860 // Determine where to start the interpreter. Normally we start at opcode #0,
1861 // but if the state machine starts with an OPC_SwitchOpcode, then we
1862 // accelerate the first lookup (which is guaranteed to be hot) with the
1863 // OpcodeOffset table.
1864 unsigned MatcherIndex = 0;
1866 if (!OpcodeOffset.empty()) {
1867 // Already computed the OpcodeOffset table, just index into it.
1868 if (N.getOpcode() < OpcodeOffset.size())
1869 MatcherIndex = OpcodeOffset[N.getOpcode()];
1870 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1872 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1873 // Otherwise, the table isn't computed, but the state machine does start
1874 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1875 // is the first time we're selecting an instruction.
1878 // Get the size of this case.
1879 unsigned CaseSize = MatcherTable[Idx++];
1881 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1882 if (CaseSize == 0) break;
1884 // Get the opcode, add the index to the table.
1885 uint16_t Opc = MatcherTable[Idx++];
1886 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1887 if (Opc >= OpcodeOffset.size())
1888 OpcodeOffset.resize((Opc+1)*2);
1889 OpcodeOffset[Opc] = Idx;
1893 // Okay, do the lookup for the first opcode.
1894 if (N.getOpcode() < OpcodeOffset.size())
1895 MatcherIndex = OpcodeOffset[N.getOpcode()];
1899 assert(MatcherIndex < TableSize && "Invalid index");
1901 unsigned CurrentOpcodeIndex = MatcherIndex;
1903 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1906 // Okay, the semantics of this operation are that we should push a scope
1907 // then evaluate the first child. However, pushing a scope only to have
1908 // the first check fail (which then pops it) is inefficient. If we can
1909 // determine immediately that the first check (or first several) will
1910 // immediately fail, don't even bother pushing a scope for them.
1914 unsigned NumToSkip = MatcherTable[MatcherIndex++];
1915 if (NumToSkip & 128)
1916 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
1917 // Found the end of the scope with no match.
1918 if (NumToSkip == 0) {
1923 FailIndex = MatcherIndex+NumToSkip;
1925 unsigned MatcherIndexOfPredicate = MatcherIndex;
1926 (void)MatcherIndexOfPredicate; // silence warning.
1928 // If we can't evaluate this predicate without pushing a scope (e.g. if
1929 // it is a 'MoveParent') or if the predicate succeeds on this node, we
1930 // push the scope and evaluate the full predicate chain.
1932 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
1933 Result, *this, RecordedNodes);
1937 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
1938 << "index " << MatcherIndexOfPredicate
1939 << ", continuing at " << FailIndex << "\n");
1940 ++NumDAGIselRetries;
1942 // Otherwise, we know that this case of the Scope is guaranteed to fail,
1943 // move to the next case.
1944 MatcherIndex = FailIndex;
1947 // If the whole scope failed to match, bail.
1948 if (FailIndex == 0) break;
1950 // Push a MatchScope which indicates where to go if the first child fails
1952 MatchScope NewEntry;
1953 NewEntry.FailIndex = FailIndex;
1954 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
1955 NewEntry.NumRecordedNodes = RecordedNodes.size();
1956 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
1957 NewEntry.InputChain = InputChain;
1958 NewEntry.InputFlag = InputFlag;
1959 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
1960 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
1961 MatchScopes.push_back(NewEntry);
1964 case OPC_RecordNode:
1965 // Remember this node, it may end up being an operand in the pattern.
1966 RecordedNodes.push_back(N);
1969 case OPC_RecordChild0: case OPC_RecordChild1:
1970 case OPC_RecordChild2: case OPC_RecordChild3:
1971 case OPC_RecordChild4: case OPC_RecordChild5:
1972 case OPC_RecordChild6: case OPC_RecordChild7: {
1973 unsigned ChildNo = Opcode-OPC_RecordChild0;
1974 if (ChildNo >= N.getNumOperands())
1975 break; // Match fails if out of range child #.
1977 RecordedNodes.push_back(N->getOperand(ChildNo));
1980 case OPC_RecordMemRef:
1981 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
1984 case OPC_CaptureFlagInput:
1985 // If the current node has an input flag, capture it in InputFlag.
1986 if (N->getNumOperands() != 0 &&
1987 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
1988 InputFlag = N->getOperand(N->getNumOperands()-1);
1991 case OPC_MoveChild: {
1992 unsigned ChildNo = MatcherTable[MatcherIndex++];
1993 if (ChildNo >= N.getNumOperands())
1994 break; // Match fails if out of range child #.
1995 N = N.getOperand(ChildNo);
1996 NodeStack.push_back(N);
2000 case OPC_MoveParent:
2001 // Pop the current node off the NodeStack.
2002 NodeStack.pop_back();
2003 assert(!NodeStack.empty() && "Node stack imbalance!");
2004 N = NodeStack.back();
2008 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2010 case OPC_CheckPatternPredicate:
2011 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2013 case OPC_CheckPredicate:
2014 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2018 case OPC_CheckComplexPat: {
2019 unsigned CPNum = MatcherTable[MatcherIndex++];
2020 unsigned RecNo = MatcherTable[MatcherIndex++];
2021 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2022 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2027 case OPC_CheckOpcode:
2028 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2032 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2035 case OPC_SwitchOpcode: {
2036 unsigned CurNodeOpcode = N.getOpcode();
2037 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2040 // Get the size of this case.
2041 CaseSize = MatcherTable[MatcherIndex++];
2043 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2044 if (CaseSize == 0) break;
2046 uint16_t Opc = MatcherTable[MatcherIndex++];
2047 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2049 // If the opcode matches, then we will execute this case.
2050 if (CurNodeOpcode == Opc)
2053 // Otherwise, skip over this case.
2054 MatcherIndex += CaseSize;
2057 // If no cases matched, bail out.
2058 if (CaseSize == 0) break;
2060 // Otherwise, execute the case we found.
2061 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2062 << " to " << MatcherIndex << "\n");
2066 case OPC_SwitchType: {
2067 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2068 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2071 // Get the size of this case.
2072 CaseSize = MatcherTable[MatcherIndex++];
2074 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2075 if (CaseSize == 0) break;
2077 MVT::SimpleValueType CaseVT =
2078 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2079 if (CaseVT == MVT::iPTR)
2080 CaseVT = TLI.getPointerTy().SimpleTy;
2082 // If the VT matches, then we will execute this case.
2083 if (CurNodeVT == CaseVT)
2086 // Otherwise, skip over this case.
2087 MatcherIndex += CaseSize;
2090 // If no cases matched, bail out.
2091 if (CaseSize == 0) break;
2093 // Otherwise, execute the case we found.
2094 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2095 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2098 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2099 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2100 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2101 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2102 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2103 Opcode-OPC_CheckChild0Type))
2106 case OPC_CheckCondCode:
2107 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2109 case OPC_CheckValueType:
2110 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2112 case OPC_CheckInteger:
2113 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2115 case OPC_CheckAndImm:
2116 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2118 case OPC_CheckOrImm:
2119 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2122 case OPC_CheckFoldableChainNode: {
2123 assert(NodeStack.size() != 1 && "No parent node");
2124 // Verify that all intermediate nodes between the root and this one have
2126 bool HasMultipleUses = false;
2127 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2128 if (!NodeStack[i].hasOneUse()) {
2129 HasMultipleUses = true;
2132 if (HasMultipleUses) break;
2134 // Check to see that the target thinks this is profitable to fold and that
2135 // we can fold it without inducing cycles in the graph.
2136 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2138 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2139 NodeToMatch, OptLevel,
2140 true/*We validate our own chains*/))
2145 case OPC_EmitInteger: {
2146 MVT::SimpleValueType VT =
2147 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2148 int64_t Val = MatcherTable[MatcherIndex++];
2150 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2151 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2154 case OPC_EmitRegister: {
2155 MVT::SimpleValueType VT =
2156 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2157 unsigned RegNo = MatcherTable[MatcherIndex++];
2158 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2162 case OPC_EmitConvertToTarget: {
2163 // Convert from IMM/FPIMM to target version.
2164 unsigned RecNo = MatcherTable[MatcherIndex++];
2165 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2166 SDValue Imm = RecordedNodes[RecNo];
2168 if (Imm->getOpcode() == ISD::Constant) {
2169 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2170 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2171 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2172 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2173 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2176 RecordedNodes.push_back(Imm);
2180 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2181 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2182 // These are space-optimized forms of OPC_EmitMergeInputChains.
2183 assert(InputChain.getNode() == 0 &&
2184 "EmitMergeInputChains should be the first chain producing node");
2185 assert(ChainNodesMatched.empty() &&
2186 "Should only have one EmitMergeInputChains per match");
2188 // Read all of the chained nodes.
2189 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2190 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2191 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2193 // FIXME: What if other value results of the node have uses not matched
2195 if (ChainNodesMatched.back() != NodeToMatch &&
2196 !RecordedNodes[RecNo].hasOneUse()) {
2197 ChainNodesMatched.clear();
2201 // Merge the input chains if they are not intra-pattern references.
2202 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2204 if (InputChain.getNode() == 0)
2205 break; // Failed to merge.
2209 case OPC_EmitMergeInputChains: {
2210 assert(InputChain.getNode() == 0 &&
2211 "EmitMergeInputChains should be the first chain producing node");
2212 // This node gets a list of nodes we matched in the input that have
2213 // chains. We want to token factor all of the input chains to these nodes
2214 // together. However, if any of the input chains is actually one of the
2215 // nodes matched in this pattern, then we have an intra-match reference.
2216 // Ignore these because the newly token factored chain should not refer to
2218 unsigned NumChains = MatcherTable[MatcherIndex++];
2219 assert(NumChains != 0 && "Can't TF zero chains");
2221 assert(ChainNodesMatched.empty() &&
2222 "Should only have one EmitMergeInputChains per match");
2224 // Read all of the chained nodes.
2225 for (unsigned i = 0; i != NumChains; ++i) {
2226 unsigned RecNo = MatcherTable[MatcherIndex++];
2227 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2228 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2230 // FIXME: What if other value results of the node have uses not matched
2232 if (ChainNodesMatched.back() != NodeToMatch &&
2233 !RecordedNodes[RecNo].hasOneUse()) {
2234 ChainNodesMatched.clear();
2239 // If the inner loop broke out, the match fails.
2240 if (ChainNodesMatched.empty())
2243 // Merge the input chains if they are not intra-pattern references.
2244 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2246 if (InputChain.getNode() == 0)
2247 break; // Failed to merge.
2252 case OPC_EmitCopyToReg: {
2253 unsigned RecNo = MatcherTable[MatcherIndex++];
2254 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2255 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2257 if (InputChain.getNode() == 0)
2258 InputChain = CurDAG->getEntryNode();
2260 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2261 DestPhysReg, RecordedNodes[RecNo],
2264 InputFlag = InputChain.getValue(1);
2268 case OPC_EmitNodeXForm: {
2269 unsigned XFormNo = MatcherTable[MatcherIndex++];
2270 unsigned RecNo = MatcherTable[MatcherIndex++];
2271 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2272 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2277 case OPC_MorphNodeTo: {
2278 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2279 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2280 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2281 // Get the result VT list.
2282 unsigned NumVTs = MatcherTable[MatcherIndex++];
2283 SmallVector<EVT, 4> VTs;
2284 for (unsigned i = 0; i != NumVTs; ++i) {
2285 MVT::SimpleValueType VT =
2286 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2287 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2291 if (EmitNodeInfo & OPFL_Chain)
2292 VTs.push_back(MVT::Other);
2293 if (EmitNodeInfo & OPFL_FlagOutput)
2294 VTs.push_back(MVT::Flag);
2296 // This is hot code, so optimize the two most common cases of 1 and 2
2299 if (VTs.size() == 1)
2300 VTList = CurDAG->getVTList(VTs[0]);
2301 else if (VTs.size() == 2)
2302 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2304 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2306 // Get the operand list.
2307 unsigned NumOps = MatcherTable[MatcherIndex++];
2308 SmallVector<SDValue, 8> Ops;
2309 for (unsigned i = 0; i != NumOps; ++i) {
2310 unsigned RecNo = MatcherTable[MatcherIndex++];
2312 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2314 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2315 Ops.push_back(RecordedNodes[RecNo]);
2318 // If there are variadic operands to add, handle them now.
2319 if (EmitNodeInfo & OPFL_VariadicInfo) {
2320 // Determine the start index to copy from.
2321 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2322 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2323 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2324 "Invalid variadic node");
2325 // Copy all of the variadic operands, not including a potential flag
2327 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2329 SDValue V = NodeToMatch->getOperand(i);
2330 if (V.getValueType() == MVT::Flag) break;
2335 // If this has chain/flag inputs, add them.
2336 if (EmitNodeInfo & OPFL_Chain)
2337 Ops.push_back(InputChain);
2338 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2339 Ops.push_back(InputFlag);
2343 if (Opcode != OPC_MorphNodeTo) {
2344 // If this is a normal EmitNode command, just create the new node and
2345 // add the results to the RecordedNodes list.
2346 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2347 VTList, Ops.data(), Ops.size());
2349 // Add all the non-flag/non-chain results to the RecordedNodes list.
2350 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2351 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2352 RecordedNodes.push_back(SDValue(Res, i));
2356 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2360 // If the node had chain/flag results, update our notion of the current
2362 if (EmitNodeInfo & OPFL_FlagOutput) {
2363 InputFlag = SDValue(Res, VTs.size()-1);
2364 if (EmitNodeInfo & OPFL_Chain)
2365 InputChain = SDValue(Res, VTs.size()-2);
2366 } else if (EmitNodeInfo & OPFL_Chain)
2367 InputChain = SDValue(Res, VTs.size()-1);
2369 // If the OPFL_MemRefs flag is set on this node, slap all of the
2370 // accumulated memrefs onto it.
2372 // FIXME: This is vastly incorrect for patterns with multiple outputs
2373 // instructions that access memory and for ComplexPatterns that match
2375 if (EmitNodeInfo & OPFL_MemRefs) {
2376 MachineSDNode::mmo_iterator MemRefs =
2377 MF->allocateMemRefsArray(MatchedMemRefs.size());
2378 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2379 cast<MachineSDNode>(Res)
2380 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2384 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2385 << " node: "; Res->dump(CurDAG); errs() << "\n");
2387 // If this was a MorphNodeTo then we're completely done!
2388 if (Opcode == OPC_MorphNodeTo) {
2389 // Update chain and flag uses.
2390 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2391 InputFlag, FlagResultNodesMatched, true);
2398 case OPC_MarkFlagResults: {
2399 unsigned NumNodes = MatcherTable[MatcherIndex++];
2401 // Read and remember all the flag-result nodes.
2402 for (unsigned i = 0; i != NumNodes; ++i) {
2403 unsigned RecNo = MatcherTable[MatcherIndex++];
2405 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2407 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2408 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2413 case OPC_CompleteMatch: {
2414 // The match has been completed, and any new nodes (if any) have been
2415 // created. Patch up references to the matched dag to use the newly
2417 unsigned NumResults = MatcherTable[MatcherIndex++];
2419 for (unsigned i = 0; i != NumResults; ++i) {
2420 unsigned ResSlot = MatcherTable[MatcherIndex++];
2422 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2424 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2425 SDValue Res = RecordedNodes[ResSlot];
2427 assert(i < NodeToMatch->getNumValues() &&
2428 NodeToMatch->getValueType(i) != MVT::Other &&
2429 NodeToMatch->getValueType(i) != MVT::Flag &&
2430 "Invalid number of results to complete!");
2431 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2432 NodeToMatch->getValueType(i) == MVT::iPTR ||
2433 Res.getValueType() == MVT::iPTR ||
2434 NodeToMatch->getValueType(i).getSizeInBits() ==
2435 Res.getValueType().getSizeInBits()) &&
2436 "invalid replacement");
2437 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2440 // If the root node defines a flag, add it to the flag nodes to update
2442 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2443 FlagResultNodesMatched.push_back(NodeToMatch);
2445 // Update chain and flag uses.
2446 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2447 InputFlag, FlagResultNodesMatched, false);
2449 assert(NodeToMatch->use_empty() &&
2450 "Didn't replace all uses of the node?");
2452 // FIXME: We just return here, which interacts correctly with SelectRoot
2453 // above. We should fix this to not return an SDNode* anymore.
2458 // If the code reached this point, then the match failed. See if there is
2459 // another child to try in the current 'Scope', otherwise pop it until we
2460 // find a case to check.
2461 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2462 ++NumDAGIselRetries;
2464 if (MatchScopes.empty()) {
2465 CannotYetSelect(NodeToMatch);
2469 // Restore the interpreter state back to the point where the scope was
2471 MatchScope &LastScope = MatchScopes.back();
2472 RecordedNodes.resize(LastScope.NumRecordedNodes);
2474 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2475 N = NodeStack.back();
2477 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2478 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2479 MatcherIndex = LastScope.FailIndex;
2481 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2483 InputChain = LastScope.InputChain;
2484 InputFlag = LastScope.InputFlag;
2485 if (!LastScope.HasChainNodesMatched)
2486 ChainNodesMatched.clear();
2487 if (!LastScope.HasFlagResultNodesMatched)
2488 FlagResultNodesMatched.clear();
2490 // Check to see what the offset is at the new MatcherIndex. If it is zero
2491 // we have reached the end of this scope, otherwise we have another child
2492 // in the current scope to try.
2493 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2494 if (NumToSkip & 128)
2495 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2497 // If we have another child in this scope to match, update FailIndex and
2499 if (NumToSkip != 0) {
2500 LastScope.FailIndex = MatcherIndex+NumToSkip;
2504 // End of this scope, pop it and try the next child in the containing
2506 MatchScopes.pop_back();
2513 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2515 raw_string_ostream Msg(msg);
2516 Msg << "Cannot yet select: ";
2518 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2519 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2520 N->getOpcode() != ISD::INTRINSIC_VOID) {
2521 N->printrFull(Msg, CurDAG);
2523 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2525 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2526 if (iid < Intrinsic::num_intrinsics)
2527 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2528 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2529 Msg << "target intrinsic %" << TII->getName(iid);
2531 Msg << "unknown intrinsic #" << iid;
2533 report_fatal_error(Msg.str());
2536 char SelectionDAGISel::ID = 0;