1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetIntrinsicInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/ADT/Statistic.h"
53 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
54 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
57 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
58 cl::desc("Enable verbose messages in the \"fast\" "
59 "instruction selector"));
61 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
62 cl::desc("Enable abort calls when \"fast\" instruction fails"));
66 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
67 cl::desc("Pop up a window to show dags before the first "
70 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
71 cl::desc("Pop up a window to show dags before legalize types"));
73 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
74 cl::desc("Pop up a window to show dags before legalize"));
76 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
77 cl::desc("Pop up a window to show dags before the second "
80 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before the post legalize types"
82 " dag combine pass"));
84 ViewISelDAGs("view-isel-dags", cl::Hidden,
85 cl::desc("Pop up a window to show isel dags as they are selected"));
87 ViewSchedDAGs("view-sched-dags", cl::Hidden,
88 cl::desc("Pop up a window to show sched dags as they are processed"));
90 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
91 cl::desc("Pop up a window to show SUnit dags after they are processed"));
93 static const bool ViewDAGCombine1 = false,
94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
95 ViewDAGCombine2 = false,
96 ViewDAGCombineLT = false,
97 ViewISelDAGs = false, ViewSchedDAGs = false,
98 ViewSUnitDAGs = false;
101 //===---------------------------------------------------------------------===//
103 /// RegisterScheduler class - Track the registration of instruction schedulers.
105 //===---------------------------------------------------------------------===//
106 MachinePassRegistry RegisterScheduler::Registry;
108 //===---------------------------------------------------------------------===//
110 /// ISHeuristic command line option for instruction schedulers.
112 //===---------------------------------------------------------------------===//
113 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
114 RegisterPassParser<RegisterScheduler> >
115 ISHeuristic("pre-RA-sched",
116 cl::init(&createDefaultScheduler),
117 cl::desc("Instruction schedulers available (before register"
120 static RegisterScheduler
121 defaultListDAGScheduler("default", "Best scheduler for the target",
122 createDefaultScheduler);
125 //===--------------------------------------------------------------------===//
126 /// createDefaultScheduler - This creates an instruction scheduler appropriate
128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
129 CodeGenOpt::Level OptLevel) {
130 const TargetLowering &TLI = IS->getTargetLowering();
132 if (OptLevel == CodeGenOpt::None)
133 return createFastDAGScheduler(IS, OptLevel);
134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
135 return createTDListDAGScheduler(IS, OptLevel);
136 assert(TLI.getSchedulingPreference() ==
137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
138 return createBURRListDAGScheduler(IS, OptLevel);
142 // EmitInstrWithCustomInserter - This method should be implemented by targets
143 // that mark instructions with the 'usesCustomInserter' flag. These
144 // instructions are special in various ways, which require special support to
145 // insert. The specified MachineInstr is created but not inserted into any
146 // basic blocks, and this method is called to expand it into a sequence of
147 // instructions, potentially also creating new basic blocks and control flow.
148 // When new basic blocks are inserted and the edges from MBB to its successors
149 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
151 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
152 MachineBasicBlock *MBB,
153 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
155 dbgs() << "If a target marks an instruction with "
156 "'usesCustomInserter', it must implement "
157 "TargetLowering::EmitInstrWithCustomInserter!";
163 //===----------------------------------------------------------------------===//
164 // SelectionDAGISel code
165 //===----------------------------------------------------------------------===//
167 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
169 FuncInfo(new FunctionLoweringInfo(TLI)),
170 CurDAG(new SelectionDAG(tm, *FuncInfo)),
171 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
177 SelectionDAGISel::~SelectionDAGISel() {
183 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
184 AU.addRequired<AliasAnalysis>();
185 AU.addPreserved<AliasAnalysis>();
186 AU.addRequired<GCModuleInfo>();
187 AU.addPreserved<GCModuleInfo>();
188 MachineFunctionPass::getAnalysisUsage(AU);
191 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
192 // Do some sanity-checking on the command-line options.
193 assert((!EnableFastISelVerbose || EnableFastISel) &&
194 "-fast-isel-verbose requires -fast-isel");
195 assert((!EnableFastISelAbort || EnableFastISel) &&
196 "-fast-isel-abort requires -fast-isel");
198 const Function &Fn = *mf.getFunction();
199 const TargetInstrInfo &TII = *TM.getInstrInfo();
200 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
203 RegInfo = &MF->getRegInfo();
204 AA = &getAnalysis<AliasAnalysis>();
205 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
207 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
210 FuncInfo->set(Fn, *MF, EnableFastISel);
213 SelectAllBasicBlocks(Fn);
215 // Release function-specific state. SDB and CurDAG are already cleared
219 // If the first basic block in the function has live ins that need to be
220 // copied into vregs, emit the copies into the top of the block before
221 // emitting the code for the block.
222 RegInfo->EmitLiveInCopies(MF->begin(), TRI, TII);
228 SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB,
229 const BasicBlock *LLVMBB,
230 BasicBlock::const_iterator Begin,
231 BasicBlock::const_iterator End,
233 // Lower all of the non-terminator instructions. If a call is emitted
234 // as a tail call, cease emitting nodes for this block. Terminators
235 // are handled below.
236 for (BasicBlock::const_iterator I = Begin;
237 I != End && !SDB->HasTailCall && !isa<TerminatorInst>(I);
241 if (!SDB->HasTailCall) {
242 // Handle PHI nodes in successor blocks.
243 if (End == LLVMBB->end()) {
244 HandlePHINodesInSuccessorBlocks(LLVMBB);
246 // Lower the terminator after the copies are emitted.
247 SDB->visit(*LLVMBB->getTerminator());
251 // Make sure the root of the DAG is up-to-date.
252 CurDAG->setRoot(SDB->getControlRoot());
254 // Final step, emit the lowered DAG as machine code.
255 BB = CodeGenAndEmitDAG(BB);
256 HadTailCall = SDB->HasTailCall;
262 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
263 /// nodes from the worklist.
264 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
265 SmallVector<SDNode*, 128> &Worklist;
266 SmallPtrSet<SDNode*, 128> &InWorklist;
268 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
269 SmallPtrSet<SDNode*, 128> &inwl)
270 : Worklist(wl), InWorklist(inwl) {}
272 void RemoveFromWorklist(SDNode *N) {
273 if (!InWorklist.erase(N)) return;
275 SmallVector<SDNode*, 128>::iterator I =
276 std::find(Worklist.begin(), Worklist.end(), N);
277 assert(I != Worklist.end() && "Not in worklist");
279 *I = Worklist.back();
283 virtual void NodeDeleted(SDNode *N, SDNode *E) {
284 RemoveFromWorklist(N);
287 virtual void NodeUpdated(SDNode *N) {
293 /// TrivialTruncElim - Eliminate some trivial nops that can result from
294 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
295 static bool TrivialTruncElim(SDValue Op,
296 TargetLowering::TargetLoweringOpt &TLO) {
297 SDValue N0 = Op.getOperand(0);
298 EVT VT = Op.getValueType();
299 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
300 N0.getOpcode() == ISD::SIGN_EXTEND ||
301 N0.getOpcode() == ISD::ANY_EXTEND) &&
302 N0.getOperand(0).getValueType() == VT) {
303 return TLO.CombineTo(Op, N0.getOperand(0));
308 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
309 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
310 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
311 void SelectionDAGISel::ShrinkDemandedOps() {
312 SmallVector<SDNode*, 128> Worklist;
313 SmallPtrSet<SDNode*, 128> InWorklist;
315 // Add all the dag nodes to the worklist.
316 Worklist.reserve(CurDAG->allnodes_size());
317 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
318 E = CurDAG->allnodes_end(); I != E; ++I) {
319 Worklist.push_back(I);
320 InWorklist.insert(I);
323 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true);
324 while (!Worklist.empty()) {
325 SDNode *N = Worklist.pop_back_val();
328 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
329 // Deleting this node may make its operands dead, add them to the worklist
330 // if they aren't already there.
331 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
332 if (InWorklist.insert(N->getOperand(i).getNode()))
333 Worklist.push_back(N->getOperand(i).getNode());
335 CurDAG->DeleteNode(N);
339 // Run ShrinkDemandedOp on scalar binary operations.
340 if (N->getNumValues() != 1 ||
341 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
344 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
345 APInt Demanded = APInt::getAllOnesValue(BitWidth);
346 APInt KnownZero, KnownOne;
347 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
348 KnownZero, KnownOne, TLO) &&
349 (N->getOpcode() != ISD::TRUNCATE ||
350 !TrivialTruncElim(SDValue(N, 0), TLO)))
354 assert(!InWorklist.count(N) && "Already in worklist");
355 Worklist.push_back(N);
356 InWorklist.insert(N);
358 // Replace the old value with the new one.
359 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
360 TLO.Old.getNode()->dump(CurDAG);
361 errs() << "\nWith: ";
362 TLO.New.getNode()->dump(CurDAG);
365 if (InWorklist.insert(TLO.New.getNode()))
366 Worklist.push_back(TLO.New.getNode());
368 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
369 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
371 if (!TLO.Old.getNode()->use_empty()) continue;
373 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
375 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
376 if (OpNode->hasOneUse()) {
377 // Add OpNode to the end of the list to revisit.
378 DeadNodes.RemoveFromWorklist(OpNode);
379 Worklist.push_back(OpNode);
380 InWorklist.insert(OpNode);
384 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
385 CurDAG->DeleteNode(TLO.Old.getNode());
389 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
390 SmallPtrSet<SDNode*, 128> VisitedNodes;
391 SmallVector<SDNode*, 128> Worklist;
393 Worklist.push_back(CurDAG->getRoot().getNode());
400 SDNode *N = Worklist.pop_back_val();
402 // If we've already seen this node, ignore it.
403 if (!VisitedNodes.insert(N))
406 // Otherwise, add all chain operands to the worklist.
407 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
408 if (N->getOperand(i).getValueType() == MVT::Other)
409 Worklist.push_back(N->getOperand(i).getNode());
411 // If this is a CopyToReg with a vreg dest, process it.
412 if (N->getOpcode() != ISD::CopyToReg)
415 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
416 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
419 // Ignore non-scalar or non-integer values.
420 SDValue Src = N->getOperand(2);
421 EVT SrcVT = Src.getValueType();
422 if (!SrcVT.isInteger() || SrcVT.isVector())
425 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
426 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
427 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
429 // Only install this information if it tells us something.
430 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
431 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
432 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
433 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
434 FunctionLoweringInfo::LiveOutInfo &LOI =
435 FuncInfo->LiveOutRegInfo[DestReg];
436 LOI.NumSignBits = NumSignBits;
437 LOI.KnownOne = KnownOne;
438 LOI.KnownZero = KnownZero;
440 } while (!Worklist.empty());
443 MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) {
444 std::string GroupName;
445 if (TimePassesIsEnabled)
446 GroupName = "Instruction Selection and Scheduling";
447 std::string BlockName;
448 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
449 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
451 BlockName = MF->getFunction()->getNameStr() + ":" +
452 BB->getBasicBlock()->getNameStr();
454 DEBUG(dbgs() << "Initial selection DAG:\n");
455 DEBUG(CurDAG->dump());
457 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
459 // Run the DAG combiner in pre-legalize mode.
460 if (TimePassesIsEnabled) {
461 NamedRegionTimer T("DAG Combining 1", GroupName);
462 CurDAG->Combine(Unrestricted, *AA, OptLevel);
464 CurDAG->Combine(Unrestricted, *AA, OptLevel);
467 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
468 DEBUG(CurDAG->dump());
470 // Second step, hack on the DAG until it only uses operations and types that
471 // the target supports.
472 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
476 if (TimePassesIsEnabled) {
477 NamedRegionTimer T("Type Legalization", GroupName);
478 Changed = CurDAG->LegalizeTypes();
480 Changed = CurDAG->LegalizeTypes();
483 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
484 DEBUG(CurDAG->dump());
487 if (ViewDAGCombineLT)
488 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
490 // Run the DAG combiner in post-type-legalize mode.
491 if (TimePassesIsEnabled) {
492 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
493 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
495 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
498 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
499 DEBUG(CurDAG->dump());
502 if (TimePassesIsEnabled) {
503 NamedRegionTimer T("Vector Legalization", GroupName);
504 Changed = CurDAG->LegalizeVectors();
506 Changed = CurDAG->LegalizeVectors();
510 if (TimePassesIsEnabled) {
511 NamedRegionTimer T("Type Legalization 2", GroupName);
512 CurDAG->LegalizeTypes();
514 CurDAG->LegalizeTypes();
517 if (ViewDAGCombineLT)
518 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
520 // Run the DAG combiner in post-type-legalize mode.
521 if (TimePassesIsEnabled) {
522 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
523 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
525 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
528 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
529 DEBUG(CurDAG->dump());
532 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
534 if (TimePassesIsEnabled) {
535 NamedRegionTimer T("DAG Legalization", GroupName);
536 CurDAG->Legalize(OptLevel);
538 CurDAG->Legalize(OptLevel);
541 DEBUG(dbgs() << "Legalized selection DAG:\n");
542 DEBUG(CurDAG->dump());
544 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
546 // Run the DAG combiner in post-legalize mode.
547 if (TimePassesIsEnabled) {
548 NamedRegionTimer T("DAG Combining 2", GroupName);
549 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
551 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
554 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
555 DEBUG(CurDAG->dump());
557 if (OptLevel != CodeGenOpt::None) {
559 ComputeLiveOutVRegInfo();
562 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
564 // Third, instruction select all of the operations to machine code, adding the
565 // code to the MachineBasicBlock.
566 if (TimePassesIsEnabled) {
567 NamedRegionTimer T("Instruction Selection", GroupName);
568 DoInstructionSelection();
570 DoInstructionSelection();
573 DEBUG(dbgs() << "Selected selection DAG:\n");
574 DEBUG(CurDAG->dump());
576 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
578 // Schedule machine code.
579 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
580 if (TimePassesIsEnabled) {
581 NamedRegionTimer T("Instruction Scheduling", GroupName);
582 Scheduler->Run(CurDAG, BB, BB->end());
584 Scheduler->Run(CurDAG, BB, BB->end());
587 if (ViewSUnitDAGs) Scheduler->viewGraph();
589 // Emit machine code to BB. This can change 'BB' to the last block being
591 if (TimePassesIsEnabled) {
592 NamedRegionTimer T("Instruction Creation", GroupName);
593 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
595 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
598 // Free the scheduler state.
599 if (TimePassesIsEnabled) {
600 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
609 void SelectionDAGISel::DoInstructionSelection() {
610 DEBUG(errs() << "===== Instruction selection begins:\n");
614 // Select target instructions for the DAG.
616 // Number all nodes with a topological order and set DAGSize.
617 DAGSize = CurDAG->AssignTopologicalOrder();
619 // Create a dummy node (which is not added to allnodes), that adds
620 // a reference to the root node, preventing it from being deleted,
621 // and tracking any changes of the root.
622 HandleSDNode Dummy(CurDAG->getRoot());
623 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
626 // The AllNodes list is now topological-sorted. Visit the
627 // nodes by starting at the end of the list (the root of the
628 // graph) and preceding back toward the beginning (the entry
630 while (ISelPosition != CurDAG->allnodes_begin()) {
631 SDNode *Node = --ISelPosition;
632 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
633 // but there are currently some corner cases that it misses. Also, this
634 // makes it theoretically possible to disable the DAGCombiner.
635 if (Node->use_empty())
638 SDNode *ResNode = Select(Node);
640 // FIXME: This is pretty gross. 'Select' should be changed to not return
641 // anything at all and this code should be nuked with a tactical strike.
643 // If node should not be replaced, continue with the next one.
644 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
648 ReplaceUses(Node, ResNode);
650 // If after the replacement this node is not used any more,
651 // remove this dead node.
652 if (Node->use_empty()) { // Don't delete EntryToken, etc.
653 ISelUpdater ISU(ISelPosition);
654 CurDAG->RemoveDeadNode(Node, &ISU);
658 CurDAG->setRoot(Dummy.getValue());
660 DEBUG(errs() << "===== Instruction selection ends:\n");
662 PostprocessISelDAG();
665 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
666 /// do other setup for EH landing-pad blocks.
667 void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) {
668 // Add a label to mark the beginning of the landing pad. Deletion of the
669 // landing pad can thus be detected via the MachineModuleInfo.
670 MCSymbol *Label = MF->getMMI().addLandingPad(BB);
672 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
673 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
675 // Mark exception register as live in.
676 unsigned Reg = TLI.getExceptionAddressRegister();
677 if (Reg) BB->addLiveIn(Reg);
679 // Mark exception selector register as live in.
680 Reg = TLI.getExceptionSelectorRegister();
681 if (Reg) BB->addLiveIn(Reg);
683 // FIXME: Hack around an exception handling flaw (PR1508): the personality
684 // function and list of typeids logically belong to the invoke (or, if you
685 // like, the basic block containing the invoke), and need to be associated
686 // with it in the dwarf exception handling tables. Currently however the
687 // information is provided by an intrinsic (eh.selector) that can be moved
688 // to unexpected places by the optimizers: if the unwind edge is critical,
689 // then breaking it can result in the intrinsics being in the successor of
690 // the landing pad, not the landing pad itself. This results
691 // in exceptions not being caught because no typeids are associated with
692 // the invoke. This may not be the only way things can go wrong, but it
693 // is the only way we try to work around for the moment.
694 const BasicBlock *LLVMBB = BB->getBasicBlock();
695 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
697 if (Br && Br->isUnconditional()) { // Critical edge?
698 BasicBlock::const_iterator I, E;
699 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
700 if (isa<EHSelectorInst>(I))
704 // No catch info found - try to extract some from the successor.
705 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
709 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
710 // Initialize the Fast-ISel state, if needed.
711 FastISel *FastIS = 0;
713 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
714 FuncInfo->StaticAllocaMap
716 , FuncInfo->CatchInfoLost
720 // Iterate over all basic blocks in the function.
721 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
722 const BasicBlock *LLVMBB = &*I;
723 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB];
725 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
726 BasicBlock::const_iterator const End = LLVMBB->end();
727 BasicBlock::const_iterator BI = Begin;
729 // Lower any arguments needed in this block if this is the entry block.
730 bool SuppressFastISel = false;
731 if (LLVMBB == &Fn.getEntryBlock()) {
732 LowerArguments(LLVMBB);
734 // If any of the arguments has the byval attribute, forgo
735 // fast-isel in the entry block.
738 for (Function::const_arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
740 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
741 if (EnableFastISelVerbose || EnableFastISelAbort)
742 dbgs() << "FastISel skips entry block due to byval argument\n";
743 SuppressFastISel = true;
749 // Setup an EH landing-pad block.
750 if (BB->isLandingPad())
751 PrepareEHLandingPad(BB);
753 // Before doing SelectionDAG ISel, see if FastISel has been requested.
754 if (FastIS && !SuppressFastISel) {
755 // Emit code for any incoming arguments. This must happen before
756 // beginning FastISel on the entry block.
757 if (LLVMBB == &Fn.getEntryBlock()) {
758 CurDAG->setRoot(SDB->getControlRoot());
759 BB = CodeGenAndEmitDAG(BB);
762 FastIS->startNewBlock(BB);
763 // Do FastISel on as many instructions as possible.
764 for (; BI != End; ++BI) {
765 // Just before the terminator instruction, insert instructions to
766 // feed PHI nodes in successor blocks.
767 if (isa<TerminatorInst>(BI))
768 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
769 ++NumFastIselFailures;
770 if (EnableFastISelVerbose || EnableFastISelAbort) {
771 dbgs() << "FastISel miss: ";
774 assert(!EnableFastISelAbort &&
775 "FastISel didn't handle a PHI in a successor");
779 // Try to select the instruction with FastISel.
780 if (FastIS->SelectInstruction(BI))
783 // Then handle certain instructions as single-LLVM-Instruction blocks.
784 if (isa<CallInst>(BI)) {
785 ++NumFastIselFailures;
786 if (EnableFastISelVerbose || EnableFastISelAbort) {
787 dbgs() << "FastISel missed call: ";
791 if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
792 unsigned &R = FuncInfo->ValueMap[BI];
794 R = FuncInfo->CreateRegForValue(BI);
797 bool HadTailCall = false;
798 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall);
800 // If the call was emitted as a tail call, we're done with the block.
806 // If the instruction was codegen'd with multiple blocks,
807 // inform the FastISel object where to resume inserting.
808 FastIS->setCurrentBlock(BB);
812 // Otherwise, give up on FastISel for the rest of the block.
813 // For now, be a little lenient about non-branch terminators.
814 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
815 ++NumFastIselFailures;
816 if (EnableFastISelVerbose || EnableFastISelAbort) {
817 dbgs() << "FastISel miss: ";
820 if (EnableFastISelAbort)
821 // The "fast" selector couldn't handle something and bailed.
822 // For the purpose of debugging, just abort.
823 llvm_unreachable("FastISel didn't select the entire block");
829 // Run SelectionDAG instruction selection on the remainder of the block
830 // not handled by FastISel. If FastISel is not run, this is the entire
834 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall);
837 FinishBasicBlock(BB);
844 SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) {
846 DEBUG(dbgs() << "Target-post-processed machine code:\n");
849 DEBUG(dbgs() << "Total amount of phi nodes to update: "
850 << SDB->PHINodesToUpdate.size() << "\n");
851 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
852 dbgs() << "Node " << i << " : ("
853 << SDB->PHINodesToUpdate[i].first
854 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
856 // Next, now that we know what the last MBB the LLVM BB expanded is, update
857 // PHI nodes in successors.
858 if (SDB->SwitchCases.empty() &&
859 SDB->JTCases.empty() &&
860 SDB->BitTestCases.empty()) {
861 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
862 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
863 assert(PHI->isPHI() &&
864 "This is not a machine PHI node that we are updating!");
865 if (!BB->isSuccessor(PHI->getParent()))
867 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
869 PHI->addOperand(MachineOperand::CreateMBB(BB));
871 SDB->PHINodesToUpdate.clear();
875 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
876 // Lower header first, if it wasn't already lowered
877 if (!SDB->BitTestCases[i].Emitted) {
878 // Set the current basic block to the mbb we wish to insert the code into
879 BB = SDB->BitTestCases[i].Parent;
881 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB);
882 CurDAG->setRoot(SDB->getRoot());
883 BB = CodeGenAndEmitDAG(BB);
887 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
888 // Set the current basic block to the mbb we wish to insert the code into
889 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
892 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
893 SDB->BitTestCases[i].Reg,
894 SDB->BitTestCases[i].Cases[j],
897 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
898 SDB->BitTestCases[i].Reg,
899 SDB->BitTestCases[i].Cases[j],
903 CurDAG->setRoot(SDB->getRoot());
904 BB = CodeGenAndEmitDAG(BB);
909 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
910 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
911 MachineBasicBlock *PHIBB = PHI->getParent();
912 assert(PHI->isPHI() &&
913 "This is not a machine PHI node that we are updating!");
914 // This is "default" BB. We have two jumps to it. From "header" BB and
915 // from last "case" BB.
916 if (PHIBB == SDB->BitTestCases[i].Default) {
917 PHI->addOperand(MachineOperand::
918 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
919 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
920 PHI->addOperand(MachineOperand::
921 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
922 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
925 // One of "cases" BB.
926 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
928 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
929 if (cBB->isSuccessor(PHIBB)) {
930 PHI->addOperand(MachineOperand::
931 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
932 PHI->addOperand(MachineOperand::CreateMBB(cBB));
937 SDB->BitTestCases.clear();
939 // If the JumpTable record is filled in, then we need to emit a jump table.
940 // Updating the PHI nodes is tricky in this case, since we need to determine
941 // whether the PHI is a successor of the range check MBB or the jump table MBB
942 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
943 // Lower header first, if it wasn't already lowered
944 if (!SDB->JTCases[i].first.Emitted) {
945 // Set the current basic block to the mbb we wish to insert the code into
946 BB = SDB->JTCases[i].first.HeaderBB;
948 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
950 CurDAG->setRoot(SDB->getRoot());
951 BB = CodeGenAndEmitDAG(BB);
955 // Set the current basic block to the mbb we wish to insert the code into
956 BB = SDB->JTCases[i].second.MBB;
958 SDB->visitJumpTable(SDB->JTCases[i].second);
959 CurDAG->setRoot(SDB->getRoot());
960 BB = CodeGenAndEmitDAG(BB);
964 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
965 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
966 MachineBasicBlock *PHIBB = PHI->getParent();
967 assert(PHI->isPHI() &&
968 "This is not a machine PHI node that we are updating!");
969 // "default" BB. We can go there only from header BB.
970 if (PHIBB == SDB->JTCases[i].second.Default) {
972 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
974 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
976 // JT BB. Just iterate over successors here
977 if (BB->isSuccessor(PHIBB)) {
979 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
980 PHI->addOperand(MachineOperand::CreateMBB(BB));
984 SDB->JTCases.clear();
986 // If the switch block involved a branch to one of the actual successors, we
987 // need to update PHI nodes in that block.
988 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
989 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
990 assert(PHI->isPHI() &&
991 "This is not a machine PHI node that we are updating!");
992 if (BB->isSuccessor(PHI->getParent())) {
993 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
995 PHI->addOperand(MachineOperand::CreateMBB(BB));
999 // If we generated any switch lowering information, build and codegen any
1000 // additional DAGs necessary.
1001 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1002 // Set the current basic block to the mbb we wish to insert the code into
1003 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1006 SDB->visitSwitchCase(SDB->SwitchCases[i], BB);
1007 CurDAG->setRoot(SDB->getRoot());
1008 BB = CodeGenAndEmitDAG(BB);
1010 // Handle any PHI nodes in successors of this chunk, as if we were coming
1011 // from the original BB before switch expansion. Note that PHI nodes can
1012 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1013 // handle them the right number of times.
1014 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1015 // If new BB's are created during scheduling, the edges may have been
1016 // updated. That is, the edge from ThisBB to BB may have been split and
1017 // BB's predecessor is now another block.
1018 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1019 SDB->EdgeMapping.find(BB);
1020 if (EI != SDB->EdgeMapping.end())
1021 ThisBB = EI->second;
1023 // BB may have been removed from the CFG if a branch was constant folded.
1024 if (ThisBB->isSuccessor(BB)) {
1025 for (MachineBasicBlock::iterator Phi = BB->begin();
1026 Phi != BB->end() && Phi->isPHI();
1028 // This value for this PHI node is recorded in PHINodesToUpdate.
1029 for (unsigned pn = 0; ; ++pn) {
1030 assert(pn != SDB->PHINodesToUpdate.size() &&
1031 "Didn't find PHI entry!");
1032 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1033 Phi->addOperand(MachineOperand::
1034 CreateReg(SDB->PHINodesToUpdate[pn].second,
1036 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1043 // Don't process RHS if same block as LHS.
1044 if (BB == SDB->SwitchCases[i].FalseBB)
1045 SDB->SwitchCases[i].FalseBB = 0;
1047 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1048 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1049 SDB->SwitchCases[i].FalseBB = 0;
1051 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1054 SDB->SwitchCases.clear();
1056 SDB->PHINodesToUpdate.clear();
1060 /// Create the scheduler. If a specific scheduler was specified
1061 /// via the SchedulerRegistry, use it, otherwise select the
1062 /// one preferred by the target.
1064 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1065 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1069 RegisterScheduler::setDefault(Ctor);
1072 return Ctor(this, OptLevel);
1075 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1076 return new ScheduleHazardRecognizer();
1079 //===----------------------------------------------------------------------===//
1080 // Helper functions used by the generated instruction selector.
1081 //===----------------------------------------------------------------------===//
1082 // Calls to these methods are generated by tblgen.
1084 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1085 /// the dag combiner simplified the 255, we still want to match. RHS is the
1086 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1087 /// specified in the .td file (e.g. 255).
1088 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1089 int64_t DesiredMaskS) const {
1090 const APInt &ActualMask = RHS->getAPIntValue();
1091 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1093 // If the actual mask exactly matches, success!
1094 if (ActualMask == DesiredMask)
1097 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1098 if (ActualMask.intersects(~DesiredMask))
1101 // Otherwise, the DAG Combiner may have proven that the value coming in is
1102 // either already zero or is not demanded. Check for known zero input bits.
1103 APInt NeededMask = DesiredMask & ~ActualMask;
1104 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1107 // TODO: check to see if missing bits are just not demanded.
1109 // Otherwise, this pattern doesn't match.
1113 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1114 /// the dag combiner simplified the 255, we still want to match. RHS is the
1115 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1116 /// specified in the .td file (e.g. 255).
1117 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1118 int64_t DesiredMaskS) const {
1119 const APInt &ActualMask = RHS->getAPIntValue();
1120 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1122 // If the actual mask exactly matches, success!
1123 if (ActualMask == DesiredMask)
1126 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1127 if (ActualMask.intersects(~DesiredMask))
1130 // Otherwise, the DAG Combiner may have proven that the value coming in is
1131 // either already zero or is not demanded. Check for known zero input bits.
1132 APInt NeededMask = DesiredMask & ~ActualMask;
1134 APInt KnownZero, KnownOne;
1135 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1137 // If all the missing bits in the or are already known to be set, match!
1138 if ((NeededMask & KnownOne) == NeededMask)
1141 // TODO: check to see if missing bits are just not demanded.
1143 // Otherwise, this pattern doesn't match.
1148 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1149 /// by tblgen. Others should not call it.
1150 void SelectionDAGISel::
1151 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1152 std::vector<SDValue> InOps;
1153 std::swap(InOps, Ops);
1155 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1156 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1157 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1159 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1160 if (InOps[e-1].getValueType() == MVT::Flag)
1161 --e; // Don't process a flag operand if it is here.
1164 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1165 if (!InlineAsm::isMemKind(Flags)) {
1166 // Just skip over this operand, copying the operands verbatim.
1167 Ops.insert(Ops.end(), InOps.begin()+i,
1168 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1169 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1171 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1172 "Memory operand with multiple values?");
1173 // Otherwise, this is a memory operand. Ask the target to select it.
1174 std::vector<SDValue> SelOps;
1175 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1176 report_fatal_error("Could not match memory address. Inline asm"
1179 // Add this to the output node.
1181 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1182 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1183 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1188 // Add the flag input back if present.
1189 if (e != InOps.size())
1190 Ops.push_back(InOps.back());
1193 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1196 static SDNode *findFlagUse(SDNode *N) {
1197 unsigned FlagResNo = N->getNumValues()-1;
1198 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1199 SDUse &Use = I.getUse();
1200 if (Use.getResNo() == FlagResNo)
1201 return Use.getUser();
1206 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1207 /// This function recursively traverses up the operand chain, ignoring
1209 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1210 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1211 bool IgnoreChains) {
1212 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1213 // greater than all of its (recursive) operands. If we scan to a point where
1214 // 'use' is smaller than the node we're scanning for, then we know we will
1217 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1218 // happen because we scan down to newly selected nodes in the case of flag
1220 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1223 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1224 // won't fail if we scan it again.
1225 if (!Visited.insert(Use))
1228 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1229 // Ignore chain uses, they are validated by HandleMergeInputChains.
1230 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1233 SDNode *N = Use->getOperand(i).getNode();
1235 if (Use == ImmedUse || Use == Root)
1236 continue; // We are not looking for immediate use.
1241 // Traverse up the operand chain.
1242 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1248 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1249 /// operand node N of U during instruction selection that starts at Root.
1250 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1251 SDNode *Root) const {
1252 if (OptLevel == CodeGenOpt::None) return false;
1253 return N.hasOneUse();
1256 /// IsLegalToFold - Returns true if the specific operand node N of
1257 /// U can be folded during instruction selection that starts at Root.
1258 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1259 CodeGenOpt::Level OptLevel,
1260 bool IgnoreChains) {
1261 if (OptLevel == CodeGenOpt::None) return false;
1263 // If Root use can somehow reach N through a path that that doesn't contain
1264 // U then folding N would create a cycle. e.g. In the following
1265 // diagram, Root can reach N through X. If N is folded into into Root, then
1266 // X is both a predecessor and a successor of U.
1277 // * indicates nodes to be folded together.
1279 // If Root produces a flag, then it gets (even more) interesting. Since it
1280 // will be "glued" together with its flag use in the scheduler, we need to
1281 // check if it might reach N.
1300 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1301 // (call it Fold), then X is a predecessor of FU and a successor of
1302 // Fold. But since Fold and FU are flagged together, this will create
1303 // a cycle in the scheduling graph.
1305 // If the node has flags, walk down the graph to the "lowest" node in the
1307 EVT VT = Root->getValueType(Root->getNumValues()-1);
1308 while (VT == MVT::Flag) {
1309 SDNode *FU = findFlagUse(Root);
1313 VT = Root->getValueType(Root->getNumValues()-1);
1315 // If our query node has a flag result with a use, we've walked up it. If
1316 // the user (which has already been selected) has a chain or indirectly uses
1317 // the chain, our WalkChainUsers predicate will not consider it. Because of
1318 // this, we cannot ignore chains in this predicate.
1319 IgnoreChains = false;
1323 SmallPtrSet<SDNode*, 16> Visited;
1324 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1327 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1328 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1329 SelectInlineAsmMemoryOperands(Ops);
1331 std::vector<EVT> VTs;
1332 VTs.push_back(MVT::Other);
1333 VTs.push_back(MVT::Flag);
1334 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1335 VTs, &Ops[0], Ops.size());
1337 return New.getNode();
1340 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1341 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1344 /// GetVBR - decode a vbr encoding whose top bit is set.
1345 ALWAYS_INLINE static uint64_t
1346 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1347 assert(Val >= 128 && "Not a VBR");
1348 Val &= 127; // Remove first vbr bit.
1353 NextBits = MatcherTable[Idx++];
1354 Val |= (NextBits&127) << Shift;
1356 } while (NextBits & 128);
1362 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1363 /// interior flag and chain results to use the new flag and chain results.
1364 void SelectionDAGISel::
1365 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1366 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1368 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1369 bool isMorphNodeTo) {
1370 SmallVector<SDNode*, 4> NowDeadNodes;
1372 ISelUpdater ISU(ISelPosition);
1374 // Now that all the normal results are replaced, we replace the chain and
1375 // flag results if present.
1376 if (!ChainNodesMatched.empty()) {
1377 assert(InputChain.getNode() != 0 &&
1378 "Matched input chains but didn't produce a chain");
1379 // Loop over all of the nodes we matched that produced a chain result.
1380 // Replace all the chain results with the final chain we ended up with.
1381 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1382 SDNode *ChainNode = ChainNodesMatched[i];
1384 // If this node was already deleted, don't look at it.
1385 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1388 // Don't replace the results of the root node if we're doing a
1390 if (ChainNode == NodeToMatch && isMorphNodeTo)
1393 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1394 if (ChainVal.getValueType() == MVT::Flag)
1395 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1396 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1397 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1399 // If the node became dead and we haven't already seen it, delete it.
1400 if (ChainNode->use_empty() &&
1401 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1402 NowDeadNodes.push_back(ChainNode);
1406 // If the result produces a flag, update any flag results in the matched
1407 // pattern with the flag result.
1408 if (InputFlag.getNode() != 0) {
1409 // Handle any interior nodes explicitly marked.
1410 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1411 SDNode *FRN = FlagResultNodesMatched[i];
1413 // If this node was already deleted, don't look at it.
1414 if (FRN->getOpcode() == ISD::DELETED_NODE)
1417 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1418 "Doesn't have a flag result");
1419 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1422 // If the node became dead and we haven't already seen it, delete it.
1423 if (FRN->use_empty() &&
1424 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1425 NowDeadNodes.push_back(FRN);
1429 if (!NowDeadNodes.empty())
1430 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1432 DEBUG(errs() << "ISEL: Match complete!\n");
1438 CR_LeadsToInteriorNode
1441 /// WalkChainUsers - Walk down the users of the specified chained node that is
1442 /// part of the pattern we're matching, looking at all of the users we find.
1443 /// This determines whether something is an interior node, whether we have a
1444 /// non-pattern node in between two pattern nodes (which prevent folding because
1445 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1446 /// between pattern nodes (in which case the TF becomes part of the pattern).
1448 /// The walk we do here is guaranteed to be small because we quickly get down to
1449 /// already selected nodes "below" us.
1451 WalkChainUsers(SDNode *ChainedNode,
1452 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1453 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1454 ChainResult Result = CR_Simple;
1456 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1457 E = ChainedNode->use_end(); UI != E; ++UI) {
1458 // Make sure the use is of the chain, not some other value we produce.
1459 if (UI.getUse().getValueType() != MVT::Other) continue;
1463 // If we see an already-selected machine node, then we've gone beyond the
1464 // pattern that we're selecting down into the already selected chunk of the
1466 if (User->isMachineOpcode() ||
1467 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1470 if (User->getOpcode() == ISD::CopyToReg ||
1471 User->getOpcode() == ISD::CopyFromReg ||
1472 User->getOpcode() == ISD::INLINEASM ||
1473 User->getOpcode() == ISD::EH_LABEL) {
1474 // If their node ID got reset to -1 then they've already been selected.
1475 // Treat them like a MachineOpcode.
1476 if (User->getNodeId() == -1)
1480 // If we have a TokenFactor, we handle it specially.
1481 if (User->getOpcode() != ISD::TokenFactor) {
1482 // If the node isn't a token factor and isn't part of our pattern, then it
1483 // must be a random chained node in between two nodes we're selecting.
1484 // This happens when we have something like:
1489 // Because we structurally match the load/store as a read/modify/write,
1490 // but the call is chained between them. We cannot fold in this case
1491 // because it would induce a cycle in the graph.
1492 if (!std::count(ChainedNodesInPattern.begin(),
1493 ChainedNodesInPattern.end(), User))
1494 return CR_InducesCycle;
1496 // Otherwise we found a node that is part of our pattern. For example in:
1500 // This would happen when we're scanning down from the load and see the
1501 // store as a user. Record that there is a use of ChainedNode that is
1502 // part of the pattern and keep scanning uses.
1503 Result = CR_LeadsToInteriorNode;
1504 InteriorChainedNodes.push_back(User);
1508 // If we found a TokenFactor, there are two cases to consider: first if the
1509 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1510 // uses of the TF are in our pattern) we just want to ignore it. Second,
1511 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1517 // | \ DAG's like cheese
1520 // [TokenFactor] [Op]
1527 // In this case, the TokenFactor becomes part of our match and we rewrite it
1528 // as a new TokenFactor.
1530 // To distinguish these two cases, do a recursive walk down the uses.
1531 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1533 // If the uses of the TokenFactor are just already-selected nodes, ignore
1534 // it, it is "below" our pattern.
1536 case CR_InducesCycle:
1537 // If the uses of the TokenFactor lead to nodes that are not part of our
1538 // pattern that are not selected, folding would turn this into a cycle,
1540 return CR_InducesCycle;
1541 case CR_LeadsToInteriorNode:
1542 break; // Otherwise, keep processing.
1545 // Okay, we know we're in the interesting interior case. The TokenFactor
1546 // is now going to be considered part of the pattern so that we rewrite its
1547 // uses (it may have uses that are not part of the pattern) with the
1548 // ultimate chain result of the generated code. We will also add its chain
1549 // inputs as inputs to the ultimate TokenFactor we create.
1550 Result = CR_LeadsToInteriorNode;
1551 ChainedNodesInPattern.push_back(User);
1552 InteriorChainedNodes.push_back(User);
1559 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1560 /// operation for when the pattern matched at least one node with a chains. The
1561 /// input vector contains a list of all of the chained nodes that we match. We
1562 /// must determine if this is a valid thing to cover (i.e. matching it won't
1563 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1564 /// be used as the input node chain for the generated nodes.
1566 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1567 SelectionDAG *CurDAG) {
1568 // Walk all of the chained nodes we've matched, recursively scanning down the
1569 // users of the chain result. This adds any TokenFactor nodes that are caught
1570 // in between chained nodes to the chained and interior nodes list.
1571 SmallVector<SDNode*, 3> InteriorChainedNodes;
1572 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1573 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1574 InteriorChainedNodes) == CR_InducesCycle)
1575 return SDValue(); // Would induce a cycle.
1578 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1579 // that we are interested in. Form our input TokenFactor node.
1580 SmallVector<SDValue, 3> InputChains;
1581 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1582 // Add the input chain of this node to the InputChains list (which will be
1583 // the operands of the generated TokenFactor) if it's not an interior node.
1584 SDNode *N = ChainNodesMatched[i];
1585 if (N->getOpcode() != ISD::TokenFactor) {
1586 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1589 // Otherwise, add the input chain.
1590 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1591 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1592 InputChains.push_back(InChain);
1596 // If we have a token factor, we want to add all inputs of the token factor
1597 // that are not part of the pattern we're matching.
1598 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1599 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1600 N->getOperand(op).getNode()))
1601 InputChains.push_back(N->getOperand(op));
1606 if (InputChains.size() == 1)
1607 return InputChains[0];
1608 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1609 MVT::Other, &InputChains[0], InputChains.size());
1612 /// MorphNode - Handle morphing a node in place for the selector.
1613 SDNode *SelectionDAGISel::
1614 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1615 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1616 // It is possible we're using MorphNodeTo to replace a node with no
1617 // normal results with one that has a normal result (or we could be
1618 // adding a chain) and the input could have flags and chains as well.
1619 // In this case we need to shift the operands down.
1620 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1621 // than the old isel though.
1622 int OldFlagResultNo = -1, OldChainResultNo = -1;
1624 unsigned NTMNumResults = Node->getNumValues();
1625 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1626 OldFlagResultNo = NTMNumResults-1;
1627 if (NTMNumResults != 1 &&
1628 Node->getValueType(NTMNumResults-2) == MVT::Other)
1629 OldChainResultNo = NTMNumResults-2;
1630 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1631 OldChainResultNo = NTMNumResults-1;
1633 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1634 // that this deletes operands of the old node that become dead.
1635 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1637 // MorphNodeTo can operate in two ways: if an existing node with the
1638 // specified operands exists, it can just return it. Otherwise, it
1639 // updates the node in place to have the requested operands.
1641 // If we updated the node in place, reset the node ID. To the isel,
1642 // this should be just like a newly allocated machine node.
1646 unsigned ResNumResults = Res->getNumValues();
1647 // Move the flag if needed.
1648 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1649 (unsigned)OldFlagResultNo != ResNumResults-1)
1650 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1651 SDValue(Res, ResNumResults-1));
1653 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1656 // Move the chain reference if needed.
1657 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1658 (unsigned)OldChainResultNo != ResNumResults-1)
1659 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1660 SDValue(Res, ResNumResults-1));
1662 // Otherwise, no replacement happened because the node already exists. Replace
1663 // Uses of the old node with the new one.
1665 CurDAG->ReplaceAllUsesWith(Node, Res);
1670 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1671 ALWAYS_INLINE static bool
1672 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1673 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1674 // Accept if it is exactly the same as a previously recorded node.
1675 unsigned RecNo = MatcherTable[MatcherIndex++];
1676 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1677 return N == RecordedNodes[RecNo];
1680 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1681 ALWAYS_INLINE static bool
1682 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1683 SelectionDAGISel &SDISel) {
1684 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1687 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1688 ALWAYS_INLINE static bool
1689 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1690 SelectionDAGISel &SDISel, SDNode *N) {
1691 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1694 ALWAYS_INLINE static bool
1695 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1697 uint16_t Opc = MatcherTable[MatcherIndex++];
1698 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1699 return N->getOpcode() == Opc;
1702 ALWAYS_INLINE static bool
1703 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1704 SDValue N, const TargetLowering &TLI) {
1705 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1706 if (N.getValueType() == VT) return true;
1708 // Handle the case when VT is iPTR.
1709 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1712 ALWAYS_INLINE static bool
1713 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1714 SDValue N, const TargetLowering &TLI,
1716 if (ChildNo >= N.getNumOperands())
1717 return false; // Match fails if out of range child #.
1718 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1722 ALWAYS_INLINE static bool
1723 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1725 return cast<CondCodeSDNode>(N)->get() ==
1726 (ISD::CondCode)MatcherTable[MatcherIndex++];
1729 ALWAYS_INLINE static bool
1730 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1731 SDValue N, const TargetLowering &TLI) {
1732 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1733 if (cast<VTSDNode>(N)->getVT() == VT)
1736 // Handle the case when VT is iPTR.
1737 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1740 ALWAYS_INLINE static bool
1741 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1743 int64_t Val = MatcherTable[MatcherIndex++];
1745 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1747 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1748 return C != 0 && C->getSExtValue() == Val;
1751 ALWAYS_INLINE static bool
1752 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1753 SDValue N, SelectionDAGISel &SDISel) {
1754 int64_t Val = MatcherTable[MatcherIndex++];
1756 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1758 if (N->getOpcode() != ISD::AND) return false;
1760 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1761 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1764 ALWAYS_INLINE static bool
1765 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1766 SDValue N, SelectionDAGISel &SDISel) {
1767 int64_t Val = MatcherTable[MatcherIndex++];
1769 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1771 if (N->getOpcode() != ISD::OR) return false;
1773 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1774 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1777 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1778 /// scope, evaluate the current node. If the current predicate is known to
1779 /// fail, set Result=true and return anything. If the current predicate is
1780 /// known to pass, set Result=false and return the MatcherIndex to continue
1781 /// with. If the current predicate is unknown, set Result=false and return the
1782 /// MatcherIndex to continue with.
1783 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1784 unsigned Index, SDValue N,
1785 bool &Result, SelectionDAGISel &SDISel,
1786 SmallVectorImpl<SDValue> &RecordedNodes){
1787 switch (Table[Index++]) {
1790 return Index-1; // Could not evaluate this predicate.
1791 case SelectionDAGISel::OPC_CheckSame:
1792 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1794 case SelectionDAGISel::OPC_CheckPatternPredicate:
1795 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1797 case SelectionDAGISel::OPC_CheckPredicate:
1798 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1800 case SelectionDAGISel::OPC_CheckOpcode:
1801 Result = !::CheckOpcode(Table, Index, N.getNode());
1803 case SelectionDAGISel::OPC_CheckType:
1804 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1806 case SelectionDAGISel::OPC_CheckChild0Type:
1807 case SelectionDAGISel::OPC_CheckChild1Type:
1808 case SelectionDAGISel::OPC_CheckChild2Type:
1809 case SelectionDAGISel::OPC_CheckChild3Type:
1810 case SelectionDAGISel::OPC_CheckChild4Type:
1811 case SelectionDAGISel::OPC_CheckChild5Type:
1812 case SelectionDAGISel::OPC_CheckChild6Type:
1813 case SelectionDAGISel::OPC_CheckChild7Type:
1814 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1815 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1817 case SelectionDAGISel::OPC_CheckCondCode:
1818 Result = !::CheckCondCode(Table, Index, N);
1820 case SelectionDAGISel::OPC_CheckValueType:
1821 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1823 case SelectionDAGISel::OPC_CheckInteger:
1824 Result = !::CheckInteger(Table, Index, N);
1826 case SelectionDAGISel::OPC_CheckAndImm:
1827 Result = !::CheckAndImm(Table, Index, N, SDISel);
1829 case SelectionDAGISel::OPC_CheckOrImm:
1830 Result = !::CheckOrImm(Table, Index, N, SDISel);
1838 /// FailIndex - If this match fails, this is the index to continue with.
1841 /// NodeStack - The node stack when the scope was formed.
1842 SmallVector<SDValue, 4> NodeStack;
1844 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1845 unsigned NumRecordedNodes;
1847 /// NumMatchedMemRefs - The number of matched memref entries.
1848 unsigned NumMatchedMemRefs;
1850 /// InputChain/InputFlag - The current chain/flag
1851 SDValue InputChain, InputFlag;
1853 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1854 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1859 SDNode *SelectionDAGISel::
1860 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1861 unsigned TableSize) {
1862 // FIXME: Should these even be selected? Handle these cases in the caller?
1863 switch (NodeToMatch->getOpcode()) {
1866 case ISD::EntryToken: // These nodes remain the same.
1867 case ISD::BasicBlock:
1869 //case ISD::VALUETYPE:
1870 //case ISD::CONDCODE:
1871 case ISD::HANDLENODE:
1872 case ISD::MDNODE_SDNODE:
1873 case ISD::TargetConstant:
1874 case ISD::TargetConstantFP:
1875 case ISD::TargetConstantPool:
1876 case ISD::TargetFrameIndex:
1877 case ISD::TargetExternalSymbol:
1878 case ISD::TargetBlockAddress:
1879 case ISD::TargetJumpTable:
1880 case ISD::TargetGlobalTLSAddress:
1881 case ISD::TargetGlobalAddress:
1882 case ISD::TokenFactor:
1883 case ISD::CopyFromReg:
1884 case ISD::CopyToReg:
1886 NodeToMatch->setNodeId(-1); // Mark selected.
1888 case ISD::AssertSext:
1889 case ISD::AssertZext:
1890 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1891 NodeToMatch->getOperand(0));
1893 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1894 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1897 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1899 // Set up the node stack with NodeToMatch as the only node on the stack.
1900 SmallVector<SDValue, 8> NodeStack;
1901 SDValue N = SDValue(NodeToMatch, 0);
1902 NodeStack.push_back(N);
1904 // MatchScopes - Scopes used when matching, if a match failure happens, this
1905 // indicates where to continue checking.
1906 SmallVector<MatchScope, 8> MatchScopes;
1908 // RecordedNodes - This is the set of nodes that have been recorded by the
1910 SmallVector<SDValue, 8> RecordedNodes;
1912 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1914 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1916 // These are the current input chain and flag for use when generating nodes.
1917 // Various Emit operations change these. For example, emitting a copytoreg
1918 // uses and updates these.
1919 SDValue InputChain, InputFlag;
1921 // ChainNodesMatched - If a pattern matches nodes that have input/output
1922 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1923 // which ones they are. The result is captured into this list so that we can
1924 // update the chain results when the pattern is complete.
1925 SmallVector<SDNode*, 3> ChainNodesMatched;
1926 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1928 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1929 NodeToMatch->dump(CurDAG);
1932 // Determine where to start the interpreter. Normally we start at opcode #0,
1933 // but if the state machine starts with an OPC_SwitchOpcode, then we
1934 // accelerate the first lookup (which is guaranteed to be hot) with the
1935 // OpcodeOffset table.
1936 unsigned MatcherIndex = 0;
1938 if (!OpcodeOffset.empty()) {
1939 // Already computed the OpcodeOffset table, just index into it.
1940 if (N.getOpcode() < OpcodeOffset.size())
1941 MatcherIndex = OpcodeOffset[N.getOpcode()];
1942 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1944 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1945 // Otherwise, the table isn't computed, but the state machine does start
1946 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1947 // is the first time we're selecting an instruction.
1950 // Get the size of this case.
1951 unsigned CaseSize = MatcherTable[Idx++];
1953 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1954 if (CaseSize == 0) break;
1956 // Get the opcode, add the index to the table.
1957 uint16_t Opc = MatcherTable[Idx++];
1958 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1959 if (Opc >= OpcodeOffset.size())
1960 OpcodeOffset.resize((Opc+1)*2);
1961 OpcodeOffset[Opc] = Idx;
1965 // Okay, do the lookup for the first opcode.
1966 if (N.getOpcode() < OpcodeOffset.size())
1967 MatcherIndex = OpcodeOffset[N.getOpcode()];
1971 assert(MatcherIndex < TableSize && "Invalid index");
1973 unsigned CurrentOpcodeIndex = MatcherIndex;
1975 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1978 // Okay, the semantics of this operation are that we should push a scope
1979 // then evaluate the first child. However, pushing a scope only to have
1980 // the first check fail (which then pops it) is inefficient. If we can
1981 // determine immediately that the first check (or first several) will
1982 // immediately fail, don't even bother pushing a scope for them.
1986 unsigned NumToSkip = MatcherTable[MatcherIndex++];
1987 if (NumToSkip & 128)
1988 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
1989 // Found the end of the scope with no match.
1990 if (NumToSkip == 0) {
1995 FailIndex = MatcherIndex+NumToSkip;
1997 unsigned MatcherIndexOfPredicate = MatcherIndex;
1998 (void)MatcherIndexOfPredicate; // silence warning.
2000 // If we can't evaluate this predicate without pushing a scope (e.g. if
2001 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2002 // push the scope and evaluate the full predicate chain.
2004 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2005 Result, *this, RecordedNodes);
2009 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2010 << "index " << MatcherIndexOfPredicate
2011 << ", continuing at " << FailIndex << "\n");
2012 ++NumDAGIselRetries;
2014 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2015 // move to the next case.
2016 MatcherIndex = FailIndex;
2019 // If the whole scope failed to match, bail.
2020 if (FailIndex == 0) break;
2022 // Push a MatchScope which indicates where to go if the first child fails
2024 MatchScope NewEntry;
2025 NewEntry.FailIndex = FailIndex;
2026 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2027 NewEntry.NumRecordedNodes = RecordedNodes.size();
2028 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2029 NewEntry.InputChain = InputChain;
2030 NewEntry.InputFlag = InputFlag;
2031 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2032 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2033 MatchScopes.push_back(NewEntry);
2036 case OPC_RecordNode:
2037 // Remember this node, it may end up being an operand in the pattern.
2038 RecordedNodes.push_back(N);
2041 case OPC_RecordChild0: case OPC_RecordChild1:
2042 case OPC_RecordChild2: case OPC_RecordChild3:
2043 case OPC_RecordChild4: case OPC_RecordChild5:
2044 case OPC_RecordChild6: case OPC_RecordChild7: {
2045 unsigned ChildNo = Opcode-OPC_RecordChild0;
2046 if (ChildNo >= N.getNumOperands())
2047 break; // Match fails if out of range child #.
2049 RecordedNodes.push_back(N->getOperand(ChildNo));
2052 case OPC_RecordMemRef:
2053 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2056 case OPC_CaptureFlagInput:
2057 // If the current node has an input flag, capture it in InputFlag.
2058 if (N->getNumOperands() != 0 &&
2059 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2060 InputFlag = N->getOperand(N->getNumOperands()-1);
2063 case OPC_MoveChild: {
2064 unsigned ChildNo = MatcherTable[MatcherIndex++];
2065 if (ChildNo >= N.getNumOperands())
2066 break; // Match fails if out of range child #.
2067 N = N.getOperand(ChildNo);
2068 NodeStack.push_back(N);
2072 case OPC_MoveParent:
2073 // Pop the current node off the NodeStack.
2074 NodeStack.pop_back();
2075 assert(!NodeStack.empty() && "Node stack imbalance!");
2076 N = NodeStack.back();
2080 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2082 case OPC_CheckPatternPredicate:
2083 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2085 case OPC_CheckPredicate:
2086 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2090 case OPC_CheckComplexPat: {
2091 unsigned CPNum = MatcherTable[MatcherIndex++];
2092 unsigned RecNo = MatcherTable[MatcherIndex++];
2093 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2094 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2099 case OPC_CheckOpcode:
2100 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2104 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2107 case OPC_SwitchOpcode: {
2108 unsigned CurNodeOpcode = N.getOpcode();
2109 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2112 // Get the size of this case.
2113 CaseSize = MatcherTable[MatcherIndex++];
2115 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2116 if (CaseSize == 0) break;
2118 uint16_t Opc = MatcherTable[MatcherIndex++];
2119 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2121 // If the opcode matches, then we will execute this case.
2122 if (CurNodeOpcode == Opc)
2125 // Otherwise, skip over this case.
2126 MatcherIndex += CaseSize;
2129 // If no cases matched, bail out.
2130 if (CaseSize == 0) break;
2132 // Otherwise, execute the case we found.
2133 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2134 << " to " << MatcherIndex << "\n");
2138 case OPC_SwitchType: {
2139 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2140 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2143 // Get the size of this case.
2144 CaseSize = MatcherTable[MatcherIndex++];
2146 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2147 if (CaseSize == 0) break;
2149 MVT::SimpleValueType CaseVT =
2150 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2151 if (CaseVT == MVT::iPTR)
2152 CaseVT = TLI.getPointerTy().SimpleTy;
2154 // If the VT matches, then we will execute this case.
2155 if (CurNodeVT == CaseVT)
2158 // Otherwise, skip over this case.
2159 MatcherIndex += CaseSize;
2162 // If no cases matched, bail out.
2163 if (CaseSize == 0) break;
2165 // Otherwise, execute the case we found.
2166 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2167 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2170 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2171 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2172 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2173 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2174 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2175 Opcode-OPC_CheckChild0Type))
2178 case OPC_CheckCondCode:
2179 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2181 case OPC_CheckValueType:
2182 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2184 case OPC_CheckInteger:
2185 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2187 case OPC_CheckAndImm:
2188 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2190 case OPC_CheckOrImm:
2191 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2194 case OPC_CheckFoldableChainNode: {
2195 assert(NodeStack.size() != 1 && "No parent node");
2196 // Verify that all intermediate nodes between the root and this one have
2198 bool HasMultipleUses = false;
2199 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2200 if (!NodeStack[i].hasOneUse()) {
2201 HasMultipleUses = true;
2204 if (HasMultipleUses) break;
2206 // Check to see that the target thinks this is profitable to fold and that
2207 // we can fold it without inducing cycles in the graph.
2208 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2210 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2211 NodeToMatch, OptLevel,
2212 true/*We validate our own chains*/))
2217 case OPC_EmitInteger: {
2218 MVT::SimpleValueType VT =
2219 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2220 int64_t Val = MatcherTable[MatcherIndex++];
2222 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2223 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2226 case OPC_EmitRegister: {
2227 MVT::SimpleValueType VT =
2228 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2229 unsigned RegNo = MatcherTable[MatcherIndex++];
2230 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2234 case OPC_EmitConvertToTarget: {
2235 // Convert from IMM/FPIMM to target version.
2236 unsigned RecNo = MatcherTable[MatcherIndex++];
2237 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2238 SDValue Imm = RecordedNodes[RecNo];
2240 if (Imm->getOpcode() == ISD::Constant) {
2241 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2242 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2243 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2244 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2245 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2248 RecordedNodes.push_back(Imm);
2252 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2253 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2254 // These are space-optimized forms of OPC_EmitMergeInputChains.
2255 assert(InputChain.getNode() == 0 &&
2256 "EmitMergeInputChains should be the first chain producing node");
2257 assert(ChainNodesMatched.empty() &&
2258 "Should only have one EmitMergeInputChains per match");
2260 // Read all of the chained nodes.
2261 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2262 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2263 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2265 // FIXME: What if other value results of the node have uses not matched
2267 if (ChainNodesMatched.back() != NodeToMatch &&
2268 !RecordedNodes[RecNo].hasOneUse()) {
2269 ChainNodesMatched.clear();
2273 // Merge the input chains if they are not intra-pattern references.
2274 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2276 if (InputChain.getNode() == 0)
2277 break; // Failed to merge.
2281 case OPC_EmitMergeInputChains: {
2282 assert(InputChain.getNode() == 0 &&
2283 "EmitMergeInputChains should be the first chain producing node");
2284 // This node gets a list of nodes we matched in the input that have
2285 // chains. We want to token factor all of the input chains to these nodes
2286 // together. However, if any of the input chains is actually one of the
2287 // nodes matched in this pattern, then we have an intra-match reference.
2288 // Ignore these because the newly token factored chain should not refer to
2290 unsigned NumChains = MatcherTable[MatcherIndex++];
2291 assert(NumChains != 0 && "Can't TF zero chains");
2293 assert(ChainNodesMatched.empty() &&
2294 "Should only have one EmitMergeInputChains per match");
2296 // Read all of the chained nodes.
2297 for (unsigned i = 0; i != NumChains; ++i) {
2298 unsigned RecNo = MatcherTable[MatcherIndex++];
2299 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2300 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2302 // FIXME: What if other value results of the node have uses not matched
2304 if (ChainNodesMatched.back() != NodeToMatch &&
2305 !RecordedNodes[RecNo].hasOneUse()) {
2306 ChainNodesMatched.clear();
2311 // If the inner loop broke out, the match fails.
2312 if (ChainNodesMatched.empty())
2315 // Merge the input chains if they are not intra-pattern references.
2316 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2318 if (InputChain.getNode() == 0)
2319 break; // Failed to merge.
2324 case OPC_EmitCopyToReg: {
2325 unsigned RecNo = MatcherTable[MatcherIndex++];
2326 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2327 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2329 if (InputChain.getNode() == 0)
2330 InputChain = CurDAG->getEntryNode();
2332 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2333 DestPhysReg, RecordedNodes[RecNo],
2336 InputFlag = InputChain.getValue(1);
2340 case OPC_EmitNodeXForm: {
2341 unsigned XFormNo = MatcherTable[MatcherIndex++];
2342 unsigned RecNo = MatcherTable[MatcherIndex++];
2343 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2344 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2349 case OPC_MorphNodeTo: {
2350 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2351 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2352 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2353 // Get the result VT list.
2354 unsigned NumVTs = MatcherTable[MatcherIndex++];
2355 SmallVector<EVT, 4> VTs;
2356 for (unsigned i = 0; i != NumVTs; ++i) {
2357 MVT::SimpleValueType VT =
2358 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2359 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2363 if (EmitNodeInfo & OPFL_Chain)
2364 VTs.push_back(MVT::Other);
2365 if (EmitNodeInfo & OPFL_FlagOutput)
2366 VTs.push_back(MVT::Flag);
2368 // This is hot code, so optimize the two most common cases of 1 and 2
2371 if (VTs.size() == 1)
2372 VTList = CurDAG->getVTList(VTs[0]);
2373 else if (VTs.size() == 2)
2374 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2376 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2378 // Get the operand list.
2379 unsigned NumOps = MatcherTable[MatcherIndex++];
2380 SmallVector<SDValue, 8> Ops;
2381 for (unsigned i = 0; i != NumOps; ++i) {
2382 unsigned RecNo = MatcherTable[MatcherIndex++];
2384 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2386 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2387 Ops.push_back(RecordedNodes[RecNo]);
2390 // If there are variadic operands to add, handle them now.
2391 if (EmitNodeInfo & OPFL_VariadicInfo) {
2392 // Determine the start index to copy from.
2393 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2394 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2395 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2396 "Invalid variadic node");
2397 // Copy all of the variadic operands, not including a potential flag
2399 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2401 SDValue V = NodeToMatch->getOperand(i);
2402 if (V.getValueType() == MVT::Flag) break;
2407 // If this has chain/flag inputs, add them.
2408 if (EmitNodeInfo & OPFL_Chain)
2409 Ops.push_back(InputChain);
2410 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2411 Ops.push_back(InputFlag);
2415 if (Opcode != OPC_MorphNodeTo) {
2416 // If this is a normal EmitNode command, just create the new node and
2417 // add the results to the RecordedNodes list.
2418 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2419 VTList, Ops.data(), Ops.size());
2421 // Add all the non-flag/non-chain results to the RecordedNodes list.
2422 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2423 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2424 RecordedNodes.push_back(SDValue(Res, i));
2428 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2432 // If the node had chain/flag results, update our notion of the current
2434 if (EmitNodeInfo & OPFL_FlagOutput) {
2435 InputFlag = SDValue(Res, VTs.size()-1);
2436 if (EmitNodeInfo & OPFL_Chain)
2437 InputChain = SDValue(Res, VTs.size()-2);
2438 } else if (EmitNodeInfo & OPFL_Chain)
2439 InputChain = SDValue(Res, VTs.size()-1);
2441 // If the OPFL_MemRefs flag is set on this node, slap all of the
2442 // accumulated memrefs onto it.
2444 // FIXME: This is vastly incorrect for patterns with multiple outputs
2445 // instructions that access memory and for ComplexPatterns that match
2447 if (EmitNodeInfo & OPFL_MemRefs) {
2448 MachineSDNode::mmo_iterator MemRefs =
2449 MF->allocateMemRefsArray(MatchedMemRefs.size());
2450 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2451 cast<MachineSDNode>(Res)
2452 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2456 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2457 << " node: "; Res->dump(CurDAG); errs() << "\n");
2459 // If this was a MorphNodeTo then we're completely done!
2460 if (Opcode == OPC_MorphNodeTo) {
2461 // Update chain and flag uses.
2462 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2463 InputFlag, FlagResultNodesMatched, true);
2470 case OPC_MarkFlagResults: {
2471 unsigned NumNodes = MatcherTable[MatcherIndex++];
2473 // Read and remember all the flag-result nodes.
2474 for (unsigned i = 0; i != NumNodes; ++i) {
2475 unsigned RecNo = MatcherTable[MatcherIndex++];
2477 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2479 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2480 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2485 case OPC_CompleteMatch: {
2486 // The match has been completed, and any new nodes (if any) have been
2487 // created. Patch up references to the matched dag to use the newly
2489 unsigned NumResults = MatcherTable[MatcherIndex++];
2491 for (unsigned i = 0; i != NumResults; ++i) {
2492 unsigned ResSlot = MatcherTable[MatcherIndex++];
2494 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2496 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2497 SDValue Res = RecordedNodes[ResSlot];
2499 assert(i < NodeToMatch->getNumValues() &&
2500 NodeToMatch->getValueType(i) != MVT::Other &&
2501 NodeToMatch->getValueType(i) != MVT::Flag &&
2502 "Invalid number of results to complete!");
2503 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2504 NodeToMatch->getValueType(i) == MVT::iPTR ||
2505 Res.getValueType() == MVT::iPTR ||
2506 NodeToMatch->getValueType(i).getSizeInBits() ==
2507 Res.getValueType().getSizeInBits()) &&
2508 "invalid replacement");
2509 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2512 // If the root node defines a flag, add it to the flag nodes to update
2514 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2515 FlagResultNodesMatched.push_back(NodeToMatch);
2517 // Update chain and flag uses.
2518 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2519 InputFlag, FlagResultNodesMatched, false);
2521 assert(NodeToMatch->use_empty() &&
2522 "Didn't replace all uses of the node?");
2524 // FIXME: We just return here, which interacts correctly with SelectRoot
2525 // above. We should fix this to not return an SDNode* anymore.
2530 // If the code reached this point, then the match failed. See if there is
2531 // another child to try in the current 'Scope', otherwise pop it until we
2532 // find a case to check.
2533 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2534 ++NumDAGIselRetries;
2536 if (MatchScopes.empty()) {
2537 CannotYetSelect(NodeToMatch);
2541 // Restore the interpreter state back to the point where the scope was
2543 MatchScope &LastScope = MatchScopes.back();
2544 RecordedNodes.resize(LastScope.NumRecordedNodes);
2546 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2547 N = NodeStack.back();
2549 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2550 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2551 MatcherIndex = LastScope.FailIndex;
2553 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2555 InputChain = LastScope.InputChain;
2556 InputFlag = LastScope.InputFlag;
2557 if (!LastScope.HasChainNodesMatched)
2558 ChainNodesMatched.clear();
2559 if (!LastScope.HasFlagResultNodesMatched)
2560 FlagResultNodesMatched.clear();
2562 // Check to see what the offset is at the new MatcherIndex. If it is zero
2563 // we have reached the end of this scope, otherwise we have another child
2564 // in the current scope to try.
2565 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2566 if (NumToSkip & 128)
2567 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2569 // If we have another child in this scope to match, update FailIndex and
2571 if (NumToSkip != 0) {
2572 LastScope.FailIndex = MatcherIndex+NumToSkip;
2576 // End of this scope, pop it and try the next child in the containing
2578 MatchScopes.pop_back();
2585 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2587 raw_string_ostream Msg(msg);
2588 Msg << "Cannot yet select: ";
2590 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2591 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2592 N->getOpcode() != ISD::INTRINSIC_VOID) {
2593 N->printrFull(Msg, CurDAG);
2595 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2597 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2598 if (iid < Intrinsic::num_intrinsics)
2599 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2600 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2601 Msg << "target intrinsic %" << TII->getName(iid);
2603 Msg << "unknown intrinsic #" << iid;
2605 report_fatal_error(Msg.str());
2608 char SelectionDAGISel::ID = 0;