1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetIntrinsicInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/ADT/Statistic.h"
53 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
54 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
57 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
58 cl::desc("Enable verbose messages in the \"fast\" "
59 "instruction selector"));
61 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
62 cl::desc("Enable abort calls when \"fast\" instruction fails"));
66 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
67 cl::desc("Pop up a window to show dags before the first "
70 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
71 cl::desc("Pop up a window to show dags before legalize types"));
73 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
74 cl::desc("Pop up a window to show dags before legalize"));
76 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
77 cl::desc("Pop up a window to show dags before the second "
80 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before the post legalize types"
82 " dag combine pass"));
84 ViewISelDAGs("view-isel-dags", cl::Hidden,
85 cl::desc("Pop up a window to show isel dags as they are selected"));
87 ViewSchedDAGs("view-sched-dags", cl::Hidden,
88 cl::desc("Pop up a window to show sched dags as they are processed"));
90 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
91 cl::desc("Pop up a window to show SUnit dags after they are processed"));
93 static const bool ViewDAGCombine1 = false,
94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
95 ViewDAGCombine2 = false,
96 ViewDAGCombineLT = false,
97 ViewISelDAGs = false, ViewSchedDAGs = false,
98 ViewSUnitDAGs = false;
101 //===---------------------------------------------------------------------===//
103 /// RegisterScheduler class - Track the registration of instruction schedulers.
105 //===---------------------------------------------------------------------===//
106 MachinePassRegistry RegisterScheduler::Registry;
108 //===---------------------------------------------------------------------===//
110 /// ISHeuristic command line option for instruction schedulers.
112 //===---------------------------------------------------------------------===//
113 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
114 RegisterPassParser<RegisterScheduler> >
115 ISHeuristic("pre-RA-sched",
116 cl::init(&createDefaultScheduler),
117 cl::desc("Instruction schedulers available (before register"
120 static RegisterScheduler
121 defaultListDAGScheduler("default", "Best scheduler for the target",
122 createDefaultScheduler);
125 //===--------------------------------------------------------------------===//
126 /// createDefaultScheduler - This creates an instruction scheduler appropriate
128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
129 CodeGenOpt::Level OptLevel) {
130 const TargetLowering &TLI = IS->getTargetLowering();
132 if (OptLevel == CodeGenOpt::None)
133 return createFastDAGScheduler(IS, OptLevel);
134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
135 return createTDListDAGScheduler(IS, OptLevel);
136 assert(TLI.getSchedulingPreference() ==
137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
138 return createBURRListDAGScheduler(IS, OptLevel);
142 // EmitInstrWithCustomInserter - This method should be implemented by targets
143 // that mark instructions with the 'usesCustomInserter' flag. These
144 // instructions are special in various ways, which require special support to
145 // insert. The specified MachineInstr is created but not inserted into any
146 // basic blocks, and this method is called to expand it into a sequence of
147 // instructions, potentially also creating new basic blocks and control flow.
148 // When new basic blocks are inserted and the edges from MBB to its successors
149 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
151 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
152 MachineBasicBlock *MBB,
153 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
155 dbgs() << "If a target marks an instruction with "
156 "'usesCustomInserter', it must implement "
157 "TargetLowering::EmitInstrWithCustomInserter!";
163 //===----------------------------------------------------------------------===//
164 // SelectionDAGISel code
165 //===----------------------------------------------------------------------===//
167 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
169 FuncInfo(new FunctionLoweringInfo(TLI)),
170 CurDAG(new SelectionDAG(tm, *FuncInfo)),
171 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
177 SelectionDAGISel::~SelectionDAGISel() {
183 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
184 AU.addRequired<AliasAnalysis>();
185 AU.addPreserved<AliasAnalysis>();
186 AU.addRequired<GCModuleInfo>();
187 AU.addPreserved<GCModuleInfo>();
188 MachineFunctionPass::getAnalysisUsage(AU);
191 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
192 // Do some sanity-checking on the command-line options.
193 assert((!EnableFastISelVerbose || EnableFastISel) &&
194 "-fast-isel-verbose requires -fast-isel");
195 assert((!EnableFastISelAbort || EnableFastISel) &&
196 "-fast-isel-abort requires -fast-isel");
198 const Function &Fn = *mf.getFunction();
199 const TargetInstrInfo &TII = *TM.getInstrInfo();
200 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
203 RegInfo = &MF->getRegInfo();
204 AA = &getAnalysis<AliasAnalysis>();
205 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
207 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
210 FuncInfo->set(Fn, *MF, EnableFastISel);
213 SelectAllBasicBlocks(Fn);
215 // Release function-specific state. SDB and CurDAG are already cleared
219 // If the first basic block in the function has live ins that need to be
220 // copied into vregs, emit the copies into the top of the block before
221 // emitting the code for the block.
222 RegInfo->EmitLiveInCopies(MF->begin(), TRI, TII);
228 SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB,
229 const BasicBlock *LLVMBB,
230 BasicBlock::const_iterator Begin,
231 BasicBlock::const_iterator End,
233 // Lower all of the non-terminator instructions. If a call is emitted
234 // as a tail call, cease emitting nodes for this block. Terminators
235 // are handled below.
236 for (BasicBlock::const_iterator I = Begin;
237 I != End && !SDB->HasTailCall && !isa<TerminatorInst>(I);
241 if (!SDB->HasTailCall) {
242 // Ensure that all instructions which are used outside of their defining
243 // blocks are available as virtual registers. Invoke is handled elsewhere.
244 for (BasicBlock::const_iterator I = Begin; I != End; ++I)
245 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
246 SDB->CopyToExportRegsIfNeeded(I);
248 // Handle PHI nodes in successor blocks.
249 if (End == LLVMBB->end()) {
250 HandlePHINodesInSuccessorBlocks(LLVMBB);
252 // Lower the terminator after the copies are emitted.
253 SDB->visit(*LLVMBB->getTerminator());
257 // Make sure the root of the DAG is up-to-date.
258 CurDAG->setRoot(SDB->getControlRoot());
260 // Final step, emit the lowered DAG as machine code.
261 BB = CodeGenAndEmitDAG(BB);
262 HadTailCall = SDB->HasTailCall;
268 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
269 /// nodes from the worklist.
270 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
271 SmallVector<SDNode*, 128> &Worklist;
272 SmallPtrSet<SDNode*, 128> &InWorklist;
274 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
275 SmallPtrSet<SDNode*, 128> &inwl)
276 : Worklist(wl), InWorklist(inwl) {}
278 void RemoveFromWorklist(SDNode *N) {
279 if (!InWorklist.erase(N)) return;
281 SmallVector<SDNode*, 128>::iterator I =
282 std::find(Worklist.begin(), Worklist.end(), N);
283 assert(I != Worklist.end() && "Not in worklist");
285 *I = Worklist.back();
289 virtual void NodeDeleted(SDNode *N, SDNode *E) {
290 RemoveFromWorklist(N);
293 virtual void NodeUpdated(SDNode *N) {
299 /// TrivialTruncElim - Eliminate some trivial nops that can result from
300 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
301 static bool TrivialTruncElim(SDValue Op,
302 TargetLowering::TargetLoweringOpt &TLO) {
303 SDValue N0 = Op.getOperand(0);
304 EVT VT = Op.getValueType();
305 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
306 N0.getOpcode() == ISD::SIGN_EXTEND ||
307 N0.getOpcode() == ISD::ANY_EXTEND) &&
308 N0.getOperand(0).getValueType() == VT) {
309 return TLO.CombineTo(Op, N0.getOperand(0));
314 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
315 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
316 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
317 void SelectionDAGISel::ShrinkDemandedOps() {
318 SmallVector<SDNode*, 128> Worklist;
319 SmallPtrSet<SDNode*, 128> InWorklist;
321 // Add all the dag nodes to the worklist.
322 Worklist.reserve(CurDAG->allnodes_size());
323 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
324 E = CurDAG->allnodes_end(); I != E; ++I) {
325 Worklist.push_back(I);
326 InWorklist.insert(I);
329 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true);
330 while (!Worklist.empty()) {
331 SDNode *N = Worklist.pop_back_val();
334 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
335 // Deleting this node may make its operands dead, add them to the worklist
336 // if they aren't already there.
337 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
338 if (InWorklist.insert(N->getOperand(i).getNode()))
339 Worklist.push_back(N->getOperand(i).getNode());
341 CurDAG->DeleteNode(N);
345 // Run ShrinkDemandedOp on scalar binary operations.
346 if (N->getNumValues() != 1 ||
347 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
350 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
351 APInt Demanded = APInt::getAllOnesValue(BitWidth);
352 APInt KnownZero, KnownOne;
353 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
354 KnownZero, KnownOne, TLO) &&
355 (N->getOpcode() != ISD::TRUNCATE ||
356 !TrivialTruncElim(SDValue(N, 0), TLO)))
360 assert(!InWorklist.count(N) && "Already in worklist");
361 Worklist.push_back(N);
362 InWorklist.insert(N);
364 // Replace the old value with the new one.
365 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
366 TLO.Old.getNode()->dump(CurDAG);
367 errs() << "\nWith: ";
368 TLO.New.getNode()->dump(CurDAG);
371 if (InWorklist.insert(TLO.New.getNode()))
372 Worklist.push_back(TLO.New.getNode());
374 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
375 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
377 if (!TLO.Old.getNode()->use_empty()) continue;
379 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
381 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
382 if (OpNode->hasOneUse()) {
383 // Add OpNode to the end of the list to revisit.
384 DeadNodes.RemoveFromWorklist(OpNode);
385 Worklist.push_back(OpNode);
386 InWorklist.insert(OpNode);
390 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
391 CurDAG->DeleteNode(TLO.Old.getNode());
395 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
396 SmallPtrSet<SDNode*, 128> VisitedNodes;
397 SmallVector<SDNode*, 128> Worklist;
399 Worklist.push_back(CurDAG->getRoot().getNode());
406 SDNode *N = Worklist.pop_back_val();
408 // If we've already seen this node, ignore it.
409 if (!VisitedNodes.insert(N))
412 // Otherwise, add all chain operands to the worklist.
413 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
414 if (N->getOperand(i).getValueType() == MVT::Other)
415 Worklist.push_back(N->getOperand(i).getNode());
417 // If this is a CopyToReg with a vreg dest, process it.
418 if (N->getOpcode() != ISD::CopyToReg)
421 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
422 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
425 // Ignore non-scalar or non-integer values.
426 SDValue Src = N->getOperand(2);
427 EVT SrcVT = Src.getValueType();
428 if (!SrcVT.isInteger() || SrcVT.isVector())
431 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
432 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
433 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
435 // Only install this information if it tells us something.
436 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
437 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
438 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
439 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
440 FunctionLoweringInfo::LiveOutInfo &LOI =
441 FuncInfo->LiveOutRegInfo[DestReg];
442 LOI.NumSignBits = NumSignBits;
443 LOI.KnownOne = KnownOne;
444 LOI.KnownZero = KnownZero;
446 } while (!Worklist.empty());
449 MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) {
450 std::string GroupName;
451 if (TimePassesIsEnabled)
452 GroupName = "Instruction Selection and Scheduling";
453 std::string BlockName;
454 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
455 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
457 BlockName = MF->getFunction()->getNameStr() + ":" +
458 BB->getBasicBlock()->getNameStr();
460 DEBUG(dbgs() << "Initial selection DAG:\n");
461 DEBUG(CurDAG->dump());
463 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
465 // Run the DAG combiner in pre-legalize mode.
466 if (TimePassesIsEnabled) {
467 NamedRegionTimer T("DAG Combining 1", GroupName);
468 CurDAG->Combine(Unrestricted, *AA, OptLevel);
470 CurDAG->Combine(Unrestricted, *AA, OptLevel);
473 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
474 DEBUG(CurDAG->dump());
476 // Second step, hack on the DAG until it only uses operations and types that
477 // the target supports.
478 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
482 if (TimePassesIsEnabled) {
483 NamedRegionTimer T("Type Legalization", GroupName);
484 Changed = CurDAG->LegalizeTypes();
486 Changed = CurDAG->LegalizeTypes();
489 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
490 DEBUG(CurDAG->dump());
493 if (ViewDAGCombineLT)
494 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
496 // Run the DAG combiner in post-type-legalize mode.
497 if (TimePassesIsEnabled) {
498 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
499 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
501 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
504 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
505 DEBUG(CurDAG->dump());
508 if (TimePassesIsEnabled) {
509 NamedRegionTimer T("Vector Legalization", GroupName);
510 Changed = CurDAG->LegalizeVectors();
512 Changed = CurDAG->LegalizeVectors();
516 if (TimePassesIsEnabled) {
517 NamedRegionTimer T("Type Legalization 2", GroupName);
518 CurDAG->LegalizeTypes();
520 CurDAG->LegalizeTypes();
523 if (ViewDAGCombineLT)
524 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
526 // Run the DAG combiner in post-type-legalize mode.
527 if (TimePassesIsEnabled) {
528 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
529 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
531 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
534 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
535 DEBUG(CurDAG->dump());
538 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
540 if (TimePassesIsEnabled) {
541 NamedRegionTimer T("DAG Legalization", GroupName);
542 CurDAG->Legalize(OptLevel);
544 CurDAG->Legalize(OptLevel);
547 DEBUG(dbgs() << "Legalized selection DAG:\n");
548 DEBUG(CurDAG->dump());
550 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
552 // Run the DAG combiner in post-legalize mode.
553 if (TimePassesIsEnabled) {
554 NamedRegionTimer T("DAG Combining 2", GroupName);
555 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
557 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
560 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
561 DEBUG(CurDAG->dump());
563 if (OptLevel != CodeGenOpt::None) {
565 ComputeLiveOutVRegInfo();
568 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
570 // Third, instruction select all of the operations to machine code, adding the
571 // code to the MachineBasicBlock.
572 if (TimePassesIsEnabled) {
573 NamedRegionTimer T("Instruction Selection", GroupName);
574 DoInstructionSelection();
576 DoInstructionSelection();
579 DEBUG(dbgs() << "Selected selection DAG:\n");
580 DEBUG(CurDAG->dump());
582 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
584 // Schedule machine code.
585 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
586 if (TimePassesIsEnabled) {
587 NamedRegionTimer T("Instruction Scheduling", GroupName);
588 Scheduler->Run(CurDAG, BB, BB->end());
590 Scheduler->Run(CurDAG, BB, BB->end());
593 if (ViewSUnitDAGs) Scheduler->viewGraph();
595 // Emit machine code to BB. This can change 'BB' to the last block being
597 if (TimePassesIsEnabled) {
598 NamedRegionTimer T("Instruction Creation", GroupName);
599 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
601 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
604 // Free the scheduler state.
605 if (TimePassesIsEnabled) {
606 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
612 DEBUG(dbgs() << "Selected machine code:\n");
617 void SelectionDAGISel::DoInstructionSelection() {
618 DEBUG(errs() << "===== Instruction selection begins:\n");
622 // Select target instructions for the DAG.
624 // Number all nodes with a topological order and set DAGSize.
625 DAGSize = CurDAG->AssignTopologicalOrder();
627 // Create a dummy node (which is not added to allnodes), that adds
628 // a reference to the root node, preventing it from being deleted,
629 // and tracking any changes of the root.
630 HandleSDNode Dummy(CurDAG->getRoot());
631 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
634 // The AllNodes list is now topological-sorted. Visit the
635 // nodes by starting at the end of the list (the root of the
636 // graph) and preceding back toward the beginning (the entry
638 while (ISelPosition != CurDAG->allnodes_begin()) {
639 SDNode *Node = --ISelPosition;
640 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
641 // but there are currently some corner cases that it misses. Also, this
642 // makes it theoretically possible to disable the DAGCombiner.
643 if (Node->use_empty())
646 SDNode *ResNode = Select(Node);
648 // FIXME: This is pretty gross. 'Select' should be changed to not return
649 // anything at all and this code should be nuked with a tactical strike.
651 // If node should not be replaced, continue with the next one.
652 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
656 ReplaceUses(Node, ResNode);
658 // If after the replacement this node is not used any more,
659 // remove this dead node.
660 if (Node->use_empty()) { // Don't delete EntryToken, etc.
661 ISelUpdater ISU(ISelPosition);
662 CurDAG->RemoveDeadNode(Node, &ISU);
666 CurDAG->setRoot(Dummy.getValue());
668 DEBUG(errs() << "===== Instruction selection ends:\n");
670 PostprocessISelDAG();
673 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
674 /// do other setup for EH landing-pad blocks.
675 void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) {
676 // Add a label to mark the beginning of the landing pad. Deletion of the
677 // landing pad can thus be detected via the MachineModuleInfo.
678 MCSymbol *Label = MF->getMMI().addLandingPad(BB);
680 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
681 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
683 // Mark exception register as live in.
684 unsigned Reg = TLI.getExceptionAddressRegister();
685 if (Reg) BB->addLiveIn(Reg);
687 // Mark exception selector register as live in.
688 Reg = TLI.getExceptionSelectorRegister();
689 if (Reg) BB->addLiveIn(Reg);
691 // FIXME: Hack around an exception handling flaw (PR1508): the personality
692 // function and list of typeids logically belong to the invoke (or, if you
693 // like, the basic block containing the invoke), and need to be associated
694 // with it in the dwarf exception handling tables. Currently however the
695 // information is provided by an intrinsic (eh.selector) that can be moved
696 // to unexpected places by the optimizers: if the unwind edge is critical,
697 // then breaking it can result in the intrinsics being in the successor of
698 // the landing pad, not the landing pad itself. This results
699 // in exceptions not being caught because no typeids are associated with
700 // the invoke. This may not be the only way things can go wrong, but it
701 // is the only way we try to work around for the moment.
702 const BasicBlock *LLVMBB = BB->getBasicBlock();
703 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
705 if (Br && Br->isUnconditional()) { // Critical edge?
706 BasicBlock::const_iterator I, E;
707 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
708 if (isa<EHSelectorInst>(I))
712 // No catch info found - try to extract some from the successor.
713 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
717 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
718 // Initialize the Fast-ISel state, if needed.
719 FastISel *FastIS = 0;
721 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
722 FuncInfo->StaticAllocaMap
724 , FuncInfo->CatchInfoLost
728 // Iterate over all basic blocks in the function.
729 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
730 const BasicBlock *LLVMBB = &*I;
731 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB];
733 BasicBlock::const_iterator const Begin = LLVMBB->begin();
734 BasicBlock::const_iterator const End = LLVMBB->end();
735 BasicBlock::const_iterator BI = Begin;
737 // Lower any arguments needed in this block if this is the entry block.
738 bool SuppressFastISel = false;
739 if (LLVMBB == &Fn.getEntryBlock()) {
740 LowerArguments(LLVMBB);
742 // If any of the arguments has the byval attribute, forgo
743 // fast-isel in the entry block.
746 for (Function::const_arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
748 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
749 if (EnableFastISelVerbose || EnableFastISelAbort)
750 dbgs() << "FastISel skips entry block due to byval argument\n";
751 SuppressFastISel = true;
757 // Setup an EH landing-pad block.
758 if (BB->isLandingPad())
759 PrepareEHLandingPad(BB);
761 // Before doing SelectionDAG ISel, see if FastISel has been requested.
762 if (FastIS && !SuppressFastISel) {
763 // Emit code for any incoming arguments. This must happen before
764 // beginning FastISel on the entry block.
765 if (LLVMBB == &Fn.getEntryBlock()) {
766 CurDAG->setRoot(SDB->getControlRoot());
767 BB = CodeGenAndEmitDAG(BB);
770 FastIS->startNewBlock(BB);
771 // Do FastISel on as many instructions as possible.
772 for (; BI != End; ++BI) {
773 // Just before the terminator instruction, insert instructions to
774 // feed PHI nodes in successor blocks.
775 if (isa<TerminatorInst>(BI))
776 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
777 ++NumFastIselFailures;
778 if (EnableFastISelVerbose || EnableFastISelAbort) {
779 dbgs() << "FastISel miss: ";
782 assert(!EnableFastISelAbort &&
783 "FastISel didn't handle a PHI in a successor");
787 // Try to select the instruction with FastISel.
788 if (FastIS->SelectInstruction(BI))
791 // Then handle certain instructions as single-LLVM-Instruction blocks.
792 if (isa<CallInst>(BI)) {
793 ++NumFastIselFailures;
794 if (EnableFastISelVerbose || EnableFastISelAbort) {
795 dbgs() << "FastISel missed call: ";
799 if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
800 unsigned &R = FuncInfo->ValueMap[BI];
802 R = FuncInfo->CreateRegForValue(BI);
805 bool HadTailCall = false;
806 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall);
808 // If the call was emitted as a tail call, we're done with the block.
814 // If the instruction was codegen'd with multiple blocks,
815 // inform the FastISel object where to resume inserting.
816 FastIS->setCurrentBlock(BB);
820 // Otherwise, give up on FastISel for the rest of the block.
821 // For now, be a little lenient about non-branch terminators.
822 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
823 ++NumFastIselFailures;
824 if (EnableFastISelVerbose || EnableFastISelAbort) {
825 dbgs() << "FastISel miss: ";
828 if (EnableFastISelAbort)
829 // The "fast" selector couldn't handle something and bailed.
830 // For the purpose of debugging, just abort.
831 llvm_unreachable("FastISel didn't select the entire block");
837 // Run SelectionDAG instruction selection on the remainder of the block
838 // not handled by FastISel. If FastISel is not run, this is the entire
842 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall);
845 FinishBasicBlock(BB);
852 SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) {
854 DEBUG(dbgs() << "Target-post-processed machine code:\n");
857 DEBUG(dbgs() << "Total amount of phi nodes to update: "
858 << SDB->PHINodesToUpdate.size() << "\n");
859 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
860 dbgs() << "Node " << i << " : ("
861 << SDB->PHINodesToUpdate[i].first
862 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
864 // Next, now that we know what the last MBB the LLVM BB expanded is, update
865 // PHI nodes in successors.
866 if (SDB->SwitchCases.empty() &&
867 SDB->JTCases.empty() &&
868 SDB->BitTestCases.empty()) {
869 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
870 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
871 assert(PHI->isPHI() &&
872 "This is not a machine PHI node that we are updating!");
873 if (!BB->isSuccessor(PHI->getParent()))
875 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
877 PHI->addOperand(MachineOperand::CreateMBB(BB));
879 SDB->PHINodesToUpdate.clear();
883 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
884 // Lower header first, if it wasn't already lowered
885 if (!SDB->BitTestCases[i].Emitted) {
886 // Set the current basic block to the mbb we wish to insert the code into
887 BB = SDB->BitTestCases[i].Parent;
889 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB);
890 CurDAG->setRoot(SDB->getRoot());
891 BB = CodeGenAndEmitDAG(BB);
895 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
896 // Set the current basic block to the mbb we wish to insert the code into
897 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
900 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
901 SDB->BitTestCases[i].Reg,
902 SDB->BitTestCases[i].Cases[j],
905 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
906 SDB->BitTestCases[i].Reg,
907 SDB->BitTestCases[i].Cases[j],
911 CurDAG->setRoot(SDB->getRoot());
912 BB = CodeGenAndEmitDAG(BB);
917 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
918 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
919 MachineBasicBlock *PHIBB = PHI->getParent();
920 assert(PHI->isPHI() &&
921 "This is not a machine PHI node that we are updating!");
922 // This is "default" BB. We have two jumps to it. From "header" BB and
923 // from last "case" BB.
924 if (PHIBB == SDB->BitTestCases[i].Default) {
925 PHI->addOperand(MachineOperand::
926 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
927 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
928 PHI->addOperand(MachineOperand::
929 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
930 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
933 // One of "cases" BB.
934 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
936 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
937 if (cBB->isSuccessor(PHIBB)) {
938 PHI->addOperand(MachineOperand::
939 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
940 PHI->addOperand(MachineOperand::CreateMBB(cBB));
945 SDB->BitTestCases.clear();
947 // If the JumpTable record is filled in, then we need to emit a jump table.
948 // Updating the PHI nodes is tricky in this case, since we need to determine
949 // whether the PHI is a successor of the range check MBB or the jump table MBB
950 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
951 // Lower header first, if it wasn't already lowered
952 if (!SDB->JTCases[i].first.Emitted) {
953 // Set the current basic block to the mbb we wish to insert the code into
954 BB = SDB->JTCases[i].first.HeaderBB;
956 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
958 CurDAG->setRoot(SDB->getRoot());
959 BB = CodeGenAndEmitDAG(BB);
963 // Set the current basic block to the mbb we wish to insert the code into
964 BB = SDB->JTCases[i].second.MBB;
966 SDB->visitJumpTable(SDB->JTCases[i].second);
967 CurDAG->setRoot(SDB->getRoot());
968 BB = CodeGenAndEmitDAG(BB);
972 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
973 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
974 MachineBasicBlock *PHIBB = PHI->getParent();
975 assert(PHI->isPHI() &&
976 "This is not a machine PHI node that we are updating!");
977 // "default" BB. We can go there only from header BB.
978 if (PHIBB == SDB->JTCases[i].second.Default) {
980 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
982 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
984 // JT BB. Just iterate over successors here
985 if (BB->isSuccessor(PHIBB)) {
987 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
988 PHI->addOperand(MachineOperand::CreateMBB(BB));
992 SDB->JTCases.clear();
994 // If the switch block involved a branch to one of the actual successors, we
995 // need to update PHI nodes in that block.
996 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
997 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
998 assert(PHI->isPHI() &&
999 "This is not a machine PHI node that we are updating!");
1000 if (BB->isSuccessor(PHI->getParent())) {
1001 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1003 PHI->addOperand(MachineOperand::CreateMBB(BB));
1007 // If we generated any switch lowering information, build and codegen any
1008 // additional DAGs necessary.
1009 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1010 // Set the current basic block to the mbb we wish to insert the code into
1011 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1014 SDB->visitSwitchCase(SDB->SwitchCases[i], BB);
1015 CurDAG->setRoot(SDB->getRoot());
1016 BB = CodeGenAndEmitDAG(BB);
1018 // Handle any PHI nodes in successors of this chunk, as if we were coming
1019 // from the original BB before switch expansion. Note that PHI nodes can
1020 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1021 // handle them the right number of times.
1022 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1023 // If new BB's are created during scheduling, the edges may have been
1024 // updated. That is, the edge from ThisBB to BB may have been split and
1025 // BB's predecessor is now another block.
1026 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1027 SDB->EdgeMapping.find(BB);
1028 if (EI != SDB->EdgeMapping.end())
1029 ThisBB = EI->second;
1031 // BB may have been removed from the CFG if a branch was constant folded.
1032 if (ThisBB->isSuccessor(BB)) {
1033 for (MachineBasicBlock::iterator Phi = BB->begin();
1034 Phi != BB->end() && Phi->isPHI();
1036 // This value for this PHI node is recorded in PHINodesToUpdate.
1037 for (unsigned pn = 0; ; ++pn) {
1038 assert(pn != SDB->PHINodesToUpdate.size() &&
1039 "Didn't find PHI entry!");
1040 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1041 Phi->addOperand(MachineOperand::
1042 CreateReg(SDB->PHINodesToUpdate[pn].second,
1044 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1051 // Don't process RHS if same block as LHS.
1052 if (BB == SDB->SwitchCases[i].FalseBB)
1053 SDB->SwitchCases[i].FalseBB = 0;
1055 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1056 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1057 SDB->SwitchCases[i].FalseBB = 0;
1059 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1062 SDB->SwitchCases.clear();
1064 SDB->PHINodesToUpdate.clear();
1068 /// Create the scheduler. If a specific scheduler was specified
1069 /// via the SchedulerRegistry, use it, otherwise select the
1070 /// one preferred by the target.
1072 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1073 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1077 RegisterScheduler::setDefault(Ctor);
1080 return Ctor(this, OptLevel);
1083 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1084 return new ScheduleHazardRecognizer();
1087 //===----------------------------------------------------------------------===//
1088 // Helper functions used by the generated instruction selector.
1089 //===----------------------------------------------------------------------===//
1090 // Calls to these methods are generated by tblgen.
1092 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1093 /// the dag combiner simplified the 255, we still want to match. RHS is the
1094 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1095 /// specified in the .td file (e.g. 255).
1096 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1097 int64_t DesiredMaskS) const {
1098 const APInt &ActualMask = RHS->getAPIntValue();
1099 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1101 // If the actual mask exactly matches, success!
1102 if (ActualMask == DesiredMask)
1105 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1106 if (ActualMask.intersects(~DesiredMask))
1109 // Otherwise, the DAG Combiner may have proven that the value coming in is
1110 // either already zero or is not demanded. Check for known zero input bits.
1111 APInt NeededMask = DesiredMask & ~ActualMask;
1112 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1115 // TODO: check to see if missing bits are just not demanded.
1117 // Otherwise, this pattern doesn't match.
1121 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1122 /// the dag combiner simplified the 255, we still want to match. RHS is the
1123 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1124 /// specified in the .td file (e.g. 255).
1125 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1126 int64_t DesiredMaskS) const {
1127 const APInt &ActualMask = RHS->getAPIntValue();
1128 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1130 // If the actual mask exactly matches, success!
1131 if (ActualMask == DesiredMask)
1134 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1135 if (ActualMask.intersects(~DesiredMask))
1138 // Otherwise, the DAG Combiner may have proven that the value coming in is
1139 // either already zero or is not demanded. Check for known zero input bits.
1140 APInt NeededMask = DesiredMask & ~ActualMask;
1142 APInt KnownZero, KnownOne;
1143 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1145 // If all the missing bits in the or are already known to be set, match!
1146 if ((NeededMask & KnownOne) == NeededMask)
1149 // TODO: check to see if missing bits are just not demanded.
1151 // Otherwise, this pattern doesn't match.
1156 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1157 /// by tblgen. Others should not call it.
1158 void SelectionDAGISel::
1159 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1160 std::vector<SDValue> InOps;
1161 std::swap(InOps, Ops);
1163 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1164 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1165 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1167 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1168 if (InOps[e-1].getValueType() == MVT::Flag)
1169 --e; // Don't process a flag operand if it is here.
1172 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1173 if (!InlineAsm::isMemKind(Flags)) {
1174 // Just skip over this operand, copying the operands verbatim.
1175 Ops.insert(Ops.end(), InOps.begin()+i,
1176 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1177 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1179 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1180 "Memory operand with multiple values?");
1181 // Otherwise, this is a memory operand. Ask the target to select it.
1182 std::vector<SDValue> SelOps;
1183 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1184 report_fatal_error("Could not match memory address. Inline asm"
1187 // Add this to the output node.
1189 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1190 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1191 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1196 // Add the flag input back if present.
1197 if (e != InOps.size())
1198 Ops.push_back(InOps.back());
1201 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1204 static SDNode *findFlagUse(SDNode *N) {
1205 unsigned FlagResNo = N->getNumValues()-1;
1206 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1207 SDUse &Use = I.getUse();
1208 if (Use.getResNo() == FlagResNo)
1209 return Use.getUser();
1214 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1215 /// This function recursively traverses up the operand chain, ignoring
1217 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1218 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1219 bool IgnoreChains) {
1220 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1221 // greater than all of its (recursive) operands. If we scan to a point where
1222 // 'use' is smaller than the node we're scanning for, then we know we will
1225 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1226 // happen because we scan down to newly selected nodes in the case of flag
1228 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1231 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1232 // won't fail if we scan it again.
1233 if (!Visited.insert(Use))
1236 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1237 // Ignore chain uses, they are validated by HandleMergeInputChains.
1238 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1241 SDNode *N = Use->getOperand(i).getNode();
1243 if (Use == ImmedUse || Use == Root)
1244 continue; // We are not looking for immediate use.
1249 // Traverse up the operand chain.
1250 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1256 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1257 /// operand node N of U during instruction selection that starts at Root.
1258 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1259 SDNode *Root) const {
1260 if (OptLevel == CodeGenOpt::None) return false;
1261 return N.hasOneUse();
1264 /// IsLegalToFold - Returns true if the specific operand node N of
1265 /// U can be folded during instruction selection that starts at Root.
1266 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1267 CodeGenOpt::Level OptLevel,
1268 bool IgnoreChains) {
1269 if (OptLevel == CodeGenOpt::None) return false;
1271 // If Root use can somehow reach N through a path that that doesn't contain
1272 // U then folding N would create a cycle. e.g. In the following
1273 // diagram, Root can reach N through X. If N is folded into into Root, then
1274 // X is both a predecessor and a successor of U.
1285 // * indicates nodes to be folded together.
1287 // If Root produces a flag, then it gets (even more) interesting. Since it
1288 // will be "glued" together with its flag use in the scheduler, we need to
1289 // check if it might reach N.
1308 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1309 // (call it Fold), then X is a predecessor of FU and a successor of
1310 // Fold. But since Fold and FU are flagged together, this will create
1311 // a cycle in the scheduling graph.
1313 // If the node has flags, walk down the graph to the "lowest" node in the
1315 EVT VT = Root->getValueType(Root->getNumValues()-1);
1316 while (VT == MVT::Flag) {
1317 SDNode *FU = findFlagUse(Root);
1321 VT = Root->getValueType(Root->getNumValues()-1);
1323 // If our query node has a flag result with a use, we've walked up it. If
1324 // the user (which has already been selected) has a chain or indirectly uses
1325 // the chain, our WalkChainUsers predicate will not consider it. Because of
1326 // this, we cannot ignore chains in this predicate.
1327 IgnoreChains = false;
1331 SmallPtrSet<SDNode*, 16> Visited;
1332 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1335 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1336 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1337 SelectInlineAsmMemoryOperands(Ops);
1339 std::vector<EVT> VTs;
1340 VTs.push_back(MVT::Other);
1341 VTs.push_back(MVT::Flag);
1342 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1343 VTs, &Ops[0], Ops.size());
1345 return New.getNode();
1348 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1349 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1352 /// GetVBR - decode a vbr encoding whose top bit is set.
1353 ALWAYS_INLINE static uint64_t
1354 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1355 assert(Val >= 128 && "Not a VBR");
1356 Val &= 127; // Remove first vbr bit.
1361 NextBits = MatcherTable[Idx++];
1362 Val |= (NextBits&127) << Shift;
1364 } while (NextBits & 128);
1370 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1371 /// interior flag and chain results to use the new flag and chain results.
1372 void SelectionDAGISel::
1373 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1374 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1376 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1377 bool isMorphNodeTo) {
1378 SmallVector<SDNode*, 4> NowDeadNodes;
1380 ISelUpdater ISU(ISelPosition);
1382 // Now that all the normal results are replaced, we replace the chain and
1383 // flag results if present.
1384 if (!ChainNodesMatched.empty()) {
1385 assert(InputChain.getNode() != 0 &&
1386 "Matched input chains but didn't produce a chain");
1387 // Loop over all of the nodes we matched that produced a chain result.
1388 // Replace all the chain results with the final chain we ended up with.
1389 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1390 SDNode *ChainNode = ChainNodesMatched[i];
1392 // If this node was already deleted, don't look at it.
1393 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1396 // Don't replace the results of the root node if we're doing a
1398 if (ChainNode == NodeToMatch && isMorphNodeTo)
1401 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1402 if (ChainVal.getValueType() == MVT::Flag)
1403 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1404 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1405 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1407 // If the node became dead and we haven't already seen it, delete it.
1408 if (ChainNode->use_empty() &&
1409 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1410 NowDeadNodes.push_back(ChainNode);
1414 // If the result produces a flag, update any flag results in the matched
1415 // pattern with the flag result.
1416 if (InputFlag.getNode() != 0) {
1417 // Handle any interior nodes explicitly marked.
1418 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1419 SDNode *FRN = FlagResultNodesMatched[i];
1421 // If this node was already deleted, don't look at it.
1422 if (FRN->getOpcode() == ISD::DELETED_NODE)
1425 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1426 "Doesn't have a flag result");
1427 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1430 // If the node became dead and we haven't already seen it, delete it.
1431 if (FRN->use_empty() &&
1432 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1433 NowDeadNodes.push_back(FRN);
1437 if (!NowDeadNodes.empty())
1438 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1440 DEBUG(errs() << "ISEL: Match complete!\n");
1446 CR_LeadsToInteriorNode
1449 /// WalkChainUsers - Walk down the users of the specified chained node that is
1450 /// part of the pattern we're matching, looking at all of the users we find.
1451 /// This determines whether something is an interior node, whether we have a
1452 /// non-pattern node in between two pattern nodes (which prevent folding because
1453 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1454 /// between pattern nodes (in which case the TF becomes part of the pattern).
1456 /// The walk we do here is guaranteed to be small because we quickly get down to
1457 /// already selected nodes "below" us.
1459 WalkChainUsers(SDNode *ChainedNode,
1460 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1461 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1462 ChainResult Result = CR_Simple;
1464 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1465 E = ChainedNode->use_end(); UI != E; ++UI) {
1466 // Make sure the use is of the chain, not some other value we produce.
1467 if (UI.getUse().getValueType() != MVT::Other) continue;
1471 // If we see an already-selected machine node, then we've gone beyond the
1472 // pattern that we're selecting down into the already selected chunk of the
1474 if (User->isMachineOpcode() ||
1475 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1478 if (User->getOpcode() == ISD::CopyToReg ||
1479 User->getOpcode() == ISD::CopyFromReg ||
1480 User->getOpcode() == ISD::INLINEASM ||
1481 User->getOpcode() == ISD::EH_LABEL) {
1482 // If their node ID got reset to -1 then they've already been selected.
1483 // Treat them like a MachineOpcode.
1484 if (User->getNodeId() == -1)
1488 // If we have a TokenFactor, we handle it specially.
1489 if (User->getOpcode() != ISD::TokenFactor) {
1490 // If the node isn't a token factor and isn't part of our pattern, then it
1491 // must be a random chained node in between two nodes we're selecting.
1492 // This happens when we have something like:
1497 // Because we structurally match the load/store as a read/modify/write,
1498 // but the call is chained between them. We cannot fold in this case
1499 // because it would induce a cycle in the graph.
1500 if (!std::count(ChainedNodesInPattern.begin(),
1501 ChainedNodesInPattern.end(), User))
1502 return CR_InducesCycle;
1504 // Otherwise we found a node that is part of our pattern. For example in:
1508 // This would happen when we're scanning down from the load and see the
1509 // store as a user. Record that there is a use of ChainedNode that is
1510 // part of the pattern and keep scanning uses.
1511 Result = CR_LeadsToInteriorNode;
1512 InteriorChainedNodes.push_back(User);
1516 // If we found a TokenFactor, there are two cases to consider: first if the
1517 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1518 // uses of the TF are in our pattern) we just want to ignore it. Second,
1519 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1525 // | \ DAG's like cheese
1528 // [TokenFactor] [Op]
1535 // In this case, the TokenFactor becomes part of our match and we rewrite it
1536 // as a new TokenFactor.
1538 // To distinguish these two cases, do a recursive walk down the uses.
1539 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1541 // If the uses of the TokenFactor are just already-selected nodes, ignore
1542 // it, it is "below" our pattern.
1544 case CR_InducesCycle:
1545 // If the uses of the TokenFactor lead to nodes that are not part of our
1546 // pattern that are not selected, folding would turn this into a cycle,
1548 return CR_InducesCycle;
1549 case CR_LeadsToInteriorNode:
1550 break; // Otherwise, keep processing.
1553 // Okay, we know we're in the interesting interior case. The TokenFactor
1554 // is now going to be considered part of the pattern so that we rewrite its
1555 // uses (it may have uses that are not part of the pattern) with the
1556 // ultimate chain result of the generated code. We will also add its chain
1557 // inputs as inputs to the ultimate TokenFactor we create.
1558 Result = CR_LeadsToInteriorNode;
1559 ChainedNodesInPattern.push_back(User);
1560 InteriorChainedNodes.push_back(User);
1567 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1568 /// operation for when the pattern matched at least one node with a chains. The
1569 /// input vector contains a list of all of the chained nodes that we match. We
1570 /// must determine if this is a valid thing to cover (i.e. matching it won't
1571 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1572 /// be used as the input node chain for the generated nodes.
1574 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1575 SelectionDAG *CurDAG) {
1576 // Walk all of the chained nodes we've matched, recursively scanning down the
1577 // users of the chain result. This adds any TokenFactor nodes that are caught
1578 // in between chained nodes to the chained and interior nodes list.
1579 SmallVector<SDNode*, 3> InteriorChainedNodes;
1580 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1581 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1582 InteriorChainedNodes) == CR_InducesCycle)
1583 return SDValue(); // Would induce a cycle.
1586 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1587 // that we are interested in. Form our input TokenFactor node.
1588 SmallVector<SDValue, 3> InputChains;
1589 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1590 // Add the input chain of this node to the InputChains list (which will be
1591 // the operands of the generated TokenFactor) if it's not an interior node.
1592 SDNode *N = ChainNodesMatched[i];
1593 if (N->getOpcode() != ISD::TokenFactor) {
1594 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1597 // Otherwise, add the input chain.
1598 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1599 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1600 InputChains.push_back(InChain);
1604 // If we have a token factor, we want to add all inputs of the token factor
1605 // that are not part of the pattern we're matching.
1606 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1607 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1608 N->getOperand(op).getNode()))
1609 InputChains.push_back(N->getOperand(op));
1614 if (InputChains.size() == 1)
1615 return InputChains[0];
1616 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1617 MVT::Other, &InputChains[0], InputChains.size());
1620 /// MorphNode - Handle morphing a node in place for the selector.
1621 SDNode *SelectionDAGISel::
1622 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1623 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1624 // It is possible we're using MorphNodeTo to replace a node with no
1625 // normal results with one that has a normal result (or we could be
1626 // adding a chain) and the input could have flags and chains as well.
1627 // In this case we need to shift the operands down.
1628 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1629 // than the old isel though.
1630 int OldFlagResultNo = -1, OldChainResultNo = -1;
1632 unsigned NTMNumResults = Node->getNumValues();
1633 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1634 OldFlagResultNo = NTMNumResults-1;
1635 if (NTMNumResults != 1 &&
1636 Node->getValueType(NTMNumResults-2) == MVT::Other)
1637 OldChainResultNo = NTMNumResults-2;
1638 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1639 OldChainResultNo = NTMNumResults-1;
1641 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1642 // that this deletes operands of the old node that become dead.
1643 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1645 // MorphNodeTo can operate in two ways: if an existing node with the
1646 // specified operands exists, it can just return it. Otherwise, it
1647 // updates the node in place to have the requested operands.
1649 // If we updated the node in place, reset the node ID. To the isel,
1650 // this should be just like a newly allocated machine node.
1654 unsigned ResNumResults = Res->getNumValues();
1655 // Move the flag if needed.
1656 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1657 (unsigned)OldFlagResultNo != ResNumResults-1)
1658 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1659 SDValue(Res, ResNumResults-1));
1661 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1664 // Move the chain reference if needed.
1665 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1666 (unsigned)OldChainResultNo != ResNumResults-1)
1667 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1668 SDValue(Res, ResNumResults-1));
1670 // Otherwise, no replacement happened because the node already exists. Replace
1671 // Uses of the old node with the new one.
1673 CurDAG->ReplaceAllUsesWith(Node, Res);
1678 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1679 ALWAYS_INLINE static bool
1680 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1681 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1682 // Accept if it is exactly the same as a previously recorded node.
1683 unsigned RecNo = MatcherTable[MatcherIndex++];
1684 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1685 return N == RecordedNodes[RecNo];
1688 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1689 ALWAYS_INLINE static bool
1690 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1691 SelectionDAGISel &SDISel) {
1692 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1695 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1696 ALWAYS_INLINE static bool
1697 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1698 SelectionDAGISel &SDISel, SDNode *N) {
1699 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1702 ALWAYS_INLINE static bool
1703 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1705 uint16_t Opc = MatcherTable[MatcherIndex++];
1706 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1707 return N->getOpcode() == Opc;
1710 ALWAYS_INLINE static bool
1711 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1712 SDValue N, const TargetLowering &TLI) {
1713 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1714 if (N.getValueType() == VT) return true;
1716 // Handle the case when VT is iPTR.
1717 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1720 ALWAYS_INLINE static bool
1721 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1722 SDValue N, const TargetLowering &TLI,
1724 if (ChildNo >= N.getNumOperands())
1725 return false; // Match fails if out of range child #.
1726 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1730 ALWAYS_INLINE static bool
1731 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1733 return cast<CondCodeSDNode>(N)->get() ==
1734 (ISD::CondCode)MatcherTable[MatcherIndex++];
1737 ALWAYS_INLINE static bool
1738 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1739 SDValue N, const TargetLowering &TLI) {
1740 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1741 if (cast<VTSDNode>(N)->getVT() == VT)
1744 // Handle the case when VT is iPTR.
1745 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1748 ALWAYS_INLINE static bool
1749 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1751 int64_t Val = MatcherTable[MatcherIndex++];
1753 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1755 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1756 return C != 0 && C->getSExtValue() == Val;
1759 ALWAYS_INLINE static bool
1760 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1761 SDValue N, SelectionDAGISel &SDISel) {
1762 int64_t Val = MatcherTable[MatcherIndex++];
1764 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1766 if (N->getOpcode() != ISD::AND) return false;
1768 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1769 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1772 ALWAYS_INLINE static bool
1773 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1774 SDValue N, SelectionDAGISel &SDISel) {
1775 int64_t Val = MatcherTable[MatcherIndex++];
1777 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1779 if (N->getOpcode() != ISD::OR) return false;
1781 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1782 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1785 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1786 /// scope, evaluate the current node. If the current predicate is known to
1787 /// fail, set Result=true and return anything. If the current predicate is
1788 /// known to pass, set Result=false and return the MatcherIndex to continue
1789 /// with. If the current predicate is unknown, set Result=false and return the
1790 /// MatcherIndex to continue with.
1791 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1792 unsigned Index, SDValue N,
1793 bool &Result, SelectionDAGISel &SDISel,
1794 SmallVectorImpl<SDValue> &RecordedNodes){
1795 switch (Table[Index++]) {
1798 return Index-1; // Could not evaluate this predicate.
1799 case SelectionDAGISel::OPC_CheckSame:
1800 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1802 case SelectionDAGISel::OPC_CheckPatternPredicate:
1803 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1805 case SelectionDAGISel::OPC_CheckPredicate:
1806 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1808 case SelectionDAGISel::OPC_CheckOpcode:
1809 Result = !::CheckOpcode(Table, Index, N.getNode());
1811 case SelectionDAGISel::OPC_CheckType:
1812 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1814 case SelectionDAGISel::OPC_CheckChild0Type:
1815 case SelectionDAGISel::OPC_CheckChild1Type:
1816 case SelectionDAGISel::OPC_CheckChild2Type:
1817 case SelectionDAGISel::OPC_CheckChild3Type:
1818 case SelectionDAGISel::OPC_CheckChild4Type:
1819 case SelectionDAGISel::OPC_CheckChild5Type:
1820 case SelectionDAGISel::OPC_CheckChild6Type:
1821 case SelectionDAGISel::OPC_CheckChild7Type:
1822 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1823 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1825 case SelectionDAGISel::OPC_CheckCondCode:
1826 Result = !::CheckCondCode(Table, Index, N);
1828 case SelectionDAGISel::OPC_CheckValueType:
1829 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1831 case SelectionDAGISel::OPC_CheckInteger:
1832 Result = !::CheckInteger(Table, Index, N);
1834 case SelectionDAGISel::OPC_CheckAndImm:
1835 Result = !::CheckAndImm(Table, Index, N, SDISel);
1837 case SelectionDAGISel::OPC_CheckOrImm:
1838 Result = !::CheckOrImm(Table, Index, N, SDISel);
1846 /// FailIndex - If this match fails, this is the index to continue with.
1849 /// NodeStack - The node stack when the scope was formed.
1850 SmallVector<SDValue, 4> NodeStack;
1852 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1853 unsigned NumRecordedNodes;
1855 /// NumMatchedMemRefs - The number of matched memref entries.
1856 unsigned NumMatchedMemRefs;
1858 /// InputChain/InputFlag - The current chain/flag
1859 SDValue InputChain, InputFlag;
1861 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1862 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1867 SDNode *SelectionDAGISel::
1868 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1869 unsigned TableSize) {
1870 // FIXME: Should these even be selected? Handle these cases in the caller?
1871 switch (NodeToMatch->getOpcode()) {
1874 case ISD::EntryToken: // These nodes remain the same.
1875 case ISD::BasicBlock:
1877 //case ISD::VALUETYPE:
1878 //case ISD::CONDCODE:
1879 case ISD::HANDLENODE:
1880 case ISD::MDNODE_SDNODE:
1881 case ISD::TargetConstant:
1882 case ISD::TargetConstantFP:
1883 case ISD::TargetConstantPool:
1884 case ISD::TargetFrameIndex:
1885 case ISD::TargetExternalSymbol:
1886 case ISD::TargetBlockAddress:
1887 case ISD::TargetJumpTable:
1888 case ISD::TargetGlobalTLSAddress:
1889 case ISD::TargetGlobalAddress:
1890 case ISD::TokenFactor:
1891 case ISD::CopyFromReg:
1892 case ISD::CopyToReg:
1894 NodeToMatch->setNodeId(-1); // Mark selected.
1896 case ISD::AssertSext:
1897 case ISD::AssertZext:
1898 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1899 NodeToMatch->getOperand(0));
1901 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1902 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1905 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1907 // Set up the node stack with NodeToMatch as the only node on the stack.
1908 SmallVector<SDValue, 8> NodeStack;
1909 SDValue N = SDValue(NodeToMatch, 0);
1910 NodeStack.push_back(N);
1912 // MatchScopes - Scopes used when matching, if a match failure happens, this
1913 // indicates where to continue checking.
1914 SmallVector<MatchScope, 8> MatchScopes;
1916 // RecordedNodes - This is the set of nodes that have been recorded by the
1918 SmallVector<SDValue, 8> RecordedNodes;
1920 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1922 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1924 // These are the current input chain and flag for use when generating nodes.
1925 // Various Emit operations change these. For example, emitting a copytoreg
1926 // uses and updates these.
1927 SDValue InputChain, InputFlag;
1929 // ChainNodesMatched - If a pattern matches nodes that have input/output
1930 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1931 // which ones they are. The result is captured into this list so that we can
1932 // update the chain results when the pattern is complete.
1933 SmallVector<SDNode*, 3> ChainNodesMatched;
1934 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1936 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1937 NodeToMatch->dump(CurDAG);
1940 // Determine where to start the interpreter. Normally we start at opcode #0,
1941 // but if the state machine starts with an OPC_SwitchOpcode, then we
1942 // accelerate the first lookup (which is guaranteed to be hot) with the
1943 // OpcodeOffset table.
1944 unsigned MatcherIndex = 0;
1946 if (!OpcodeOffset.empty()) {
1947 // Already computed the OpcodeOffset table, just index into it.
1948 if (N.getOpcode() < OpcodeOffset.size())
1949 MatcherIndex = OpcodeOffset[N.getOpcode()];
1950 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1952 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1953 // Otherwise, the table isn't computed, but the state machine does start
1954 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1955 // is the first time we're selecting an instruction.
1958 // Get the size of this case.
1959 unsigned CaseSize = MatcherTable[Idx++];
1961 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1962 if (CaseSize == 0) break;
1964 // Get the opcode, add the index to the table.
1965 uint16_t Opc = MatcherTable[Idx++];
1966 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1967 if (Opc >= OpcodeOffset.size())
1968 OpcodeOffset.resize((Opc+1)*2);
1969 OpcodeOffset[Opc] = Idx;
1973 // Okay, do the lookup for the first opcode.
1974 if (N.getOpcode() < OpcodeOffset.size())
1975 MatcherIndex = OpcodeOffset[N.getOpcode()];
1979 assert(MatcherIndex < TableSize && "Invalid index");
1981 unsigned CurrentOpcodeIndex = MatcherIndex;
1983 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1986 // Okay, the semantics of this operation are that we should push a scope
1987 // then evaluate the first child. However, pushing a scope only to have
1988 // the first check fail (which then pops it) is inefficient. If we can
1989 // determine immediately that the first check (or first several) will
1990 // immediately fail, don't even bother pushing a scope for them.
1994 unsigned NumToSkip = MatcherTable[MatcherIndex++];
1995 if (NumToSkip & 128)
1996 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
1997 // Found the end of the scope with no match.
1998 if (NumToSkip == 0) {
2003 FailIndex = MatcherIndex+NumToSkip;
2005 unsigned MatcherIndexOfPredicate = MatcherIndex;
2006 (void)MatcherIndexOfPredicate; // silence warning.
2008 // If we can't evaluate this predicate without pushing a scope (e.g. if
2009 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2010 // push the scope and evaluate the full predicate chain.
2012 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2013 Result, *this, RecordedNodes);
2017 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2018 << "index " << MatcherIndexOfPredicate
2019 << ", continuing at " << FailIndex << "\n");
2020 ++NumDAGIselRetries;
2022 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2023 // move to the next case.
2024 MatcherIndex = FailIndex;
2027 // If the whole scope failed to match, bail.
2028 if (FailIndex == 0) break;
2030 // Push a MatchScope which indicates where to go if the first child fails
2032 MatchScope NewEntry;
2033 NewEntry.FailIndex = FailIndex;
2034 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2035 NewEntry.NumRecordedNodes = RecordedNodes.size();
2036 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2037 NewEntry.InputChain = InputChain;
2038 NewEntry.InputFlag = InputFlag;
2039 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2040 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2041 MatchScopes.push_back(NewEntry);
2044 case OPC_RecordNode:
2045 // Remember this node, it may end up being an operand in the pattern.
2046 RecordedNodes.push_back(N);
2049 case OPC_RecordChild0: case OPC_RecordChild1:
2050 case OPC_RecordChild2: case OPC_RecordChild3:
2051 case OPC_RecordChild4: case OPC_RecordChild5:
2052 case OPC_RecordChild6: case OPC_RecordChild7: {
2053 unsigned ChildNo = Opcode-OPC_RecordChild0;
2054 if (ChildNo >= N.getNumOperands())
2055 break; // Match fails if out of range child #.
2057 RecordedNodes.push_back(N->getOperand(ChildNo));
2060 case OPC_RecordMemRef:
2061 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2064 case OPC_CaptureFlagInput:
2065 // If the current node has an input flag, capture it in InputFlag.
2066 if (N->getNumOperands() != 0 &&
2067 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2068 InputFlag = N->getOperand(N->getNumOperands()-1);
2071 case OPC_MoveChild: {
2072 unsigned ChildNo = MatcherTable[MatcherIndex++];
2073 if (ChildNo >= N.getNumOperands())
2074 break; // Match fails if out of range child #.
2075 N = N.getOperand(ChildNo);
2076 NodeStack.push_back(N);
2080 case OPC_MoveParent:
2081 // Pop the current node off the NodeStack.
2082 NodeStack.pop_back();
2083 assert(!NodeStack.empty() && "Node stack imbalance!");
2084 N = NodeStack.back();
2088 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2090 case OPC_CheckPatternPredicate:
2091 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2093 case OPC_CheckPredicate:
2094 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2098 case OPC_CheckComplexPat: {
2099 unsigned CPNum = MatcherTable[MatcherIndex++];
2100 unsigned RecNo = MatcherTable[MatcherIndex++];
2101 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2102 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2107 case OPC_CheckOpcode:
2108 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2112 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2115 case OPC_SwitchOpcode: {
2116 unsigned CurNodeOpcode = N.getOpcode();
2117 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2120 // Get the size of this case.
2121 CaseSize = MatcherTable[MatcherIndex++];
2123 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2124 if (CaseSize == 0) break;
2126 uint16_t Opc = MatcherTable[MatcherIndex++];
2127 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2129 // If the opcode matches, then we will execute this case.
2130 if (CurNodeOpcode == Opc)
2133 // Otherwise, skip over this case.
2134 MatcherIndex += CaseSize;
2137 // If no cases matched, bail out.
2138 if (CaseSize == 0) break;
2140 // Otherwise, execute the case we found.
2141 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2142 << " to " << MatcherIndex << "\n");
2146 case OPC_SwitchType: {
2147 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2148 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2151 // Get the size of this case.
2152 CaseSize = MatcherTable[MatcherIndex++];
2154 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2155 if (CaseSize == 0) break;
2157 MVT::SimpleValueType CaseVT =
2158 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2159 if (CaseVT == MVT::iPTR)
2160 CaseVT = TLI.getPointerTy().SimpleTy;
2162 // If the VT matches, then we will execute this case.
2163 if (CurNodeVT == CaseVT)
2166 // Otherwise, skip over this case.
2167 MatcherIndex += CaseSize;
2170 // If no cases matched, bail out.
2171 if (CaseSize == 0) break;
2173 // Otherwise, execute the case we found.
2174 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2175 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2178 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2179 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2180 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2181 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2182 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2183 Opcode-OPC_CheckChild0Type))
2186 case OPC_CheckCondCode:
2187 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2189 case OPC_CheckValueType:
2190 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2192 case OPC_CheckInteger:
2193 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2195 case OPC_CheckAndImm:
2196 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2198 case OPC_CheckOrImm:
2199 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2202 case OPC_CheckFoldableChainNode: {
2203 assert(NodeStack.size() != 1 && "No parent node");
2204 // Verify that all intermediate nodes between the root and this one have
2206 bool HasMultipleUses = false;
2207 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2208 if (!NodeStack[i].hasOneUse()) {
2209 HasMultipleUses = true;
2212 if (HasMultipleUses) break;
2214 // Check to see that the target thinks this is profitable to fold and that
2215 // we can fold it without inducing cycles in the graph.
2216 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2218 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2219 NodeToMatch, OptLevel,
2220 true/*We validate our own chains*/))
2225 case OPC_EmitInteger: {
2226 MVT::SimpleValueType VT =
2227 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2228 int64_t Val = MatcherTable[MatcherIndex++];
2230 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2231 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2234 case OPC_EmitRegister: {
2235 MVT::SimpleValueType VT =
2236 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2237 unsigned RegNo = MatcherTable[MatcherIndex++];
2238 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2242 case OPC_EmitConvertToTarget: {
2243 // Convert from IMM/FPIMM to target version.
2244 unsigned RecNo = MatcherTable[MatcherIndex++];
2245 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2246 SDValue Imm = RecordedNodes[RecNo];
2248 if (Imm->getOpcode() == ISD::Constant) {
2249 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2250 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2251 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2252 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2253 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2256 RecordedNodes.push_back(Imm);
2260 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2261 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2262 // These are space-optimized forms of OPC_EmitMergeInputChains.
2263 assert(InputChain.getNode() == 0 &&
2264 "EmitMergeInputChains should be the first chain producing node");
2265 assert(ChainNodesMatched.empty() &&
2266 "Should only have one EmitMergeInputChains per match");
2268 // Read all of the chained nodes.
2269 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2270 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2271 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2273 // FIXME: What if other value results of the node have uses not matched
2275 if (ChainNodesMatched.back() != NodeToMatch &&
2276 !RecordedNodes[RecNo].hasOneUse()) {
2277 ChainNodesMatched.clear();
2281 // Merge the input chains if they are not intra-pattern references.
2282 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2284 if (InputChain.getNode() == 0)
2285 break; // Failed to merge.
2289 case OPC_EmitMergeInputChains: {
2290 assert(InputChain.getNode() == 0 &&
2291 "EmitMergeInputChains should be the first chain producing node");
2292 // This node gets a list of nodes we matched in the input that have
2293 // chains. We want to token factor all of the input chains to these nodes
2294 // together. However, if any of the input chains is actually one of the
2295 // nodes matched in this pattern, then we have an intra-match reference.
2296 // Ignore these because the newly token factored chain should not refer to
2298 unsigned NumChains = MatcherTable[MatcherIndex++];
2299 assert(NumChains != 0 && "Can't TF zero chains");
2301 assert(ChainNodesMatched.empty() &&
2302 "Should only have one EmitMergeInputChains per match");
2304 // Read all of the chained nodes.
2305 for (unsigned i = 0; i != NumChains; ++i) {
2306 unsigned RecNo = MatcherTable[MatcherIndex++];
2307 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2308 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2310 // FIXME: What if other value results of the node have uses not matched
2312 if (ChainNodesMatched.back() != NodeToMatch &&
2313 !RecordedNodes[RecNo].hasOneUse()) {
2314 ChainNodesMatched.clear();
2319 // If the inner loop broke out, the match fails.
2320 if (ChainNodesMatched.empty())
2323 // Merge the input chains if they are not intra-pattern references.
2324 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2326 if (InputChain.getNode() == 0)
2327 break; // Failed to merge.
2332 case OPC_EmitCopyToReg: {
2333 unsigned RecNo = MatcherTable[MatcherIndex++];
2334 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2335 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2337 if (InputChain.getNode() == 0)
2338 InputChain = CurDAG->getEntryNode();
2340 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2341 DestPhysReg, RecordedNodes[RecNo],
2344 InputFlag = InputChain.getValue(1);
2348 case OPC_EmitNodeXForm: {
2349 unsigned XFormNo = MatcherTable[MatcherIndex++];
2350 unsigned RecNo = MatcherTable[MatcherIndex++];
2351 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2352 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2357 case OPC_MorphNodeTo: {
2358 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2359 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2360 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2361 // Get the result VT list.
2362 unsigned NumVTs = MatcherTable[MatcherIndex++];
2363 SmallVector<EVT, 4> VTs;
2364 for (unsigned i = 0; i != NumVTs; ++i) {
2365 MVT::SimpleValueType VT =
2366 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2367 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2371 if (EmitNodeInfo & OPFL_Chain)
2372 VTs.push_back(MVT::Other);
2373 if (EmitNodeInfo & OPFL_FlagOutput)
2374 VTs.push_back(MVT::Flag);
2376 // This is hot code, so optimize the two most common cases of 1 and 2
2379 if (VTs.size() == 1)
2380 VTList = CurDAG->getVTList(VTs[0]);
2381 else if (VTs.size() == 2)
2382 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2384 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2386 // Get the operand list.
2387 unsigned NumOps = MatcherTable[MatcherIndex++];
2388 SmallVector<SDValue, 8> Ops;
2389 for (unsigned i = 0; i != NumOps; ++i) {
2390 unsigned RecNo = MatcherTable[MatcherIndex++];
2392 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2394 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2395 Ops.push_back(RecordedNodes[RecNo]);
2398 // If there are variadic operands to add, handle them now.
2399 if (EmitNodeInfo & OPFL_VariadicInfo) {
2400 // Determine the start index to copy from.
2401 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2402 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2403 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2404 "Invalid variadic node");
2405 // Copy all of the variadic operands, not including a potential flag
2407 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2409 SDValue V = NodeToMatch->getOperand(i);
2410 if (V.getValueType() == MVT::Flag) break;
2415 // If this has chain/flag inputs, add them.
2416 if (EmitNodeInfo & OPFL_Chain)
2417 Ops.push_back(InputChain);
2418 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2419 Ops.push_back(InputFlag);
2423 if (Opcode != OPC_MorphNodeTo) {
2424 // If this is a normal EmitNode command, just create the new node and
2425 // add the results to the RecordedNodes list.
2426 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2427 VTList, Ops.data(), Ops.size());
2429 // Add all the non-flag/non-chain results to the RecordedNodes list.
2430 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2431 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2432 RecordedNodes.push_back(SDValue(Res, i));
2436 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2440 // If the node had chain/flag results, update our notion of the current
2442 if (EmitNodeInfo & OPFL_FlagOutput) {
2443 InputFlag = SDValue(Res, VTs.size()-1);
2444 if (EmitNodeInfo & OPFL_Chain)
2445 InputChain = SDValue(Res, VTs.size()-2);
2446 } else if (EmitNodeInfo & OPFL_Chain)
2447 InputChain = SDValue(Res, VTs.size()-1);
2449 // If the OPFL_MemRefs flag is set on this node, slap all of the
2450 // accumulated memrefs onto it.
2452 // FIXME: This is vastly incorrect for patterns with multiple outputs
2453 // instructions that access memory and for ComplexPatterns that match
2455 if (EmitNodeInfo & OPFL_MemRefs) {
2456 MachineSDNode::mmo_iterator MemRefs =
2457 MF->allocateMemRefsArray(MatchedMemRefs.size());
2458 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2459 cast<MachineSDNode>(Res)
2460 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2464 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2465 << " node: "; Res->dump(CurDAG); errs() << "\n");
2467 // If this was a MorphNodeTo then we're completely done!
2468 if (Opcode == OPC_MorphNodeTo) {
2469 // Update chain and flag uses.
2470 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2471 InputFlag, FlagResultNodesMatched, true);
2478 case OPC_MarkFlagResults: {
2479 unsigned NumNodes = MatcherTable[MatcherIndex++];
2481 // Read and remember all the flag-result nodes.
2482 for (unsigned i = 0; i != NumNodes; ++i) {
2483 unsigned RecNo = MatcherTable[MatcherIndex++];
2485 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2487 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2488 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2493 case OPC_CompleteMatch: {
2494 // The match has been completed, and any new nodes (if any) have been
2495 // created. Patch up references to the matched dag to use the newly
2497 unsigned NumResults = MatcherTable[MatcherIndex++];
2499 for (unsigned i = 0; i != NumResults; ++i) {
2500 unsigned ResSlot = MatcherTable[MatcherIndex++];
2502 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2504 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2505 SDValue Res = RecordedNodes[ResSlot];
2507 assert(i < NodeToMatch->getNumValues() &&
2508 NodeToMatch->getValueType(i) != MVT::Other &&
2509 NodeToMatch->getValueType(i) != MVT::Flag &&
2510 "Invalid number of results to complete!");
2511 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2512 NodeToMatch->getValueType(i) == MVT::iPTR ||
2513 Res.getValueType() == MVT::iPTR ||
2514 NodeToMatch->getValueType(i).getSizeInBits() ==
2515 Res.getValueType().getSizeInBits()) &&
2516 "invalid replacement");
2517 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2520 // If the root node defines a flag, add it to the flag nodes to update
2522 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2523 FlagResultNodesMatched.push_back(NodeToMatch);
2525 // Update chain and flag uses.
2526 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2527 InputFlag, FlagResultNodesMatched, false);
2529 assert(NodeToMatch->use_empty() &&
2530 "Didn't replace all uses of the node?");
2532 // FIXME: We just return here, which interacts correctly with SelectRoot
2533 // above. We should fix this to not return an SDNode* anymore.
2538 // If the code reached this point, then the match failed. See if there is
2539 // another child to try in the current 'Scope', otherwise pop it until we
2540 // find a case to check.
2541 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2542 ++NumDAGIselRetries;
2544 if (MatchScopes.empty()) {
2545 CannotYetSelect(NodeToMatch);
2549 // Restore the interpreter state back to the point where the scope was
2551 MatchScope &LastScope = MatchScopes.back();
2552 RecordedNodes.resize(LastScope.NumRecordedNodes);
2554 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2555 N = NodeStack.back();
2557 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2558 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2559 MatcherIndex = LastScope.FailIndex;
2561 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2563 InputChain = LastScope.InputChain;
2564 InputFlag = LastScope.InputFlag;
2565 if (!LastScope.HasChainNodesMatched)
2566 ChainNodesMatched.clear();
2567 if (!LastScope.HasFlagResultNodesMatched)
2568 FlagResultNodesMatched.clear();
2570 // Check to see what the offset is at the new MatcherIndex. If it is zero
2571 // we have reached the end of this scope, otherwise we have another child
2572 // in the current scope to try.
2573 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2574 if (NumToSkip & 128)
2575 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2577 // If we have another child in this scope to match, update FailIndex and
2579 if (NumToSkip != 0) {
2580 LastScope.FailIndex = MatcherIndex+NumToSkip;
2584 // End of this scope, pop it and try the next child in the containing
2586 MatchScopes.pop_back();
2593 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2595 raw_string_ostream Msg(msg);
2596 Msg << "Cannot yet select: ";
2598 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2599 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2600 N->getOpcode() != ISD::INTRINSIC_VOID) {
2601 N->printrFull(Msg, CurDAG);
2603 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2605 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2606 if (iid < Intrinsic::num_intrinsics)
2607 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2608 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2609 Msg << "target intrinsic %" << TII->getName(iid);
2611 Msg << "unknown intrinsic #" << iid;
2613 report_fatal_error(Msg.str());
2616 char SelectionDAGISel::ID = 0;