1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetIntrinsicInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/ADT/Statistic.h"
53 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
54 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
57 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
58 cl::desc("Enable verbose messages in the \"fast\" "
59 "instruction selector"));
61 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
62 cl::desc("Enable abort calls when \"fast\" instruction fails"));
66 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
67 cl::desc("Pop up a window to show dags before the first "
70 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
71 cl::desc("Pop up a window to show dags before legalize types"));
73 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
74 cl::desc("Pop up a window to show dags before legalize"));
76 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
77 cl::desc("Pop up a window to show dags before the second "
80 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before the post legalize types"
82 " dag combine pass"));
84 ViewISelDAGs("view-isel-dags", cl::Hidden,
85 cl::desc("Pop up a window to show isel dags as they are selected"));
87 ViewSchedDAGs("view-sched-dags", cl::Hidden,
88 cl::desc("Pop up a window to show sched dags as they are processed"));
90 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
91 cl::desc("Pop up a window to show SUnit dags after they are processed"));
93 static const bool ViewDAGCombine1 = false,
94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
95 ViewDAGCombine2 = false,
96 ViewDAGCombineLT = false,
97 ViewISelDAGs = false, ViewSchedDAGs = false,
98 ViewSUnitDAGs = false;
101 //===---------------------------------------------------------------------===//
103 /// RegisterScheduler class - Track the registration of instruction schedulers.
105 //===---------------------------------------------------------------------===//
106 MachinePassRegistry RegisterScheduler::Registry;
108 //===---------------------------------------------------------------------===//
110 /// ISHeuristic command line option for instruction schedulers.
112 //===---------------------------------------------------------------------===//
113 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
114 RegisterPassParser<RegisterScheduler> >
115 ISHeuristic("pre-RA-sched",
116 cl::init(&createDefaultScheduler),
117 cl::desc("Instruction schedulers available (before register"
120 static RegisterScheduler
121 defaultListDAGScheduler("default", "Best scheduler for the target",
122 createDefaultScheduler);
125 //===--------------------------------------------------------------------===//
126 /// createDefaultScheduler - This creates an instruction scheduler appropriate
128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
129 CodeGenOpt::Level OptLevel) {
130 const TargetLowering &TLI = IS->getTargetLowering();
132 if (OptLevel == CodeGenOpt::None)
133 return createFastDAGScheduler(IS, OptLevel);
134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
135 return createTDListDAGScheduler(IS, OptLevel);
136 assert(TLI.getSchedulingPreference() ==
137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
138 return createBURRListDAGScheduler(IS, OptLevel);
142 // EmitInstrWithCustomInserter - This method should be implemented by targets
143 // that mark instructions with the 'usesCustomInserter' flag. These
144 // instructions are special in various ways, which require special support to
145 // insert. The specified MachineInstr is created but not inserted into any
146 // basic blocks, and this method is called to expand it into a sequence of
147 // instructions, potentially also creating new basic blocks and control flow.
148 // When new basic blocks are inserted and the edges from MBB to its successors
149 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
151 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
152 MachineBasicBlock *MBB,
153 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
155 dbgs() << "If a target marks an instruction with "
156 "'usesCustomInserter', it must implement "
157 "TargetLowering::EmitInstrWithCustomInserter!";
163 //===----------------------------------------------------------------------===//
164 // SelectionDAGISel code
165 //===----------------------------------------------------------------------===//
167 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
169 FuncInfo(new FunctionLoweringInfo(TLI)),
170 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
171 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
177 SelectionDAGISel::~SelectionDAGISel() {
183 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
184 AU.addRequired<AliasAnalysis>();
185 AU.addPreserved<AliasAnalysis>();
186 AU.addRequired<GCModuleInfo>();
187 AU.addPreserved<GCModuleInfo>();
188 MachineFunctionPass::getAnalysisUsage(AU);
191 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
192 // Do some sanity-checking on the command-line options.
193 assert((!EnableFastISelVerbose || EnableFastISel) &&
194 "-fast-isel-verbose requires -fast-isel");
195 assert((!EnableFastISelAbort || EnableFastISel) &&
196 "-fast-isel-abort requires -fast-isel");
198 Function &Fn = *mf.getFunction();
199 const TargetInstrInfo &TII = *TM.getInstrInfo();
200 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
203 RegInfo = &MF->getRegInfo();
204 AA = &getAnalysis<AliasAnalysis>();
205 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
207 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
210 FuncInfo->set(Fn, *MF, EnableFastISel);
213 SelectAllBasicBlocks(Fn, *MF, TII);
215 // Release function-specific state. SDB and CurDAG are already cleared
219 // If the first basic block in the function has live ins that need to be
220 // copied into vregs, emit the copies into the top of the block before
221 // emitting the code for the block.
222 RegInfo->EmitLiveInCopies(MF->begin(), TRI, TII);
227 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
228 /// attached with this instruction.
229 static void SetDebugLoc(Instruction *I, SelectionDAGBuilder *SDB,
230 FastISel *FastIS, MachineFunction *MF) {
231 DebugLoc DL = I->getDebugLoc();
232 if (DL.isUnknown()) return;
234 SDB->setCurDebugLoc(DL);
237 FastIS->setCurDebugLoc(DL);
239 // If the function doesn't have a default debug location yet, set
240 // it. This is kind of a hack.
241 if (MF->getDefaultDebugLoc().isUnknown())
242 MF->setDefaultDebugLoc(DL);
245 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
246 static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
247 SDB->setCurDebugLoc(DebugLoc());
249 FastIS->setCurDebugLoc(DebugLoc());
252 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
253 BasicBlock::iterator Begin,
254 BasicBlock::iterator End,
256 SDB->setCurrentBasicBlock(BB);
258 // Lower all of the non-terminator instructions. If a call is emitted
259 // as a tail call, cease emitting nodes for this block.
260 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
261 SetDebugLoc(I, SDB, 0, MF);
263 // Visit the instruction. Terminators are handled below.
264 if (!isa<TerminatorInst>(I))
267 ResetDebugLoc(SDB, 0);
270 if (!SDB->HasTailCall) {
271 // Ensure that all instructions which are used outside of their defining
272 // blocks are available as virtual registers. Invoke is handled elsewhere.
273 for (BasicBlock::iterator I = Begin; I != End; ++I)
274 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
275 SDB->CopyToExportRegsIfNeeded(I);
277 // Handle PHI nodes in successor blocks.
278 if (End == LLVMBB->end()) {
279 HandlePHINodesInSuccessorBlocks(LLVMBB);
281 // Lower the terminator after the copies are emitted.
282 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF);
283 SDB->visit(*LLVMBB->getTerminator());
284 ResetDebugLoc(SDB, 0);
288 // Make sure the root of the DAG is up-to-date.
289 CurDAG->setRoot(SDB->getControlRoot());
291 // Final step, emit the lowered DAG as machine code.
293 HadTailCall = SDB->HasTailCall;
298 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
299 /// nodes from the worklist.
300 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
301 SmallVector<SDNode*, 128> &Worklist;
302 SmallPtrSet<SDNode*, 128> &InWorklist;
304 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
305 SmallPtrSet<SDNode*, 128> &inwl)
306 : Worklist(wl), InWorklist(inwl) {}
308 void RemoveFromWorklist(SDNode *N) {
309 if (!InWorklist.erase(N)) return;
311 SmallVector<SDNode*, 128>::iterator I =
312 std::find(Worklist.begin(), Worklist.end(), N);
313 assert(I != Worklist.end() && "Not in worklist");
315 *I = Worklist.back();
319 virtual void NodeDeleted(SDNode *N, SDNode *E) {
320 RemoveFromWorklist(N);
323 virtual void NodeUpdated(SDNode *N) {
329 /// TrivialTruncElim - Eliminate some trivial nops that can result from
330 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
331 static bool TrivialTruncElim(SDValue Op,
332 TargetLowering::TargetLoweringOpt &TLO) {
333 SDValue N0 = Op.getOperand(0);
334 EVT VT = Op.getValueType();
335 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
336 N0.getOpcode() == ISD::SIGN_EXTEND ||
337 N0.getOpcode() == ISD::ANY_EXTEND) &&
338 N0.getOperand(0).getValueType() == VT) {
339 return TLO.CombineTo(Op, N0.getOperand(0));
344 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
345 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
346 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
347 void SelectionDAGISel::ShrinkDemandedOps() {
348 SmallVector<SDNode*, 128> Worklist;
349 SmallPtrSet<SDNode*, 128> InWorklist;
351 // Add all the dag nodes to the worklist.
352 Worklist.reserve(CurDAG->allnodes_size());
353 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
354 E = CurDAG->allnodes_end(); I != E; ++I) {
355 Worklist.push_back(I);
356 InWorklist.insert(I);
359 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
360 while (!Worklist.empty()) {
361 SDNode *N = Worklist.pop_back_val();
364 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
365 // Deleting this node may make its operands dead, add them to the worklist
366 // if they aren't already there.
367 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
368 if (InWorklist.insert(N->getOperand(i).getNode()))
369 Worklist.push_back(N->getOperand(i).getNode());
371 CurDAG->DeleteNode(N);
375 // Run ShrinkDemandedOp on scalar binary operations.
376 if (N->getNumValues() != 1 ||
377 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
380 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
381 APInt Demanded = APInt::getAllOnesValue(BitWidth);
382 APInt KnownZero, KnownOne;
383 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
384 KnownZero, KnownOne, TLO) &&
385 (N->getOpcode() != ISD::TRUNCATE ||
386 !TrivialTruncElim(SDValue(N, 0), TLO)))
390 assert(!InWorklist.count(N) && "Already in worklist");
391 Worklist.push_back(N);
392 InWorklist.insert(N);
394 // Replace the old value with the new one.
395 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
396 TLO.Old.getNode()->dump(CurDAG);
397 errs() << "\nWith: ";
398 TLO.New.getNode()->dump(CurDAG);
401 if (InWorklist.insert(TLO.New.getNode()))
402 Worklist.push_back(TLO.New.getNode());
404 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
405 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
407 if (!TLO.Old.getNode()->use_empty()) continue;
409 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
411 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
412 if (OpNode->hasOneUse()) {
413 // Add OpNode to the end of the list to revisit.
414 DeadNodes.RemoveFromWorklist(OpNode);
415 Worklist.push_back(OpNode);
416 InWorklist.insert(OpNode);
420 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
421 CurDAG->DeleteNode(TLO.Old.getNode());
425 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
426 SmallPtrSet<SDNode*, 128> VisitedNodes;
427 SmallVector<SDNode*, 128> Worklist;
429 Worklist.push_back(CurDAG->getRoot().getNode());
436 SDNode *N = Worklist.pop_back_val();
438 // If we've already seen this node, ignore it.
439 if (!VisitedNodes.insert(N))
442 // Otherwise, add all chain operands to the worklist.
443 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
444 if (N->getOperand(i).getValueType() == MVT::Other)
445 Worklist.push_back(N->getOperand(i).getNode());
447 // If this is a CopyToReg with a vreg dest, process it.
448 if (N->getOpcode() != ISD::CopyToReg)
451 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
452 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
455 // Ignore non-scalar or non-integer values.
456 SDValue Src = N->getOperand(2);
457 EVT SrcVT = Src.getValueType();
458 if (!SrcVT.isInteger() || SrcVT.isVector())
461 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
462 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
463 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
465 // Only install this information if it tells us something.
466 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
467 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
468 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
469 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
470 FunctionLoweringInfo::LiveOutInfo &LOI =
471 FuncInfo->LiveOutRegInfo[DestReg];
472 LOI.NumSignBits = NumSignBits;
473 LOI.KnownOne = KnownOne;
474 LOI.KnownZero = KnownZero;
476 } while (!Worklist.empty());
479 void SelectionDAGISel::CodeGenAndEmitDAG() {
480 std::string GroupName;
481 if (TimePassesIsEnabled)
482 GroupName = "Instruction Selection and Scheduling";
483 std::string BlockName;
484 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
485 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
487 BlockName = MF->getFunction()->getNameStr() + ":" +
488 BB->getBasicBlock()->getNameStr();
490 DEBUG(dbgs() << "Initial selection DAG:\n");
491 DEBUG(CurDAG->dump());
493 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
495 // Run the DAG combiner in pre-legalize mode.
496 if (TimePassesIsEnabled) {
497 NamedRegionTimer T("DAG Combining 1", GroupName);
498 CurDAG->Combine(Unrestricted, *AA, OptLevel);
500 CurDAG->Combine(Unrestricted, *AA, OptLevel);
503 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
504 DEBUG(CurDAG->dump());
506 // Second step, hack on the DAG until it only uses operations and types that
507 // the target supports.
508 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
512 if (TimePassesIsEnabled) {
513 NamedRegionTimer T("Type Legalization", GroupName);
514 Changed = CurDAG->LegalizeTypes();
516 Changed = CurDAG->LegalizeTypes();
519 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
520 DEBUG(CurDAG->dump());
523 if (ViewDAGCombineLT)
524 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
526 // Run the DAG combiner in post-type-legalize mode.
527 if (TimePassesIsEnabled) {
528 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
529 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
531 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
534 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
535 DEBUG(CurDAG->dump());
538 if (TimePassesIsEnabled) {
539 NamedRegionTimer T("Vector Legalization", GroupName);
540 Changed = CurDAG->LegalizeVectors();
542 Changed = CurDAG->LegalizeVectors();
546 if (TimePassesIsEnabled) {
547 NamedRegionTimer T("Type Legalization 2", GroupName);
548 CurDAG->LegalizeTypes();
550 CurDAG->LegalizeTypes();
553 if (ViewDAGCombineLT)
554 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
556 // Run the DAG combiner in post-type-legalize mode.
557 if (TimePassesIsEnabled) {
558 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
559 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
561 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
564 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
565 DEBUG(CurDAG->dump());
568 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
570 if (TimePassesIsEnabled) {
571 NamedRegionTimer T("DAG Legalization", GroupName);
572 CurDAG->Legalize(OptLevel);
574 CurDAG->Legalize(OptLevel);
577 DEBUG(dbgs() << "Legalized selection DAG:\n");
578 DEBUG(CurDAG->dump());
580 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
582 // Run the DAG combiner in post-legalize mode.
583 if (TimePassesIsEnabled) {
584 NamedRegionTimer T("DAG Combining 2", GroupName);
585 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
587 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
590 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
591 DEBUG(CurDAG->dump());
593 if (OptLevel != CodeGenOpt::None) {
595 ComputeLiveOutVRegInfo();
598 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
600 // Third, instruction select all of the operations to machine code, adding the
601 // code to the MachineBasicBlock.
602 if (TimePassesIsEnabled) {
603 NamedRegionTimer T("Instruction Selection", GroupName);
604 DoInstructionSelection();
606 DoInstructionSelection();
609 DEBUG(dbgs() << "Selected selection DAG:\n");
610 DEBUG(CurDAG->dump());
612 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
614 // Schedule machine code.
615 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
616 if (TimePassesIsEnabled) {
617 NamedRegionTimer T("Instruction Scheduling", GroupName);
618 Scheduler->Run(CurDAG, BB, BB->end());
620 Scheduler->Run(CurDAG, BB, BB->end());
623 if (ViewSUnitDAGs) Scheduler->viewGraph();
625 // Emit machine code to BB. This can change 'BB' to the last block being
627 if (TimePassesIsEnabled) {
628 NamedRegionTimer T("Instruction Creation", GroupName);
629 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
631 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
634 // Free the scheduler state.
635 if (TimePassesIsEnabled) {
636 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
642 DEBUG(dbgs() << "Selected machine code:\n");
646 void SelectionDAGISel::DoInstructionSelection() {
647 DEBUG(errs() << "===== Instruction selection begins:\n");
651 // Select target instructions for the DAG.
653 // Number all nodes with a topological order and set DAGSize.
654 DAGSize = CurDAG->AssignTopologicalOrder();
656 // Create a dummy node (which is not added to allnodes), that adds
657 // a reference to the root node, preventing it from being deleted,
658 // and tracking any changes of the root.
659 HandleSDNode Dummy(CurDAG->getRoot());
660 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
663 // The AllNodes list is now topological-sorted. Visit the
664 // nodes by starting at the end of the list (the root of the
665 // graph) and preceding back toward the beginning (the entry
667 while (ISelPosition != CurDAG->allnodes_begin()) {
668 SDNode *Node = --ISelPosition;
669 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
670 // but there are currently some corner cases that it misses. Also, this
671 // makes it theoretically possible to disable the DAGCombiner.
672 if (Node->use_empty())
675 SDNode *ResNode = Select(Node);
677 // FIXME: This is pretty gross. 'Select' should be changed to not return
678 // anything at all and this code should be nuked with a tactical strike.
680 // If node should not be replaced, continue with the next one.
681 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
685 ReplaceUses(Node, ResNode);
687 // If after the replacement this node is not used any more,
688 // remove this dead node.
689 if (Node->use_empty()) { // Don't delete EntryToken, etc.
690 ISelUpdater ISU(ISelPosition);
691 CurDAG->RemoveDeadNode(Node, &ISU);
695 CurDAG->setRoot(Dummy.getValue());
697 DEBUG(errs() << "===== Instruction selection ends:\n");
699 PostprocessISelDAG();
703 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
705 const TargetInstrInfo &TII) {
706 // Initialize the Fast-ISel state, if needed.
707 FastISel *FastIS = 0;
709 FastIS = TLI.createFastISel(MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
710 FuncInfo->StaticAllocaMap
712 , FuncInfo->CatchInfoLost
716 // Iterate over all basic blocks in the function.
717 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
718 BasicBlock *LLVMBB = &*I;
719 BB = FuncInfo->MBBMap[LLVMBB];
721 BasicBlock::iterator const Begin = LLVMBB->begin();
722 BasicBlock::iterator const End = LLVMBB->end();
723 BasicBlock::iterator BI = Begin;
725 // Lower any arguments needed in this block if this is the entry block.
726 bool SuppressFastISel = false;
727 if (LLVMBB == &Fn.getEntryBlock()) {
728 LowerArguments(LLVMBB);
730 // If any of the arguments has the byval attribute, forgo
731 // fast-isel in the entry block.
734 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
736 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
737 if (EnableFastISelVerbose || EnableFastISelAbort)
738 dbgs() << "FastISel skips entry block due to byval argument\n";
739 SuppressFastISel = true;
745 if (BB->isLandingPad()) {
746 // Add a label to mark the beginning of the landing pad. Deletion of the
747 // landing pad can thus be detected via the MachineModuleInfo.
748 MCSymbol *Label = MF.getMMI().addLandingPad(BB);
750 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL);
751 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
753 // Mark exception register as live in.
754 unsigned Reg = TLI.getExceptionAddressRegister();
755 if (Reg) BB->addLiveIn(Reg);
757 // Mark exception selector register as live in.
758 Reg = TLI.getExceptionSelectorRegister();
759 if (Reg) BB->addLiveIn(Reg);
761 // FIXME: Hack around an exception handling flaw (PR1508): the personality
762 // function and list of typeids logically belong to the invoke (or, if you
763 // like, the basic block containing the invoke), and need to be associated
764 // with it in the dwarf exception handling tables. Currently however the
765 // information is provided by an intrinsic (eh.selector) that can be moved
766 // to unexpected places by the optimizers: if the unwind edge is critical,
767 // then breaking it can result in the intrinsics being in the successor of
768 // the landing pad, not the landing pad itself. This results
769 // in exceptions not being caught because no typeids are associated with
770 // the invoke. This may not be the only way things can go wrong, but it
771 // is the only way we try to work around for the moment.
772 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
774 if (Br && Br->isUnconditional()) { // Critical edge?
775 BasicBlock::iterator I, E;
776 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
777 if (isa<EHSelectorInst>(I))
781 // No catch info found - try to extract some from the successor.
782 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF.getMMI(), *FuncInfo);
786 // Before doing SelectionDAG ISel, see if FastISel has been requested.
787 if (FastIS && !SuppressFastISel) {
788 // Emit code for any incoming arguments. This must happen before
789 // beginning FastISel on the entry block.
790 if (LLVMBB == &Fn.getEntryBlock()) {
791 CurDAG->setRoot(SDB->getControlRoot());
795 FastIS->startNewBlock(BB);
796 // Do FastISel on as many instructions as possible.
797 for (; BI != End; ++BI) {
798 // Just before the terminator instruction, insert instructions to
799 // feed PHI nodes in successor blocks.
800 if (isa<TerminatorInst>(BI))
801 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
802 ++NumFastIselFailures;
803 ResetDebugLoc(SDB, FastIS);
804 if (EnableFastISelVerbose || EnableFastISelAbort) {
805 dbgs() << "FastISel miss: ";
808 assert(!EnableFastISelAbort &&
809 "FastISel didn't handle a PHI in a successor");
813 SetDebugLoc(BI, SDB, FastIS, &MF);
815 // Try to select the instruction with FastISel.
816 if (FastIS->SelectInstruction(BI)) {
817 ResetDebugLoc(SDB, FastIS);
821 // Clear out the debug location so that it doesn't carry over to
822 // unrelated instructions.
823 ResetDebugLoc(SDB, FastIS);
825 // Then handle certain instructions as single-LLVM-Instruction blocks.
826 if (isa<CallInst>(BI)) {
827 ++NumFastIselFailures;
828 if (EnableFastISelVerbose || EnableFastISelAbort) {
829 dbgs() << "FastISel missed call: ";
833 if (!BI->getType()->isVoidTy()) {
834 unsigned &R = FuncInfo->ValueMap[BI];
836 R = FuncInfo->CreateRegForValue(BI);
839 bool HadTailCall = false;
840 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
842 // If the call was emitted as a tail call, we're done with the block.
848 // If the instruction was codegen'd with multiple blocks,
849 // inform the FastISel object where to resume inserting.
850 FastIS->setCurrentBlock(BB);
854 // Otherwise, give up on FastISel for the rest of the block.
855 // For now, be a little lenient about non-branch terminators.
856 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
857 ++NumFastIselFailures;
858 if (EnableFastISelVerbose || EnableFastISelAbort) {
859 dbgs() << "FastISel miss: ";
862 if (EnableFastISelAbort)
863 // The "fast" selector couldn't handle something and bailed.
864 // For the purpose of debugging, just abort.
865 llvm_unreachable("FastISel didn't select the entire block");
871 // Run SelectionDAG instruction selection on the remainder of the block
872 // not handled by FastISel. If FastISel is not run, this is the entire
876 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
886 SelectionDAGISel::FinishBasicBlock() {
888 DEBUG(dbgs() << "Target-post-processed machine code:\n");
891 DEBUG(dbgs() << "Total amount of phi nodes to update: "
892 << SDB->PHINodesToUpdate.size() << "\n");
893 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
894 dbgs() << "Node " << i << " : ("
895 << SDB->PHINodesToUpdate[i].first
896 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
898 // Next, now that we know what the last MBB the LLVM BB expanded is, update
899 // PHI nodes in successors.
900 if (SDB->SwitchCases.empty() &&
901 SDB->JTCases.empty() &&
902 SDB->BitTestCases.empty()) {
903 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
904 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
905 assert(PHI->isPHI() &&
906 "This is not a machine PHI node that we are updating!");
907 if (!BB->isSuccessor(PHI->getParent()))
909 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
911 PHI->addOperand(MachineOperand::CreateMBB(BB));
913 SDB->PHINodesToUpdate.clear();
917 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
918 // Lower header first, if it wasn't already lowered
919 if (!SDB->BitTestCases[i].Emitted) {
920 // Set the current basic block to the mbb we wish to insert the code into
921 BB = SDB->BitTestCases[i].Parent;
922 SDB->setCurrentBasicBlock(BB);
924 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
925 CurDAG->setRoot(SDB->getRoot());
930 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
931 // Set the current basic block to the mbb we wish to insert the code into
932 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
933 SDB->setCurrentBasicBlock(BB);
936 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
937 SDB->BitTestCases[i].Reg,
938 SDB->BitTestCases[i].Cases[j]);
940 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
941 SDB->BitTestCases[i].Reg,
942 SDB->BitTestCases[i].Cases[j]);
945 CurDAG->setRoot(SDB->getRoot());
951 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
952 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
953 MachineBasicBlock *PHIBB = PHI->getParent();
954 assert(PHI->isPHI() &&
955 "This is not a machine PHI node that we are updating!");
956 // This is "default" BB. We have two jumps to it. From "header" BB and
957 // from last "case" BB.
958 if (PHIBB == SDB->BitTestCases[i].Default) {
959 PHI->addOperand(MachineOperand::
960 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
961 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
962 PHI->addOperand(MachineOperand::
963 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
964 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
967 // One of "cases" BB.
968 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
970 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
971 if (cBB->isSuccessor(PHIBB)) {
972 PHI->addOperand(MachineOperand::
973 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
974 PHI->addOperand(MachineOperand::CreateMBB(cBB));
979 SDB->BitTestCases.clear();
981 // If the JumpTable record is filled in, then we need to emit a jump table.
982 // Updating the PHI nodes is tricky in this case, since we need to determine
983 // whether the PHI is a successor of the range check MBB or the jump table MBB
984 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
985 // Lower header first, if it wasn't already lowered
986 if (!SDB->JTCases[i].first.Emitted) {
987 // Set the current basic block to the mbb we wish to insert the code into
988 BB = SDB->JTCases[i].first.HeaderBB;
989 SDB->setCurrentBasicBlock(BB);
991 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
992 CurDAG->setRoot(SDB->getRoot());
997 // Set the current basic block to the mbb we wish to insert the code into
998 BB = SDB->JTCases[i].second.MBB;
999 SDB->setCurrentBasicBlock(BB);
1001 SDB->visitJumpTable(SDB->JTCases[i].second);
1002 CurDAG->setRoot(SDB->getRoot());
1003 CodeGenAndEmitDAG();
1007 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1008 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1009 MachineBasicBlock *PHIBB = PHI->getParent();
1010 assert(PHI->isPHI() &&
1011 "This is not a machine PHI node that we are updating!");
1012 // "default" BB. We can go there only from header BB.
1013 if (PHIBB == SDB->JTCases[i].second.Default) {
1015 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1017 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1019 // JT BB. Just iterate over successors here
1020 if (BB->isSuccessor(PHIBB)) {
1022 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1023 PHI->addOperand(MachineOperand::CreateMBB(BB));
1027 SDB->JTCases.clear();
1029 // If the switch block involved a branch to one of the actual successors, we
1030 // need to update PHI nodes in that block.
1031 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1032 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1033 assert(PHI->isPHI() &&
1034 "This is not a machine PHI node that we are updating!");
1035 if (BB->isSuccessor(PHI->getParent())) {
1036 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1038 PHI->addOperand(MachineOperand::CreateMBB(BB));
1042 // If we generated any switch lowering information, build and codegen any
1043 // additional DAGs necessary.
1044 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1045 // Set the current basic block to the mbb we wish to insert the code into
1046 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1047 SDB->setCurrentBasicBlock(BB);
1050 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1051 CurDAG->setRoot(SDB->getRoot());
1052 CodeGenAndEmitDAG();
1054 // Handle any PHI nodes in successors of this chunk, as if we were coming
1055 // from the original BB before switch expansion. Note that PHI nodes can
1056 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1057 // handle them the right number of times.
1058 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1059 // If new BB's are created during scheduling, the edges may have been
1060 // updated. That is, the edge from ThisBB to BB may have been split and
1061 // BB's predecessor is now another block.
1062 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1063 SDB->EdgeMapping.find(BB);
1064 if (EI != SDB->EdgeMapping.end())
1065 ThisBB = EI->second;
1067 // BB may have been removed from the CFG if a branch was constant folded.
1068 if (ThisBB->isSuccessor(BB)) {
1069 for (MachineBasicBlock::iterator Phi = BB->begin();
1070 Phi != BB->end() && Phi->isPHI();
1072 // This value for this PHI node is recorded in PHINodesToUpdate.
1073 for (unsigned pn = 0; ; ++pn) {
1074 assert(pn != SDB->PHINodesToUpdate.size() &&
1075 "Didn't find PHI entry!");
1076 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1077 Phi->addOperand(MachineOperand::
1078 CreateReg(SDB->PHINodesToUpdate[pn].second,
1080 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1087 // Don't process RHS if same block as LHS.
1088 if (BB == SDB->SwitchCases[i].FalseBB)
1089 SDB->SwitchCases[i].FalseBB = 0;
1091 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1092 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1093 SDB->SwitchCases[i].FalseBB = 0;
1095 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1098 SDB->SwitchCases.clear();
1100 SDB->PHINodesToUpdate.clear();
1104 /// Create the scheduler. If a specific scheduler was specified
1105 /// via the SchedulerRegistry, use it, otherwise select the
1106 /// one preferred by the target.
1108 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1109 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1113 RegisterScheduler::setDefault(Ctor);
1116 return Ctor(this, OptLevel);
1119 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1120 return new ScheduleHazardRecognizer();
1123 //===----------------------------------------------------------------------===//
1124 // Helper functions used by the generated instruction selector.
1125 //===----------------------------------------------------------------------===//
1126 // Calls to these methods are generated by tblgen.
1128 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1129 /// the dag combiner simplified the 255, we still want to match. RHS is the
1130 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1131 /// specified in the .td file (e.g. 255).
1132 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1133 int64_t DesiredMaskS) const {
1134 const APInt &ActualMask = RHS->getAPIntValue();
1135 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1137 // If the actual mask exactly matches, success!
1138 if (ActualMask == DesiredMask)
1141 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1142 if (ActualMask.intersects(~DesiredMask))
1145 // Otherwise, the DAG Combiner may have proven that the value coming in is
1146 // either already zero or is not demanded. Check for known zero input bits.
1147 APInt NeededMask = DesiredMask & ~ActualMask;
1148 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1151 // TODO: check to see if missing bits are just not demanded.
1153 // Otherwise, this pattern doesn't match.
1157 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1158 /// the dag combiner simplified the 255, we still want to match. RHS is the
1159 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1160 /// specified in the .td file (e.g. 255).
1161 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1162 int64_t DesiredMaskS) const {
1163 const APInt &ActualMask = RHS->getAPIntValue();
1164 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1166 // If the actual mask exactly matches, success!
1167 if (ActualMask == DesiredMask)
1170 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1171 if (ActualMask.intersects(~DesiredMask))
1174 // Otherwise, the DAG Combiner may have proven that the value coming in is
1175 // either already zero or is not demanded. Check for known zero input bits.
1176 APInt NeededMask = DesiredMask & ~ActualMask;
1178 APInt KnownZero, KnownOne;
1179 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1181 // If all the missing bits in the or are already known to be set, match!
1182 if ((NeededMask & KnownOne) == NeededMask)
1185 // TODO: check to see if missing bits are just not demanded.
1187 // Otherwise, this pattern doesn't match.
1192 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1193 /// by tblgen. Others should not call it.
1194 void SelectionDAGISel::
1195 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1196 std::vector<SDValue> InOps;
1197 std::swap(InOps, Ops);
1199 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1200 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1201 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1203 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1204 if (InOps[e-1].getValueType() == MVT::Flag)
1205 --e; // Don't process a flag operand if it is here.
1208 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1209 if (!InlineAsm::isMemKind(Flags)) {
1210 // Just skip over this operand, copying the operands verbatim.
1211 Ops.insert(Ops.end(), InOps.begin()+i,
1212 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1213 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1215 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1216 "Memory operand with multiple values?");
1217 // Otherwise, this is a memory operand. Ask the target to select it.
1218 std::vector<SDValue> SelOps;
1219 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1220 report_fatal_error("Could not match memory address. Inline asm"
1223 // Add this to the output node.
1225 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1226 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1227 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1232 // Add the flag input back if present.
1233 if (e != InOps.size())
1234 Ops.push_back(InOps.back());
1237 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1240 static SDNode *findFlagUse(SDNode *N) {
1241 unsigned FlagResNo = N->getNumValues()-1;
1242 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1243 SDUse &Use = I.getUse();
1244 if (Use.getResNo() == FlagResNo)
1245 return Use.getUser();
1250 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1251 /// This function recursively traverses up the operand chain, ignoring
1253 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1254 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1255 bool IgnoreChains) {
1256 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1257 // greater than all of its (recursive) operands. If we scan to a point where
1258 // 'use' is smaller than the node we're scanning for, then we know we will
1261 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1262 // happen because we scan down to newly selected nodes in the case of flag
1264 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1267 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1268 // won't fail if we scan it again.
1269 if (!Visited.insert(Use))
1272 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1273 // Ignore chain uses, they are validated by HandleMergeInputChains.
1274 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1277 SDNode *N = Use->getOperand(i).getNode();
1279 if (Use == ImmedUse || Use == Root)
1280 continue; // We are not looking for immediate use.
1285 // Traverse up the operand chain.
1286 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1292 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1293 /// operand node N of U during instruction selection that starts at Root.
1294 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1295 SDNode *Root) const {
1296 if (OptLevel == CodeGenOpt::None) return false;
1297 return N.hasOneUse();
1300 /// IsLegalToFold - Returns true if the specific operand node N of
1301 /// U can be folded during instruction selection that starts at Root.
1302 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1303 bool IgnoreChains) const {
1304 if (OptLevel == CodeGenOpt::None) return false;
1306 // If Root use can somehow reach N through a path that that doesn't contain
1307 // U then folding N would create a cycle. e.g. In the following
1308 // diagram, Root can reach N through X. If N is folded into into Root, then
1309 // X is both a predecessor and a successor of U.
1320 // * indicates nodes to be folded together.
1322 // If Root produces a flag, then it gets (even more) interesting. Since it
1323 // will be "glued" together with its flag use in the scheduler, we need to
1324 // check if it might reach N.
1343 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1344 // (call it Fold), then X is a predecessor of FU and a successor of
1345 // Fold. But since Fold and FU are flagged together, this will create
1346 // a cycle in the scheduling graph.
1348 // If the node has flags, walk down the graph to the "lowest" node in the
1350 EVT VT = Root->getValueType(Root->getNumValues()-1);
1351 while (VT == MVT::Flag) {
1352 SDNode *FU = findFlagUse(Root);
1356 VT = Root->getValueType(Root->getNumValues()-1);
1358 // If our query node has a flag result with a use, we've walked up it. If
1359 // the user (which has already been selected) has a chain or indirectly uses
1360 // the chain, our WalkChainUsers predicate will not consider it. Because of
1361 // this, we cannot ignore chains in this predicate.
1362 IgnoreChains = false;
1366 SmallPtrSet<SDNode*, 16> Visited;
1367 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1370 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1371 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1372 SelectInlineAsmMemoryOperands(Ops);
1374 std::vector<EVT> VTs;
1375 VTs.push_back(MVT::Other);
1376 VTs.push_back(MVT::Flag);
1377 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1378 VTs, &Ops[0], Ops.size());
1380 return New.getNode();
1383 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1384 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1387 /// GetVBR - decode a vbr encoding whose top bit is set.
1388 ALWAYS_INLINE static uint64_t
1389 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1390 assert(Val >= 128 && "Not a VBR");
1391 Val &= 127; // Remove first vbr bit.
1396 NextBits = MatcherTable[Idx++];
1397 Val |= (NextBits&127) << Shift;
1399 } while (NextBits & 128);
1405 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1406 /// interior flag and chain results to use the new flag and chain results.
1407 void SelectionDAGISel::
1408 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1409 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1411 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1412 bool isMorphNodeTo) {
1413 SmallVector<SDNode*, 4> NowDeadNodes;
1415 ISelUpdater ISU(ISelPosition);
1417 // Now that all the normal results are replaced, we replace the chain and
1418 // flag results if present.
1419 if (!ChainNodesMatched.empty()) {
1420 assert(InputChain.getNode() != 0 &&
1421 "Matched input chains but didn't produce a chain");
1422 // Loop over all of the nodes we matched that produced a chain result.
1423 // Replace all the chain results with the final chain we ended up with.
1424 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1425 SDNode *ChainNode = ChainNodesMatched[i];
1427 // If this node was already deleted, don't look at it.
1428 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1431 // Don't replace the results of the root node if we're doing a
1433 if (ChainNode == NodeToMatch && isMorphNodeTo)
1436 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1437 if (ChainVal.getValueType() == MVT::Flag)
1438 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1439 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1440 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1442 // If the node became dead and we haven't already seen it, delete it.
1443 if (ChainNode->use_empty() &&
1444 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1445 NowDeadNodes.push_back(ChainNode);
1449 // If the result produces a flag, update any flag results in the matched
1450 // pattern with the flag result.
1451 if (InputFlag.getNode() != 0) {
1452 // Handle any interior nodes explicitly marked.
1453 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1454 SDNode *FRN = FlagResultNodesMatched[i];
1456 // If this node was already deleted, don't look at it.
1457 if (FRN->getOpcode() == ISD::DELETED_NODE)
1460 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1461 "Doesn't have a flag result");
1462 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1465 // If the node became dead and we haven't already seen it, delete it.
1466 if (FRN->use_empty() &&
1467 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1468 NowDeadNodes.push_back(FRN);
1472 if (!NowDeadNodes.empty())
1473 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1475 DEBUG(errs() << "ISEL: Match complete!\n");
1481 CR_LeadsToInteriorNode
1484 /// WalkChainUsers - Walk down the users of the specified chained node that is
1485 /// part of the pattern we're matching, looking at all of the users we find.
1486 /// This determines whether something is an interior node, whether we have a
1487 /// non-pattern node in between two pattern nodes (which prevent folding because
1488 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1489 /// between pattern nodes (in which case the TF becomes part of the pattern).
1491 /// The walk we do here is guaranteed to be small because we quickly get down to
1492 /// already selected nodes "below" us.
1494 WalkChainUsers(SDNode *ChainedNode,
1495 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1496 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1497 ChainResult Result = CR_Simple;
1499 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1500 E = ChainedNode->use_end(); UI != E; ++UI) {
1501 // Make sure the use is of the chain, not some other value we produce.
1502 if (UI.getUse().getValueType() != MVT::Other) continue;
1506 // If we see an already-selected machine node, then we've gone beyond the
1507 // pattern that we're selecting down into the already selected chunk of the
1509 if (User->isMachineOpcode() ||
1510 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1513 if (User->getOpcode() == ISD::CopyToReg ||
1514 User->getOpcode() == ISD::CopyFromReg ||
1515 User->getOpcode() == ISD::INLINEASM ||
1516 User->getOpcode() == ISD::EH_LABEL) {
1517 // If their node ID got reset to -1 then they've already been selected.
1518 // Treat them like a MachineOpcode.
1519 if (User->getNodeId() == -1)
1523 // If we have a TokenFactor, we handle it specially.
1524 if (User->getOpcode() != ISD::TokenFactor) {
1525 // If the node isn't a token factor and isn't part of our pattern, then it
1526 // must be a random chained node in between two nodes we're selecting.
1527 // This happens when we have something like:
1532 // Because we structurally match the load/store as a read/modify/write,
1533 // but the call is chained between them. We cannot fold in this case
1534 // because it would induce a cycle in the graph.
1535 if (!std::count(ChainedNodesInPattern.begin(),
1536 ChainedNodesInPattern.end(), User))
1537 return CR_InducesCycle;
1539 // Otherwise we found a node that is part of our pattern. For example in:
1543 // This would happen when we're scanning down from the load and see the
1544 // store as a user. Record that there is a use of ChainedNode that is
1545 // part of the pattern and keep scanning uses.
1546 Result = CR_LeadsToInteriorNode;
1547 InteriorChainedNodes.push_back(User);
1551 // If we found a TokenFactor, there are two cases to consider: first if the
1552 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1553 // uses of the TF are in our pattern) we just want to ignore it. Second,
1554 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1560 // | \ DAG's like cheese
1563 // [TokenFactor] [Op]
1570 // In this case, the TokenFactor becomes part of our match and we rewrite it
1571 // as a new TokenFactor.
1573 // To distinguish these two cases, do a recursive walk down the uses.
1574 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1576 // If the uses of the TokenFactor are just already-selected nodes, ignore
1577 // it, it is "below" our pattern.
1579 case CR_InducesCycle:
1580 // If the uses of the TokenFactor lead to nodes that are not part of our
1581 // pattern that are not selected, folding would turn this into a cycle,
1583 return CR_InducesCycle;
1584 case CR_LeadsToInteriorNode:
1585 break; // Otherwise, keep processing.
1588 // Okay, we know we're in the interesting interior case. The TokenFactor
1589 // is now going to be considered part of the pattern so that we rewrite its
1590 // uses (it may have uses that are not part of the pattern) with the
1591 // ultimate chain result of the generated code. We will also add its chain
1592 // inputs as inputs to the ultimate TokenFactor we create.
1593 Result = CR_LeadsToInteriorNode;
1594 ChainedNodesInPattern.push_back(User);
1595 InteriorChainedNodes.push_back(User);
1602 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1603 /// operation for when the pattern matched at least one node with a chains. The
1604 /// input vector contains a list of all of the chained nodes that we match. We
1605 /// must determine if this is a valid thing to cover (i.e. matching it won't
1606 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1607 /// be used as the input node chain for the generated nodes.
1609 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1610 SelectionDAG *CurDAG) {
1611 // Walk all of the chained nodes we've matched, recursively scanning down the
1612 // users of the chain result. This adds any TokenFactor nodes that are caught
1613 // in between chained nodes to the chained and interior nodes list.
1614 SmallVector<SDNode*, 3> InteriorChainedNodes;
1615 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1616 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1617 InteriorChainedNodes) == CR_InducesCycle)
1618 return SDValue(); // Would induce a cycle.
1621 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1622 // that we are interested in. Form our input TokenFactor node.
1623 SmallVector<SDValue, 3> InputChains;
1624 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1625 // Add the input chain of this node to the InputChains list (which will be
1626 // the operands of the generated TokenFactor) if it's not an interior node.
1627 SDNode *N = ChainNodesMatched[i];
1628 if (N->getOpcode() != ISD::TokenFactor) {
1629 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1632 // Otherwise, add the input chain.
1633 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1634 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1635 InputChains.push_back(InChain);
1639 // If we have a token factor, we want to add all inputs of the token factor
1640 // that are not part of the pattern we're matching.
1641 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1642 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1643 N->getOperand(op).getNode()))
1644 InputChains.push_back(N->getOperand(op));
1649 if (InputChains.size() == 1)
1650 return InputChains[0];
1651 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1652 MVT::Other, &InputChains[0], InputChains.size());
1655 /// MorphNode - Handle morphing a node in place for the selector.
1656 SDNode *SelectionDAGISel::
1657 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1658 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1659 // It is possible we're using MorphNodeTo to replace a node with no
1660 // normal results with one that has a normal result (or we could be
1661 // adding a chain) and the input could have flags and chains as well.
1662 // In this case we need to shift the operands down.
1663 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1664 // than the old isel though.
1665 int OldFlagResultNo = -1, OldChainResultNo = -1;
1667 unsigned NTMNumResults = Node->getNumValues();
1668 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1669 OldFlagResultNo = NTMNumResults-1;
1670 if (NTMNumResults != 1 &&
1671 Node->getValueType(NTMNumResults-2) == MVT::Other)
1672 OldChainResultNo = NTMNumResults-2;
1673 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1674 OldChainResultNo = NTMNumResults-1;
1676 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1677 // that this deletes operands of the old node that become dead.
1678 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1680 // MorphNodeTo can operate in two ways: if an existing node with the
1681 // specified operands exists, it can just return it. Otherwise, it
1682 // updates the node in place to have the requested operands.
1684 // If we updated the node in place, reset the node ID. To the isel,
1685 // this should be just like a newly allocated machine node.
1689 unsigned ResNumResults = Res->getNumValues();
1690 // Move the flag if needed.
1691 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1692 (unsigned)OldFlagResultNo != ResNumResults-1)
1693 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1694 SDValue(Res, ResNumResults-1));
1696 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1699 // Move the chain reference if needed.
1700 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1701 (unsigned)OldChainResultNo != ResNumResults-1)
1702 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1703 SDValue(Res, ResNumResults-1));
1705 // Otherwise, no replacement happened because the node already exists. Replace
1706 // Uses of the old node with the new one.
1708 CurDAG->ReplaceAllUsesWith(Node, Res);
1713 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1714 ALWAYS_INLINE static bool
1715 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1716 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1717 // Accept if it is exactly the same as a previously recorded node.
1718 unsigned RecNo = MatcherTable[MatcherIndex++];
1719 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1720 return N == RecordedNodes[RecNo];
1723 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1724 ALWAYS_INLINE static bool
1725 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1726 SelectionDAGISel &SDISel) {
1727 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1730 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1731 ALWAYS_INLINE static bool
1732 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1733 SelectionDAGISel &SDISel, SDNode *N) {
1734 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1737 ALWAYS_INLINE static bool
1738 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1740 uint16_t Opc = MatcherTable[MatcherIndex++];
1741 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1742 return N->getOpcode() == Opc;
1745 ALWAYS_INLINE static bool
1746 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1747 SDValue N, const TargetLowering &TLI) {
1748 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1749 if (N.getValueType() == VT) return true;
1751 // Handle the case when VT is iPTR.
1752 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1755 ALWAYS_INLINE static bool
1756 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1757 SDValue N, const TargetLowering &TLI,
1759 if (ChildNo >= N.getNumOperands())
1760 return false; // Match fails if out of range child #.
1761 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1765 ALWAYS_INLINE static bool
1766 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1768 return cast<CondCodeSDNode>(N)->get() ==
1769 (ISD::CondCode)MatcherTable[MatcherIndex++];
1772 ALWAYS_INLINE static bool
1773 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1774 SDValue N, const TargetLowering &TLI) {
1775 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1776 if (cast<VTSDNode>(N)->getVT() == VT)
1779 // Handle the case when VT is iPTR.
1780 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1783 ALWAYS_INLINE static bool
1784 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1786 int64_t Val = MatcherTable[MatcherIndex++];
1788 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1790 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1791 return C != 0 && C->getSExtValue() == Val;
1794 ALWAYS_INLINE static bool
1795 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1796 SDValue N, SelectionDAGISel &SDISel) {
1797 int64_t Val = MatcherTable[MatcherIndex++];
1799 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1801 if (N->getOpcode() != ISD::AND) return false;
1803 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1804 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1807 ALWAYS_INLINE static bool
1808 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1809 SDValue N, SelectionDAGISel &SDISel) {
1810 int64_t Val = MatcherTable[MatcherIndex++];
1812 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1814 if (N->getOpcode() != ISD::OR) return false;
1816 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1817 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1820 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1821 /// scope, evaluate the current node. If the current predicate is known to
1822 /// fail, set Result=true and return anything. If the current predicate is
1823 /// known to pass, set Result=false and return the MatcherIndex to continue
1824 /// with. If the current predicate is unknown, set Result=false and return the
1825 /// MatcherIndex to continue with.
1826 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1827 unsigned Index, SDValue N,
1828 bool &Result, SelectionDAGISel &SDISel,
1829 SmallVectorImpl<SDValue> &RecordedNodes){
1830 switch (Table[Index++]) {
1833 return Index-1; // Could not evaluate this predicate.
1834 case SelectionDAGISel::OPC_CheckSame:
1835 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1837 case SelectionDAGISel::OPC_CheckPatternPredicate:
1838 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1840 case SelectionDAGISel::OPC_CheckPredicate:
1841 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1843 case SelectionDAGISel::OPC_CheckOpcode:
1844 Result = !::CheckOpcode(Table, Index, N.getNode());
1846 case SelectionDAGISel::OPC_CheckType:
1847 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1849 case SelectionDAGISel::OPC_CheckChild0Type:
1850 case SelectionDAGISel::OPC_CheckChild1Type:
1851 case SelectionDAGISel::OPC_CheckChild2Type:
1852 case SelectionDAGISel::OPC_CheckChild3Type:
1853 case SelectionDAGISel::OPC_CheckChild4Type:
1854 case SelectionDAGISel::OPC_CheckChild5Type:
1855 case SelectionDAGISel::OPC_CheckChild6Type:
1856 case SelectionDAGISel::OPC_CheckChild7Type:
1857 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1858 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1860 case SelectionDAGISel::OPC_CheckCondCode:
1861 Result = !::CheckCondCode(Table, Index, N);
1863 case SelectionDAGISel::OPC_CheckValueType:
1864 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1866 case SelectionDAGISel::OPC_CheckInteger:
1867 Result = !::CheckInteger(Table, Index, N);
1869 case SelectionDAGISel::OPC_CheckAndImm:
1870 Result = !::CheckAndImm(Table, Index, N, SDISel);
1872 case SelectionDAGISel::OPC_CheckOrImm:
1873 Result = !::CheckOrImm(Table, Index, N, SDISel);
1880 /// FailIndex - If this match fails, this is the index to continue with.
1883 /// NodeStack - The node stack when the scope was formed.
1884 SmallVector<SDValue, 4> NodeStack;
1886 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1887 unsigned NumRecordedNodes;
1889 /// NumMatchedMemRefs - The number of matched memref entries.
1890 unsigned NumMatchedMemRefs;
1892 /// InputChain/InputFlag - The current chain/flag
1893 SDValue InputChain, InputFlag;
1895 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1896 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1899 SDNode *SelectionDAGISel::
1900 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1901 unsigned TableSize) {
1902 // FIXME: Should these even be selected? Handle these cases in the caller?
1903 switch (NodeToMatch->getOpcode()) {
1906 case ISD::EntryToken: // These nodes remain the same.
1907 case ISD::BasicBlock:
1909 //case ISD::VALUETYPE:
1910 //case ISD::CONDCODE:
1911 case ISD::HANDLENODE:
1912 case ISD::MDNODE_SDNODE:
1913 case ISD::TargetConstant:
1914 case ISD::TargetConstantFP:
1915 case ISD::TargetConstantPool:
1916 case ISD::TargetFrameIndex:
1917 case ISD::TargetExternalSymbol:
1918 case ISD::TargetBlockAddress:
1919 case ISD::TargetJumpTable:
1920 case ISD::TargetGlobalTLSAddress:
1921 case ISD::TargetGlobalAddress:
1922 case ISD::TokenFactor:
1923 case ISD::CopyFromReg:
1924 case ISD::CopyToReg:
1926 NodeToMatch->setNodeId(-1); // Mark selected.
1928 case ISD::AssertSext:
1929 case ISD::AssertZext:
1930 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1931 NodeToMatch->getOperand(0));
1933 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1934 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1937 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1939 // Set up the node stack with NodeToMatch as the only node on the stack.
1940 SmallVector<SDValue, 8> NodeStack;
1941 SDValue N = SDValue(NodeToMatch, 0);
1942 NodeStack.push_back(N);
1944 // MatchScopes - Scopes used when matching, if a match failure happens, this
1945 // indicates where to continue checking.
1946 SmallVector<MatchScope, 8> MatchScopes;
1948 // RecordedNodes - This is the set of nodes that have been recorded by the
1950 SmallVector<SDValue, 8> RecordedNodes;
1952 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1954 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1956 // These are the current input chain and flag for use when generating nodes.
1957 // Various Emit operations change these. For example, emitting a copytoreg
1958 // uses and updates these.
1959 SDValue InputChain, InputFlag;
1961 // ChainNodesMatched - If a pattern matches nodes that have input/output
1962 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1963 // which ones they are. The result is captured into this list so that we can
1964 // update the chain results when the pattern is complete.
1965 SmallVector<SDNode*, 3> ChainNodesMatched;
1966 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1968 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1969 NodeToMatch->dump(CurDAG);
1972 // Determine where to start the interpreter. Normally we start at opcode #0,
1973 // but if the state machine starts with an OPC_SwitchOpcode, then we
1974 // accelerate the first lookup (which is guaranteed to be hot) with the
1975 // OpcodeOffset table.
1976 unsigned MatcherIndex = 0;
1978 if (!OpcodeOffset.empty()) {
1979 // Already computed the OpcodeOffset table, just index into it.
1980 if (N.getOpcode() < OpcodeOffset.size())
1981 MatcherIndex = OpcodeOffset[N.getOpcode()];
1982 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1984 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1985 // Otherwise, the table isn't computed, but the state machine does start
1986 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1987 // is the first time we're selecting an instruction.
1990 // Get the size of this case.
1991 unsigned CaseSize = MatcherTable[Idx++];
1993 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1994 if (CaseSize == 0) break;
1996 // Get the opcode, add the index to the table.
1997 uint16_t Opc = MatcherTable[Idx++];
1998 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1999 if (Opc >= OpcodeOffset.size())
2000 OpcodeOffset.resize((Opc+1)*2);
2001 OpcodeOffset[Opc] = Idx;
2005 // Okay, do the lookup for the first opcode.
2006 if (N.getOpcode() < OpcodeOffset.size())
2007 MatcherIndex = OpcodeOffset[N.getOpcode()];
2011 assert(MatcherIndex < TableSize && "Invalid index");
2013 unsigned CurrentOpcodeIndex = MatcherIndex;
2015 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2018 // Okay, the semantics of this operation are that we should push a scope
2019 // then evaluate the first child. However, pushing a scope only to have
2020 // the first check fail (which then pops it) is inefficient. If we can
2021 // determine immediately that the first check (or first several) will
2022 // immediately fail, don't even bother pushing a scope for them.
2026 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2027 if (NumToSkip & 128)
2028 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2029 // Found the end of the scope with no match.
2030 if (NumToSkip == 0) {
2035 FailIndex = MatcherIndex+NumToSkip;
2037 unsigned MatcherIndexOfPredicate = MatcherIndex;
2038 (void)MatcherIndexOfPredicate; // silence warning.
2040 // If we can't evaluate this predicate without pushing a scope (e.g. if
2041 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2042 // push the scope and evaluate the full predicate chain.
2044 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2045 Result, *this, RecordedNodes);
2049 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2050 << "index " << MatcherIndexOfPredicate
2051 << ", continuing at " << FailIndex << "\n");
2052 ++NumDAGIselRetries;
2054 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2055 // move to the next case.
2056 MatcherIndex = FailIndex;
2059 // If the whole scope failed to match, bail.
2060 if (FailIndex == 0) break;
2062 // Push a MatchScope which indicates where to go if the first child fails
2064 MatchScope NewEntry;
2065 NewEntry.FailIndex = FailIndex;
2066 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2067 NewEntry.NumRecordedNodes = RecordedNodes.size();
2068 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2069 NewEntry.InputChain = InputChain;
2070 NewEntry.InputFlag = InputFlag;
2071 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2072 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2073 MatchScopes.push_back(NewEntry);
2076 case OPC_RecordNode:
2077 // Remember this node, it may end up being an operand in the pattern.
2078 RecordedNodes.push_back(N);
2081 case OPC_RecordChild0: case OPC_RecordChild1:
2082 case OPC_RecordChild2: case OPC_RecordChild3:
2083 case OPC_RecordChild4: case OPC_RecordChild5:
2084 case OPC_RecordChild6: case OPC_RecordChild7: {
2085 unsigned ChildNo = Opcode-OPC_RecordChild0;
2086 if (ChildNo >= N.getNumOperands())
2087 break; // Match fails if out of range child #.
2089 RecordedNodes.push_back(N->getOperand(ChildNo));
2092 case OPC_RecordMemRef:
2093 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2096 case OPC_CaptureFlagInput:
2097 // If the current node has an input flag, capture it in InputFlag.
2098 if (N->getNumOperands() != 0 &&
2099 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2100 InputFlag = N->getOperand(N->getNumOperands()-1);
2103 case OPC_MoveChild: {
2104 unsigned ChildNo = MatcherTable[MatcherIndex++];
2105 if (ChildNo >= N.getNumOperands())
2106 break; // Match fails if out of range child #.
2107 N = N.getOperand(ChildNo);
2108 NodeStack.push_back(N);
2112 case OPC_MoveParent:
2113 // Pop the current node off the NodeStack.
2114 NodeStack.pop_back();
2115 assert(!NodeStack.empty() && "Node stack imbalance!");
2116 N = NodeStack.back();
2120 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2122 case OPC_CheckPatternPredicate:
2123 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2125 case OPC_CheckPredicate:
2126 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2130 case OPC_CheckComplexPat: {
2131 unsigned CPNum = MatcherTable[MatcherIndex++];
2132 unsigned RecNo = MatcherTable[MatcherIndex++];
2133 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2134 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2139 case OPC_CheckOpcode:
2140 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2144 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2147 case OPC_SwitchOpcode: {
2148 unsigned CurNodeOpcode = N.getOpcode();
2149 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2152 // Get the size of this case.
2153 CaseSize = MatcherTable[MatcherIndex++];
2155 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2156 if (CaseSize == 0) break;
2158 uint16_t Opc = MatcherTable[MatcherIndex++];
2159 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2161 // If the opcode matches, then we will execute this case.
2162 if (CurNodeOpcode == Opc)
2165 // Otherwise, skip over this case.
2166 MatcherIndex += CaseSize;
2169 // If no cases matched, bail out.
2170 if (CaseSize == 0) break;
2172 // Otherwise, execute the case we found.
2173 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2174 << " to " << MatcherIndex << "\n");
2178 case OPC_SwitchType: {
2179 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2180 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2183 // Get the size of this case.
2184 CaseSize = MatcherTable[MatcherIndex++];
2186 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2187 if (CaseSize == 0) break;
2189 MVT::SimpleValueType CaseVT =
2190 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2191 if (CaseVT == MVT::iPTR)
2192 CaseVT = TLI.getPointerTy().SimpleTy;
2194 // If the VT matches, then we will execute this case.
2195 if (CurNodeVT == CaseVT)
2198 // Otherwise, skip over this case.
2199 MatcherIndex += CaseSize;
2202 // If no cases matched, bail out.
2203 if (CaseSize == 0) break;
2205 // Otherwise, execute the case we found.
2206 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2207 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2210 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2211 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2212 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2213 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2214 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2215 Opcode-OPC_CheckChild0Type))
2218 case OPC_CheckCondCode:
2219 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2221 case OPC_CheckValueType:
2222 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2224 case OPC_CheckInteger:
2225 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2227 case OPC_CheckAndImm:
2228 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2230 case OPC_CheckOrImm:
2231 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2234 case OPC_CheckFoldableChainNode: {
2235 assert(NodeStack.size() != 1 && "No parent node");
2236 // Verify that all intermediate nodes between the root and this one have
2238 bool HasMultipleUses = false;
2239 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2240 if (!NodeStack[i].hasOneUse()) {
2241 HasMultipleUses = true;
2244 if (HasMultipleUses) break;
2246 // Check to see that the target thinks this is profitable to fold and that
2247 // we can fold it without inducing cycles in the graph.
2248 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2250 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2251 NodeToMatch, true/*We validate our own chains*/))
2256 case OPC_EmitInteger: {
2257 MVT::SimpleValueType VT =
2258 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2259 int64_t Val = MatcherTable[MatcherIndex++];
2261 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2262 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2265 case OPC_EmitRegister: {
2266 MVT::SimpleValueType VT =
2267 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2268 unsigned RegNo = MatcherTable[MatcherIndex++];
2269 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2273 case OPC_EmitConvertToTarget: {
2274 // Convert from IMM/FPIMM to target version.
2275 unsigned RecNo = MatcherTable[MatcherIndex++];
2276 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2277 SDValue Imm = RecordedNodes[RecNo];
2279 if (Imm->getOpcode() == ISD::Constant) {
2280 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2281 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2282 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2283 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2284 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2287 RecordedNodes.push_back(Imm);
2291 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2292 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2293 // These are space-optimized forms of OPC_EmitMergeInputChains.
2294 assert(InputChain.getNode() == 0 &&
2295 "EmitMergeInputChains should be the first chain producing node");
2296 assert(ChainNodesMatched.empty() &&
2297 "Should only have one EmitMergeInputChains per match");
2299 // Read all of the chained nodes.
2300 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2301 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2302 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2304 // FIXME: What if other value results of the node have uses not matched
2306 if (ChainNodesMatched.back() != NodeToMatch &&
2307 !RecordedNodes[RecNo].hasOneUse()) {
2308 ChainNodesMatched.clear();
2312 // Merge the input chains if they are not intra-pattern references.
2313 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2315 if (InputChain.getNode() == 0)
2316 break; // Failed to merge.
2320 case OPC_EmitMergeInputChains: {
2321 assert(InputChain.getNode() == 0 &&
2322 "EmitMergeInputChains should be the first chain producing node");
2323 // This node gets a list of nodes we matched in the input that have
2324 // chains. We want to token factor all of the input chains to these nodes
2325 // together. However, if any of the input chains is actually one of the
2326 // nodes matched in this pattern, then we have an intra-match reference.
2327 // Ignore these because the newly token factored chain should not refer to
2329 unsigned NumChains = MatcherTable[MatcherIndex++];
2330 assert(NumChains != 0 && "Can't TF zero chains");
2332 assert(ChainNodesMatched.empty() &&
2333 "Should only have one EmitMergeInputChains per match");
2335 // Read all of the chained nodes.
2336 for (unsigned i = 0; i != NumChains; ++i) {
2337 unsigned RecNo = MatcherTable[MatcherIndex++];
2338 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2339 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2341 // FIXME: What if other value results of the node have uses not matched
2343 if (ChainNodesMatched.back() != NodeToMatch &&
2344 !RecordedNodes[RecNo].hasOneUse()) {
2345 ChainNodesMatched.clear();
2350 // If the inner loop broke out, the match fails.
2351 if (ChainNodesMatched.empty())
2354 // Merge the input chains if they are not intra-pattern references.
2355 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2357 if (InputChain.getNode() == 0)
2358 break; // Failed to merge.
2363 case OPC_EmitCopyToReg: {
2364 unsigned RecNo = MatcherTable[MatcherIndex++];
2365 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2366 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2368 if (InputChain.getNode() == 0)
2369 InputChain = CurDAG->getEntryNode();
2371 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2372 DestPhysReg, RecordedNodes[RecNo],
2375 InputFlag = InputChain.getValue(1);
2379 case OPC_EmitNodeXForm: {
2380 unsigned XFormNo = MatcherTable[MatcherIndex++];
2381 unsigned RecNo = MatcherTable[MatcherIndex++];
2382 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2383 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2388 case OPC_MorphNodeTo: {
2389 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2390 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2391 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2392 // Get the result VT list.
2393 unsigned NumVTs = MatcherTable[MatcherIndex++];
2394 SmallVector<EVT, 4> VTs;
2395 for (unsigned i = 0; i != NumVTs; ++i) {
2396 MVT::SimpleValueType VT =
2397 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2398 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2402 if (EmitNodeInfo & OPFL_Chain)
2403 VTs.push_back(MVT::Other);
2404 if (EmitNodeInfo & OPFL_FlagOutput)
2405 VTs.push_back(MVT::Flag);
2407 // This is hot code, so optimize the two most common cases of 1 and 2
2410 if (VTs.size() == 1)
2411 VTList = CurDAG->getVTList(VTs[0]);
2412 else if (VTs.size() == 2)
2413 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2415 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2417 // Get the operand list.
2418 unsigned NumOps = MatcherTable[MatcherIndex++];
2419 SmallVector<SDValue, 8> Ops;
2420 for (unsigned i = 0; i != NumOps; ++i) {
2421 unsigned RecNo = MatcherTable[MatcherIndex++];
2423 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2425 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2426 Ops.push_back(RecordedNodes[RecNo]);
2429 // If there are variadic operands to add, handle them now.
2430 if (EmitNodeInfo & OPFL_VariadicInfo) {
2431 // Determine the start index to copy from.
2432 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2433 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2434 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2435 "Invalid variadic node");
2436 // Copy all of the variadic operands, not including a potential flag
2438 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2440 SDValue V = NodeToMatch->getOperand(i);
2441 if (V.getValueType() == MVT::Flag) break;
2446 // If this has chain/flag inputs, add them.
2447 if (EmitNodeInfo & OPFL_Chain)
2448 Ops.push_back(InputChain);
2449 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2450 Ops.push_back(InputFlag);
2454 if (Opcode != OPC_MorphNodeTo) {
2455 // If this is a normal EmitNode command, just create the new node and
2456 // add the results to the RecordedNodes list.
2457 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2458 VTList, Ops.data(), Ops.size());
2460 // Add all the non-flag/non-chain results to the RecordedNodes list.
2461 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2462 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2463 RecordedNodes.push_back(SDValue(Res, i));
2467 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2471 // If the node had chain/flag results, update our notion of the current
2473 if (EmitNodeInfo & OPFL_FlagOutput) {
2474 InputFlag = SDValue(Res, VTs.size()-1);
2475 if (EmitNodeInfo & OPFL_Chain)
2476 InputChain = SDValue(Res, VTs.size()-2);
2477 } else if (EmitNodeInfo & OPFL_Chain)
2478 InputChain = SDValue(Res, VTs.size()-1);
2480 // If the OPFL_MemRefs flag is set on this node, slap all of the
2481 // accumulated memrefs onto it.
2483 // FIXME: This is vastly incorrect for patterns with multiple outputs
2484 // instructions that access memory and for ComplexPatterns that match
2486 if (EmitNodeInfo & OPFL_MemRefs) {
2487 MachineSDNode::mmo_iterator MemRefs =
2488 MF->allocateMemRefsArray(MatchedMemRefs.size());
2489 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2490 cast<MachineSDNode>(Res)
2491 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2495 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2496 << " node: "; Res->dump(CurDAG); errs() << "\n");
2498 // If this was a MorphNodeTo then we're completely done!
2499 if (Opcode == OPC_MorphNodeTo) {
2500 // Update chain and flag uses.
2501 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2502 InputFlag, FlagResultNodesMatched, true);
2509 case OPC_MarkFlagResults: {
2510 unsigned NumNodes = MatcherTable[MatcherIndex++];
2512 // Read and remember all the flag-result nodes.
2513 for (unsigned i = 0; i != NumNodes; ++i) {
2514 unsigned RecNo = MatcherTable[MatcherIndex++];
2516 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2518 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2519 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2524 case OPC_CompleteMatch: {
2525 // The match has been completed, and any new nodes (if any) have been
2526 // created. Patch up references to the matched dag to use the newly
2528 unsigned NumResults = MatcherTable[MatcherIndex++];
2530 for (unsigned i = 0; i != NumResults; ++i) {
2531 unsigned ResSlot = MatcherTable[MatcherIndex++];
2533 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2535 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2536 SDValue Res = RecordedNodes[ResSlot];
2538 assert(i < NodeToMatch->getNumValues() &&
2539 NodeToMatch->getValueType(i) != MVT::Other &&
2540 NodeToMatch->getValueType(i) != MVT::Flag &&
2541 "Invalid number of results to complete!");
2542 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2543 NodeToMatch->getValueType(i) == MVT::iPTR ||
2544 Res.getValueType() == MVT::iPTR ||
2545 NodeToMatch->getValueType(i).getSizeInBits() ==
2546 Res.getValueType().getSizeInBits()) &&
2547 "invalid replacement");
2548 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2551 // If the root node defines a flag, add it to the flag nodes to update
2553 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2554 FlagResultNodesMatched.push_back(NodeToMatch);
2556 // Update chain and flag uses.
2557 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2558 InputFlag, FlagResultNodesMatched, false);
2560 assert(NodeToMatch->use_empty() &&
2561 "Didn't replace all uses of the node?");
2563 // FIXME: We just return here, which interacts correctly with SelectRoot
2564 // above. We should fix this to not return an SDNode* anymore.
2569 // If the code reached this point, then the match failed. See if there is
2570 // another child to try in the current 'Scope', otherwise pop it until we
2571 // find a case to check.
2572 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2573 ++NumDAGIselRetries;
2575 if (MatchScopes.empty()) {
2576 CannotYetSelect(NodeToMatch);
2580 // Restore the interpreter state back to the point where the scope was
2582 MatchScope &LastScope = MatchScopes.back();
2583 RecordedNodes.resize(LastScope.NumRecordedNodes);
2585 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2586 N = NodeStack.back();
2588 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2589 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2590 MatcherIndex = LastScope.FailIndex;
2592 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2594 InputChain = LastScope.InputChain;
2595 InputFlag = LastScope.InputFlag;
2596 if (!LastScope.HasChainNodesMatched)
2597 ChainNodesMatched.clear();
2598 if (!LastScope.HasFlagResultNodesMatched)
2599 FlagResultNodesMatched.clear();
2601 // Check to see what the offset is at the new MatcherIndex. If it is zero
2602 // we have reached the end of this scope, otherwise we have another child
2603 // in the current scope to try.
2604 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2605 if (NumToSkip & 128)
2606 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2608 // If we have another child in this scope to match, update FailIndex and
2610 if (NumToSkip != 0) {
2611 LastScope.FailIndex = MatcherIndex+NumToSkip;
2615 // End of this scope, pop it and try the next child in the containing
2617 MatchScopes.pop_back();
2624 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2626 raw_string_ostream Msg(msg);
2627 Msg << "Cannot yet select: ";
2629 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2630 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2631 N->getOpcode() != ISD::INTRINSIC_VOID) {
2632 N->printrFull(Msg, CurDAG);
2634 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2636 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2637 if (iid < Intrinsic::num_intrinsics)
2638 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2639 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2640 Msg << "target intrinsic %" << TII->getName(iid);
2642 Msg << "unknown intrinsic #" << iid;
2644 report_fatal_error(Msg.str());
2647 char SelectionDAGISel::ID = 0;