1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/DebugInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
39 #include "llvm/CodeGen/SchedulerRegistry.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Target/TargetIntrinsicInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLibraryInfo.h"
45 #include "llvm/Target/TargetLowering.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/Timer.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/ADT/PostOrderIterator.h"
55 #include "llvm/ADT/Statistic.h"
59 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
60 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
61 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
62 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
63 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
68 cl::desc("Enable extra verbose messages in the \"fast\" "
69 "instruction selector"));
71 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
72 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
73 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
74 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
75 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
76 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
77 STATISTIC(NumFastIselFailUnwind,"Fast isel fails on Unwind");
78 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
80 // Standard binary operators...
81 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
82 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
83 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
84 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
85 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
86 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
87 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
88 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
89 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
90 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
91 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
92 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
94 // Logical operators...
95 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
96 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
97 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
99 // Memory instructions...
100 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
101 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
102 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
103 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
104 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
105 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
106 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
108 // Convert instructions...
109 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
110 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
111 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
112 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
113 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
114 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
115 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
116 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
117 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
118 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
119 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
120 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
122 // Other instructions...
123 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
124 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
125 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
126 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
127 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
128 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
129 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
130 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
131 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
132 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
133 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
134 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
135 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
136 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
137 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
141 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
142 cl::desc("Enable verbose messages in the \"fast\" "
143 "instruction selector"));
145 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
146 cl::desc("Enable abort calls when \"fast\" instruction fails"));
150 cl::desc("use Machine Branch Probability Info"),
151 cl::init(true), cl::Hidden);
155 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
156 cl::desc("Pop up a window to show dags before the first "
157 "dag combine pass"));
159 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
160 cl::desc("Pop up a window to show dags before legalize types"));
162 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
163 cl::desc("Pop up a window to show dags before legalize"));
165 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
166 cl::desc("Pop up a window to show dags before the second "
167 "dag combine pass"));
169 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
170 cl::desc("Pop up a window to show dags before the post legalize types"
171 " dag combine pass"));
173 ViewISelDAGs("view-isel-dags", cl::Hidden,
174 cl::desc("Pop up a window to show isel dags as they are selected"));
176 ViewSchedDAGs("view-sched-dags", cl::Hidden,
177 cl::desc("Pop up a window to show sched dags as they are processed"));
179 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
180 cl::desc("Pop up a window to show SUnit dags after they are processed"));
182 static const bool ViewDAGCombine1 = false,
183 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
184 ViewDAGCombine2 = false,
185 ViewDAGCombineLT = false,
186 ViewISelDAGs = false, ViewSchedDAGs = false,
187 ViewSUnitDAGs = false;
190 //===---------------------------------------------------------------------===//
192 /// RegisterScheduler class - Track the registration of instruction schedulers.
194 //===---------------------------------------------------------------------===//
195 MachinePassRegistry RegisterScheduler::Registry;
197 //===---------------------------------------------------------------------===//
199 /// ISHeuristic command line option for instruction schedulers.
201 //===---------------------------------------------------------------------===//
202 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
203 RegisterPassParser<RegisterScheduler> >
204 ISHeuristic("pre-RA-sched",
205 cl::init(&createDefaultScheduler),
206 cl::desc("Instruction schedulers available (before register"
209 static RegisterScheduler
210 defaultListDAGScheduler("default", "Best scheduler for the target",
211 createDefaultScheduler);
214 //===--------------------------------------------------------------------===//
215 /// createDefaultScheduler - This creates an instruction scheduler appropriate
217 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
218 CodeGenOpt::Level OptLevel) {
219 const TargetLowering &TLI = IS->getTargetLowering();
221 if (OptLevel == CodeGenOpt::None)
222 return createSourceListDAGScheduler(IS, OptLevel);
223 if (TLI.getSchedulingPreference() == Sched::RegPressure)
224 return createBURRListDAGScheduler(IS, OptLevel);
225 if (TLI.getSchedulingPreference() == Sched::Hybrid)
226 return createHybridListDAGScheduler(IS, OptLevel);
227 assert(TLI.getSchedulingPreference() == Sched::ILP &&
228 "Unknown sched type!");
229 return createILPListDAGScheduler(IS, OptLevel);
233 // EmitInstrWithCustomInserter - This method should be implemented by targets
234 // that mark instructions with the 'usesCustomInserter' flag. These
235 // instructions are special in various ways, which require special support to
236 // insert. The specified MachineInstr is created but not inserted into any
237 // basic blocks, and this method is called to expand it into a sequence of
238 // instructions, potentially also creating new basic blocks and control flow.
239 // When new basic blocks are inserted and the edges from MBB to its successors
240 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
243 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
244 MachineBasicBlock *MBB) const {
246 dbgs() << "If a target marks an instruction with "
247 "'usesCustomInserter', it must implement "
248 "TargetLowering::EmitInstrWithCustomInserter!";
254 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
255 SDNode *Node) const {
256 assert(!MI->hasPostISelHook() &&
257 "If a target marks an instruction with 'hasPostISelHook', "
258 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
261 //===----------------------------------------------------------------------===//
262 // SelectionDAGISel code
263 //===----------------------------------------------------------------------===//
265 void SelectionDAGISel::ISelUpdater::anchor() { }
267 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
268 CodeGenOpt::Level OL) :
269 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
270 FuncInfo(new FunctionLoweringInfo(TLI)),
271 CurDAG(new SelectionDAG(tm, OL)),
272 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
276 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
277 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
278 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
279 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
282 SelectionDAGISel::~SelectionDAGISel() {
288 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
289 AU.addRequired<AliasAnalysis>();
290 AU.addPreserved<AliasAnalysis>();
291 AU.addRequired<GCModuleInfo>();
292 AU.addPreserved<GCModuleInfo>();
293 AU.addRequired<TargetLibraryInfo>();
294 if (UseMBPI && OptLevel != CodeGenOpt::None)
295 AU.addRequired<BranchProbabilityInfo>();
296 MachineFunctionPass::getAnalysisUsage(AU);
299 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
300 /// may trap on it. In this case we have to split the edge so that the path
301 /// through the predecessor block that doesn't go to the phi block doesn't
302 /// execute the possibly trapping instruction.
304 /// This is required for correctness, so it must be done at -O0.
306 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
307 // Loop for blocks with phi nodes.
308 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
309 PHINode *PN = dyn_cast<PHINode>(BB->begin());
310 if (PN == 0) continue;
313 // For each block with a PHI node, check to see if any of the input values
314 // are potentially trapping constant expressions. Constant expressions are
315 // the only potentially trapping value that can occur as the argument to a
317 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
318 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
319 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
320 if (CE == 0 || !CE->canTrap()) continue;
322 // The only case we have to worry about is when the edge is critical.
323 // Since this block has a PHI Node, we assume it has multiple input
324 // edges: check to see if the pred has multiple successors.
325 BasicBlock *Pred = PN->getIncomingBlock(i);
326 if (Pred->getTerminator()->getNumSuccessors() == 1)
329 // Okay, we have to split this edge.
330 SplitCriticalEdge(Pred->getTerminator(),
331 GetSuccessorNumber(Pred, BB), SDISel, true);
337 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
338 // Do some sanity-checking on the command-line options.
339 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
340 "-fast-isel-verbose requires -fast-isel");
341 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
342 "-fast-isel-abort requires -fast-isel");
344 const Function &Fn = *mf.getFunction();
345 const TargetInstrInfo &TII = *TM.getInstrInfo();
346 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
349 RegInfo = &MF->getRegInfo();
350 AA = &getAnalysis<AliasAnalysis>();
351 LibInfo = &getAnalysis<TargetLibraryInfo>();
352 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
354 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
356 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
359 FuncInfo->set(Fn, *MF);
361 if (UseMBPI && OptLevel != CodeGenOpt::None)
362 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
366 SDB->init(GFI, *AA, LibInfo);
368 SelectAllBasicBlocks(Fn);
370 // If the first basic block in the function has live ins that need to be
371 // copied into vregs, emit the copies into the top of the block before
372 // emitting the code for the block.
373 MachineBasicBlock *EntryMBB = MF->begin();
374 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
376 DenseMap<unsigned, unsigned> LiveInMap;
377 if (!FuncInfo->ArgDbgValues.empty())
378 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
379 E = RegInfo->livein_end(); LI != E; ++LI)
381 LiveInMap.insert(std::make_pair(LI->first, LI->second));
383 // Insert DBG_VALUE instructions for function arguments to the entry block.
384 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
385 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
386 unsigned Reg = MI->getOperand(0).getReg();
387 if (TargetRegisterInfo::isPhysicalRegister(Reg))
388 EntryMBB->insert(EntryMBB->begin(), MI);
390 MachineInstr *Def = RegInfo->getVRegDef(Reg);
391 MachineBasicBlock::iterator InsertPos = Def;
392 // FIXME: VR def may not be in entry block.
393 Def->getParent()->insert(llvm::next(InsertPos), MI);
396 // If Reg is live-in then update debug info to track its copy in a vreg.
397 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
398 if (LDI != LiveInMap.end()) {
399 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
400 MachineBasicBlock::iterator InsertPos = Def;
401 const MDNode *Variable =
402 MI->getOperand(MI->getNumOperands()-1).getMetadata();
403 unsigned Offset = MI->getOperand(1).getImm();
404 // Def is never a terminator here, so it is ok to increment InsertPos.
405 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
406 TII.get(TargetOpcode::DBG_VALUE))
407 .addReg(LDI->second, RegState::Debug)
408 .addImm(Offset).addMetadata(Variable);
410 // If this vreg is directly copied into an exported register then
411 // that COPY instructions also need DBG_VALUE, if it is the only
412 // user of LDI->second.
413 MachineInstr *CopyUseMI = NULL;
414 for (MachineRegisterInfo::use_iterator
415 UI = RegInfo->use_begin(LDI->second);
416 MachineInstr *UseMI = UI.skipInstruction();) {
417 if (UseMI->isDebugValue()) continue;
418 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
419 CopyUseMI = UseMI; continue;
421 // Otherwise this is another use or second copy use.
422 CopyUseMI = NULL; break;
425 MachineInstr *NewMI =
426 BuildMI(*MF, CopyUseMI->getDebugLoc(),
427 TII.get(TargetOpcode::DBG_VALUE))
428 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
429 .addImm(Offset).addMetadata(Variable);
430 MachineBasicBlock::iterator Pos = CopyUseMI;
431 EntryMBB->insertAfter(Pos, NewMI);
436 // Determine if there are any calls in this machine function.
437 MachineFrameInfo *MFI = MF->getFrameInfo();
438 if (!MFI->hasCalls()) {
439 for (MachineFunction::const_iterator
440 I = MF->begin(), E = MF->end(); I != E; ++I) {
441 const MachineBasicBlock *MBB = I;
442 for (MachineBasicBlock::const_iterator
443 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
444 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
446 if ((MCID.isCall() && !MCID.isReturn()) ||
447 II->isStackAligningInlineAsm()) {
448 MFI->setHasCalls(true);
456 // Determine if there is a call to setjmp in the machine function.
457 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
459 // Replace forward-declared registers with the registers containing
460 // the desired value.
461 MachineRegisterInfo &MRI = MF->getRegInfo();
462 for (DenseMap<unsigned, unsigned>::iterator
463 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
465 unsigned From = I->first;
466 unsigned To = I->second;
467 // If To is also scheduled to be replaced, find what its ultimate
470 DenseMap<unsigned, unsigned>::iterator J =
471 FuncInfo->RegFixups.find(To);
476 MRI.replaceRegWith(From, To);
479 // Release function-specific state. SDB and CurDAG are already cleared
486 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
487 BasicBlock::const_iterator End,
489 // Lower all of the non-terminator instructions. If a call is emitted
490 // as a tail call, cease emitting nodes for this block. Terminators
491 // are handled below.
492 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
495 // Make sure the root of the DAG is up-to-date.
496 CurDAG->setRoot(SDB->getControlRoot());
497 HadTailCall = SDB->HasTailCall;
500 // Final step, emit the lowered DAG as machine code.
504 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
505 SmallPtrSet<SDNode*, 128> VisitedNodes;
506 SmallVector<SDNode*, 128> Worklist;
508 Worklist.push_back(CurDAG->getRoot().getNode());
515 SDNode *N = Worklist.pop_back_val();
517 // If we've already seen this node, ignore it.
518 if (!VisitedNodes.insert(N))
521 // Otherwise, add all chain operands to the worklist.
522 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
523 if (N->getOperand(i).getValueType() == MVT::Other)
524 Worklist.push_back(N->getOperand(i).getNode());
526 // If this is a CopyToReg with a vreg dest, process it.
527 if (N->getOpcode() != ISD::CopyToReg)
530 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
531 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
534 // Ignore non-scalar or non-integer values.
535 SDValue Src = N->getOperand(2);
536 EVT SrcVT = Src.getValueType();
537 if (!SrcVT.isInteger() || SrcVT.isVector())
540 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
541 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
542 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
543 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
544 } while (!Worklist.empty());
547 void SelectionDAGISel::CodeGenAndEmitDAG() {
548 std::string GroupName;
549 if (TimePassesIsEnabled)
550 GroupName = "Instruction Selection and Scheduling";
551 std::string BlockName;
552 int BlockNumber = -1;
555 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
556 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
560 BlockNumber = FuncInfo->MBB->getNumber();
561 BlockName = MF->getFunction()->getName().str() + ":" +
562 FuncInfo->MBB->getBasicBlock()->getName().str();
564 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
565 << " '" << BlockName << "'\n"; CurDAG->dump());
567 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
569 // Run the DAG combiner in pre-legalize mode.
571 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
572 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
575 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
576 << " '" << BlockName << "'\n"; CurDAG->dump());
578 // Second step, hack on the DAG until it only uses operations and types that
579 // the target supports.
580 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
585 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
586 Changed = CurDAG->LegalizeTypes();
589 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
590 << " '" << BlockName << "'\n"; CurDAG->dump());
593 if (ViewDAGCombineLT)
594 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
596 // Run the DAG combiner in post-type-legalize mode.
598 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
599 TimePassesIsEnabled);
600 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
603 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
604 << " '" << BlockName << "'\n"; CurDAG->dump());
608 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
609 Changed = CurDAG->LegalizeVectors();
614 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
615 CurDAG->LegalizeTypes();
618 if (ViewDAGCombineLT)
619 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
621 // Run the DAG combiner in post-type-legalize mode.
623 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
624 TimePassesIsEnabled);
625 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
628 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
629 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
632 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
635 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
639 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
640 << " '" << BlockName << "'\n"; CurDAG->dump());
642 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
644 // Run the DAG combiner in post-legalize mode.
646 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
647 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
650 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
651 << " '" << BlockName << "'\n"; CurDAG->dump());
653 if (OptLevel != CodeGenOpt::None)
654 ComputeLiveOutVRegInfo();
656 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
658 // Third, instruction select all of the operations to machine code, adding the
659 // code to the MachineBasicBlock.
661 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
662 DoInstructionSelection();
665 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
666 << " '" << BlockName << "'\n"; CurDAG->dump());
668 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
670 // Schedule machine code.
671 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
673 NamedRegionTimer T("Instruction Scheduling", GroupName,
674 TimePassesIsEnabled);
675 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
678 if (ViewSUnitDAGs) Scheduler->viewGraph();
680 // Emit machine code to BB. This can change 'BB' to the last block being
682 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
684 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
686 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
687 FuncInfo->InsertPt = Scheduler->InsertPos;
690 // If the block was split, make sure we update any references that are used to
691 // update PHI nodes later on.
692 if (FirstMBB != LastMBB)
693 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
695 // Free the scheduler state.
697 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
698 TimePassesIsEnabled);
702 // Free the SelectionDAG state, now that we're finished with it.
706 void SelectionDAGISel::DoInstructionSelection() {
707 DEBUG(errs() << "===== Instruction selection begins: BB#"
708 << FuncInfo->MBB->getNumber()
709 << " '" << FuncInfo->MBB->getName() << "'\n");
713 // Select target instructions for the DAG.
715 // Number all nodes with a topological order and set DAGSize.
716 DAGSize = CurDAG->AssignTopologicalOrder();
718 // Create a dummy node (which is not added to allnodes), that adds
719 // a reference to the root node, preventing it from being deleted,
720 // and tracking any changes of the root.
721 HandleSDNode Dummy(CurDAG->getRoot());
722 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
725 // The AllNodes list is now topological-sorted. Visit the
726 // nodes by starting at the end of the list (the root of the
727 // graph) and preceding back toward the beginning (the entry
729 while (ISelPosition != CurDAG->allnodes_begin()) {
730 SDNode *Node = --ISelPosition;
731 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
732 // but there are currently some corner cases that it misses. Also, this
733 // makes it theoretically possible to disable the DAGCombiner.
734 if (Node->use_empty())
737 SDNode *ResNode = Select(Node);
739 // FIXME: This is pretty gross. 'Select' should be changed to not return
740 // anything at all and this code should be nuked with a tactical strike.
742 // If node should not be replaced, continue with the next one.
743 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
747 ReplaceUses(Node, ResNode);
749 // If after the replacement this node is not used any more,
750 // remove this dead node.
751 if (Node->use_empty()) { // Don't delete EntryToken, etc.
752 ISelUpdater ISU(ISelPosition);
753 CurDAG->RemoveDeadNode(Node, &ISU);
757 CurDAG->setRoot(Dummy.getValue());
760 DEBUG(errs() << "===== Instruction selection ends:\n");
762 PostprocessISelDAG();
765 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
766 /// do other setup for EH landing-pad blocks.
767 void SelectionDAGISel::PrepareEHLandingPad() {
768 MachineBasicBlock *MBB = FuncInfo->MBB;
770 // Add a label to mark the beginning of the landing pad. Deletion of the
771 // landing pad can thus be detected via the MachineModuleInfo.
772 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
774 // Assign the call site to the landing pad's begin label.
775 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
777 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
778 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
781 // Mark exception register as live in.
782 unsigned Reg = TLI.getExceptionAddressRegister();
783 if (Reg) MBB->addLiveIn(Reg);
785 // Mark exception selector register as live in.
786 Reg = TLI.getExceptionSelectorRegister();
787 if (Reg) MBB->addLiveIn(Reg);
789 // FIXME: Hack around an exception handling flaw (PR1508): the personality
790 // function and list of typeids logically belong to the invoke (or, if you
791 // like, the basic block containing the invoke), and need to be associated
792 // with it in the dwarf exception handling tables. Currently however the
793 // information is provided by an intrinsic (eh.selector) that can be moved
794 // to unexpected places by the optimizers: if the unwind edge is critical,
795 // then breaking it can result in the intrinsics being in the successor of
796 // the landing pad, not the landing pad itself. This results
797 // in exceptions not being caught because no typeids are associated with
798 // the invoke. This may not be the only way things can go wrong, but it
799 // is the only way we try to work around for the moment.
800 const BasicBlock *LLVMBB = MBB->getBasicBlock();
801 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
803 if (Br && Br->isUnconditional()) { // Critical edge?
804 BasicBlock::const_iterator I, E;
805 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
806 if (isa<EHSelectorInst>(I))
810 // No catch info found - try to extract some from the successor.
811 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
815 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
816 /// load into the specified FoldInst. Note that we could have a sequence where
817 /// multiple LLVM IR instructions are folded into the same machineinstr. For
818 /// example we could have:
819 /// A: x = load i32 *P
820 /// B: y = icmp A, 42
823 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
824 /// any other folded instructions) because it is between A and C.
826 /// If we succeed in folding the load into the operation, return true.
828 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
829 const Instruction *FoldInst,
831 // We know that the load has a single use, but don't know what it is. If it
832 // isn't one of the folded instructions, then we can't succeed here. Handle
833 // this by scanning the single-use users of the load until we get to FoldInst.
834 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
836 const Instruction *TheUser = LI->use_back();
837 while (TheUser != FoldInst && // Scan up until we find FoldInst.
838 // Stay in the right block.
839 TheUser->getParent() == FoldInst->getParent() &&
840 --MaxUsers) { // Don't scan too far.
841 // If there are multiple or no uses of this instruction, then bail out.
842 if (!TheUser->hasOneUse())
845 TheUser = TheUser->use_back();
848 // If we didn't find the fold instruction, then we failed to collapse the
850 if (TheUser != FoldInst)
853 // Don't try to fold volatile loads. Target has to deal with alignment
855 if (LI->isVolatile()) return false;
857 // Figure out which vreg this is going into. If there is no assigned vreg yet
858 // then there actually was no reference to it. Perhaps the load is referenced
859 // by a dead instruction.
860 unsigned LoadReg = FastIS->getRegForValue(LI);
864 // Check to see what the uses of this vreg are. If it has no uses, or more
865 // than one use (at the machine instr level) then we can't fold it.
866 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
867 if (RI == RegInfo->reg_end())
870 // See if there is exactly one use of the vreg. If there are multiple uses,
871 // then the instruction got lowered to multiple machine instructions or the
872 // use of the loaded value ended up being multiple operands of the result, in
873 // either case, we can't fold this.
874 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
875 if (PostRI != RegInfo->reg_end())
878 assert(RI.getOperand().isUse() &&
879 "The only use of the vreg must be a use, we haven't emitted the def!");
881 MachineInstr *User = &*RI;
883 // Set the insertion point properly. Folding the load can cause generation of
884 // other random instructions (like sign extends) for addressing modes, make
885 // sure they get inserted in a logical place before the new instruction.
886 FuncInfo->InsertPt = User;
887 FuncInfo->MBB = User->getParent();
889 // Ask the target to try folding the load.
890 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
893 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
894 /// side-effect free and is either dead or folded into a generated instruction.
895 /// Return false if it needs to be emitted.
896 static bool isFoldedOrDeadInstruction(const Instruction *I,
897 FunctionLoweringInfo *FuncInfo) {
898 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
899 !isa<TerminatorInst>(I) && // Terminators aren't folded.
900 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
901 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
902 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
906 // Collect per Instruction statistics for fast-isel misses. Only those
907 // instructions that cause the bail are accounted for. It does not account for
908 // instructions higher in the block. Thus, summing the per instructions stats
909 // will not add up to what is reported by NumFastIselFailures.
910 static void collectFailStats(const Instruction *I) {
911 switch (I->getOpcode()) {
912 default: assert (0 && "<Invalid operator> ");
915 case Instruction::Ret: NumFastIselFailRet++; return;
916 case Instruction::Br: NumFastIselFailBr++; return;
917 case Instruction::Switch: NumFastIselFailSwitch++; return;
918 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
919 case Instruction::Invoke: NumFastIselFailInvoke++; return;
920 case Instruction::Resume: NumFastIselFailResume++; return;
921 case Instruction::Unwind: NumFastIselFailUnwind++; return;
922 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
924 // Standard binary operators...
925 case Instruction::Add: NumFastIselFailAdd++; return;
926 case Instruction::FAdd: NumFastIselFailFAdd++; return;
927 case Instruction::Sub: NumFastIselFailSub++; return;
928 case Instruction::FSub: NumFastIselFailFSub++; return;
929 case Instruction::Mul: NumFastIselFailMul++; return;
930 case Instruction::FMul: NumFastIselFailFMul++; return;
931 case Instruction::UDiv: NumFastIselFailUDiv++; return;
932 case Instruction::SDiv: NumFastIselFailSDiv++; return;
933 case Instruction::FDiv: NumFastIselFailFDiv++; return;
934 case Instruction::URem: NumFastIselFailURem++; return;
935 case Instruction::SRem: NumFastIselFailSRem++; return;
936 case Instruction::FRem: NumFastIselFailFRem++; return;
938 // Logical operators...
939 case Instruction::And: NumFastIselFailAnd++; return;
940 case Instruction::Or: NumFastIselFailOr++; return;
941 case Instruction::Xor: NumFastIselFailXor++; return;
943 // Memory instructions...
944 case Instruction::Alloca: NumFastIselFailAlloca++; return;
945 case Instruction::Load: NumFastIselFailLoad++; return;
946 case Instruction::Store: NumFastIselFailStore++; return;
947 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
948 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
949 case Instruction::Fence: NumFastIselFailFence++; return;
950 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
952 // Convert instructions...
953 case Instruction::Trunc: NumFastIselFailTrunc++; return;
954 case Instruction::ZExt: NumFastIselFailZExt++; return;
955 case Instruction::SExt: NumFastIselFailSExt++; return;
956 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
957 case Instruction::FPExt: NumFastIselFailFPExt++; return;
958 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
959 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
960 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
961 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
962 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
963 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
964 case Instruction::BitCast: NumFastIselFailBitCast++; return;
966 // Other instructions...
967 case Instruction::ICmp: NumFastIselFailICmp++; return;
968 case Instruction::FCmp: NumFastIselFailFCmp++; return;
969 case Instruction::PHI: NumFastIselFailPHI++; return;
970 case Instruction::Select: NumFastIselFailSelect++; return;
971 case Instruction::Call: NumFastIselFailCall++; return;
972 case Instruction::Shl: NumFastIselFailShl++; return;
973 case Instruction::LShr: NumFastIselFailLShr++; return;
974 case Instruction::AShr: NumFastIselFailAShr++; return;
975 case Instruction::VAArg: NumFastIselFailVAArg++; return;
976 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
977 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
978 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
979 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
980 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
981 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
987 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
988 // Initialize the Fast-ISel state, if needed.
989 FastISel *FastIS = 0;
990 if (TM.Options.EnableFastISel)
991 FastIS = TLI.createFastISel(*FuncInfo);
993 // Iterate over all basic blocks in the function.
994 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
995 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
996 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
997 const BasicBlock *LLVMBB = *I;
999 if (OptLevel != CodeGenOpt::None) {
1000 bool AllPredsVisited = true;
1001 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1003 if (!FuncInfo->VisitedBBs.count(*PI)) {
1004 AllPredsVisited = false;
1009 if (AllPredsVisited) {
1010 for (BasicBlock::const_iterator I = LLVMBB->begin();
1011 isa<PHINode>(I); ++I)
1012 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I));
1014 for (BasicBlock::const_iterator I = LLVMBB->begin();
1015 isa<PHINode>(I); ++I)
1016 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I));
1019 FuncInfo->VisitedBBs.insert(LLVMBB);
1022 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1023 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1025 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1026 BasicBlock::const_iterator const End = LLVMBB->end();
1027 BasicBlock::const_iterator BI = End;
1029 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1031 // Setup an EH landing-pad block.
1032 if (FuncInfo->MBB->isLandingPad())
1033 PrepareEHLandingPad();
1035 // Lower any arguments needed in this block if this is the entry block.
1036 if (LLVMBB == &Fn.getEntryBlock())
1037 LowerArguments(LLVMBB);
1039 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1041 FastIS->startNewBlock();
1043 // Emit code for any incoming arguments. This must happen before
1044 // beginning FastISel on the entry block.
1045 if (LLVMBB == &Fn.getEntryBlock()) {
1046 CurDAG->setRoot(SDB->getControlRoot());
1048 CodeGenAndEmitDAG();
1050 // If we inserted any instructions at the beginning, make a note of
1051 // where they are, so we can be sure to emit subsequent instructions
1053 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1054 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1056 FastIS->setLastLocalValue(0);
1059 unsigned NumFastIselRemaining = std::distance(Begin, End);
1060 // Do FastISel on as many instructions as possible.
1061 for (; BI != Begin; --BI) {
1062 const Instruction *Inst = llvm::prior(BI);
1064 // If we no longer require this instruction, skip it.
1065 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1066 --NumFastIselRemaining;
1070 // Bottom-up: reset the insert pos at the top, after any local-value
1072 FastIS->recomputeInsertPt();
1074 // Try to select the instruction with FastISel.
1075 if (FastIS->SelectInstruction(Inst)) {
1076 --NumFastIselRemaining;
1077 ++NumFastIselSuccess;
1078 // If fast isel succeeded, skip over all the folded instructions, and
1079 // then see if there is a load right before the selected instructions.
1080 // Try to fold the load if so.
1081 const Instruction *BeforeInst = Inst;
1082 while (BeforeInst != Begin) {
1083 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1084 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1087 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1088 BeforeInst->hasOneUse() &&
1089 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
1090 // If we succeeded, don't re-select the load.
1091 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1092 --NumFastIselRemaining;
1093 ++NumFastIselSuccess;
1099 if (EnableFastISelVerbose2)
1100 collectFailStats(Inst);
1103 // Then handle certain instructions as single-LLVM-Instruction blocks.
1104 if (isa<CallInst>(Inst)) {
1106 if (EnableFastISelVerbose || EnableFastISelAbort) {
1107 dbgs() << "FastISel missed call: ";
1111 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1112 unsigned &R = FuncInfo->ValueMap[Inst];
1114 R = FuncInfo->CreateRegs(Inst->getType());
1117 bool HadTailCall = false;
1118 SelectBasicBlock(Inst, BI, HadTailCall);
1120 // Recompute NumFastIselRemaining as Selection DAG instruction
1121 // selection may have handled the call, input args, etc.
1122 unsigned RemainingNow = std::distance(Begin, BI);
1123 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1125 // If the call was emitted as a tail call, we're done with the block.
1131 NumFastIselRemaining = RemainingNow;
1135 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1136 // Don't abort, and use a different message for terminator misses.
1137 NumFastIselFailures += NumFastIselRemaining;
1138 if (EnableFastISelVerbose || EnableFastISelAbort) {
1139 dbgs() << "FastISel missed terminator: ";
1143 NumFastIselFailures += NumFastIselRemaining;
1144 if (EnableFastISelVerbose || EnableFastISelAbort) {
1145 dbgs() << "FastISel miss: ";
1148 if (EnableFastISelAbort)
1149 // The "fast" selector couldn't handle something and bailed.
1150 // For the purpose of debugging, just abort.
1151 llvm_unreachable("FastISel didn't select the entire block");
1156 FastIS->recomputeInsertPt();
1162 ++NumFastIselBlocks;
1165 // Run SelectionDAG instruction selection on the remainder of the block
1166 // not handled by FastISel. If FastISel is not run, this is the entire
1169 SelectBasicBlock(Begin, BI, HadTailCall);
1173 FuncInfo->PHINodesToUpdate.clear();
1177 SDB->clearDanglingDebugInfo();
1181 SelectionDAGISel::FinishBasicBlock() {
1183 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1184 << FuncInfo->PHINodesToUpdate.size() << "\n";
1185 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1186 dbgs() << "Node " << i << " : ("
1187 << FuncInfo->PHINodesToUpdate[i].first
1188 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1190 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1191 // PHI nodes in successors.
1192 if (SDB->SwitchCases.empty() &&
1193 SDB->JTCases.empty() &&
1194 SDB->BitTestCases.empty()) {
1195 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1196 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1197 assert(PHI->isPHI() &&
1198 "This is not a machine PHI node that we are updating!");
1199 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1202 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1203 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1208 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1209 // Lower header first, if it wasn't already lowered
1210 if (!SDB->BitTestCases[i].Emitted) {
1211 // Set the current basic block to the mbb we wish to insert the code into
1212 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1213 FuncInfo->InsertPt = FuncInfo->MBB->end();
1215 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1216 CurDAG->setRoot(SDB->getRoot());
1218 CodeGenAndEmitDAG();
1221 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1222 // Set the current basic block to the mbb we wish to insert the code into
1223 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1224 FuncInfo->InsertPt = FuncInfo->MBB->end();
1227 SDB->visitBitTestCase(SDB->BitTestCases[i],
1228 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1229 SDB->BitTestCases[i].Reg,
1230 SDB->BitTestCases[i].Cases[j],
1233 SDB->visitBitTestCase(SDB->BitTestCases[i],
1234 SDB->BitTestCases[i].Default,
1235 SDB->BitTestCases[i].Reg,
1236 SDB->BitTestCases[i].Cases[j],
1240 CurDAG->setRoot(SDB->getRoot());
1242 CodeGenAndEmitDAG();
1246 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1248 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1249 MachineBasicBlock *PHIBB = PHI->getParent();
1250 assert(PHI->isPHI() &&
1251 "This is not a machine PHI node that we are updating!");
1252 // This is "default" BB. We have two jumps to it. From "header" BB and
1253 // from last "case" BB.
1254 if (PHIBB == SDB->BitTestCases[i].Default) {
1255 PHI->addOperand(MachineOperand::
1256 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1258 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1259 PHI->addOperand(MachineOperand::
1260 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1262 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1265 // One of "cases" BB.
1266 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1268 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1269 if (cBB->isSuccessor(PHIBB)) {
1270 PHI->addOperand(MachineOperand::
1271 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1273 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1278 SDB->BitTestCases.clear();
1280 // If the JumpTable record is filled in, then we need to emit a jump table.
1281 // Updating the PHI nodes is tricky in this case, since we need to determine
1282 // whether the PHI is a successor of the range check MBB or the jump table MBB
1283 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1284 // Lower header first, if it wasn't already lowered
1285 if (!SDB->JTCases[i].first.Emitted) {
1286 // Set the current basic block to the mbb we wish to insert the code into
1287 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1288 FuncInfo->InsertPt = FuncInfo->MBB->end();
1290 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1292 CurDAG->setRoot(SDB->getRoot());
1294 CodeGenAndEmitDAG();
1297 // Set the current basic block to the mbb we wish to insert the code into
1298 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1299 FuncInfo->InsertPt = FuncInfo->MBB->end();
1301 SDB->visitJumpTable(SDB->JTCases[i].second);
1302 CurDAG->setRoot(SDB->getRoot());
1304 CodeGenAndEmitDAG();
1307 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1309 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1310 MachineBasicBlock *PHIBB = PHI->getParent();
1311 assert(PHI->isPHI() &&
1312 "This is not a machine PHI node that we are updating!");
1313 // "default" BB. We can go there only from header BB.
1314 if (PHIBB == SDB->JTCases[i].second.Default) {
1316 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1319 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1321 // JT BB. Just iterate over successors here
1322 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1324 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1326 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1330 SDB->JTCases.clear();
1332 // If the switch block involved a branch to one of the actual successors, we
1333 // need to update PHI nodes in that block.
1334 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1335 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1336 assert(PHI->isPHI() &&
1337 "This is not a machine PHI node that we are updating!");
1338 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1340 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1341 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1345 // If we generated any switch lowering information, build and codegen any
1346 // additional DAGs necessary.
1347 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1348 // Set the current basic block to the mbb we wish to insert the code into
1349 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1350 FuncInfo->InsertPt = FuncInfo->MBB->end();
1352 // Determine the unique successors.
1353 SmallVector<MachineBasicBlock *, 2> Succs;
1354 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1355 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1356 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1358 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1359 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1360 CurDAG->setRoot(SDB->getRoot());
1362 CodeGenAndEmitDAG();
1364 // Remember the last block, now that any splitting is done, for use in
1365 // populating PHI nodes in successors.
1366 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1368 // Handle any PHI nodes in successors of this chunk, as if we were coming
1369 // from the original BB before switch expansion. Note that PHI nodes can
1370 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1371 // handle them the right number of times.
1372 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1373 FuncInfo->MBB = Succs[i];
1374 FuncInfo->InsertPt = FuncInfo->MBB->end();
1375 // FuncInfo->MBB may have been removed from the CFG if a branch was
1377 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1378 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1379 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1381 // This value for this PHI node is recorded in PHINodesToUpdate.
1382 for (unsigned pn = 0; ; ++pn) {
1383 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1384 "Didn't find PHI entry!");
1385 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1386 Phi->addOperand(MachineOperand::
1387 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1389 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1397 SDB->SwitchCases.clear();
1401 /// Create the scheduler. If a specific scheduler was specified
1402 /// via the SchedulerRegistry, use it, otherwise select the
1403 /// one preferred by the target.
1405 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1406 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1410 RegisterScheduler::setDefault(Ctor);
1413 return Ctor(this, OptLevel);
1416 //===----------------------------------------------------------------------===//
1417 // Helper functions used by the generated instruction selector.
1418 //===----------------------------------------------------------------------===//
1419 // Calls to these methods are generated by tblgen.
1421 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1422 /// the dag combiner simplified the 255, we still want to match. RHS is the
1423 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1424 /// specified in the .td file (e.g. 255).
1425 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1426 int64_t DesiredMaskS) const {
1427 const APInt &ActualMask = RHS->getAPIntValue();
1428 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1430 // If the actual mask exactly matches, success!
1431 if (ActualMask == DesiredMask)
1434 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1435 if (ActualMask.intersects(~DesiredMask))
1438 // Otherwise, the DAG Combiner may have proven that the value coming in is
1439 // either already zero or is not demanded. Check for known zero input bits.
1440 APInt NeededMask = DesiredMask & ~ActualMask;
1441 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1444 // TODO: check to see if missing bits are just not demanded.
1446 // Otherwise, this pattern doesn't match.
1450 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1451 /// the dag combiner simplified the 255, we still want to match. RHS is the
1452 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1453 /// specified in the .td file (e.g. 255).
1454 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1455 int64_t DesiredMaskS) const {
1456 const APInt &ActualMask = RHS->getAPIntValue();
1457 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1459 // If the actual mask exactly matches, success!
1460 if (ActualMask == DesiredMask)
1463 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1464 if (ActualMask.intersects(~DesiredMask))
1467 // Otherwise, the DAG Combiner may have proven that the value coming in is
1468 // either already zero or is not demanded. Check for known zero input bits.
1469 APInt NeededMask = DesiredMask & ~ActualMask;
1471 APInt KnownZero, KnownOne;
1472 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1474 // If all the missing bits in the or are already known to be set, match!
1475 if ((NeededMask & KnownOne) == NeededMask)
1478 // TODO: check to see if missing bits are just not demanded.
1480 // Otherwise, this pattern doesn't match.
1485 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1486 /// by tblgen. Others should not call it.
1487 void SelectionDAGISel::
1488 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1489 std::vector<SDValue> InOps;
1490 std::swap(InOps, Ops);
1492 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1493 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1494 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1495 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1497 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1498 if (InOps[e-1].getValueType() == MVT::Glue)
1499 --e; // Don't process a glue operand if it is here.
1502 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1503 if (!InlineAsm::isMemKind(Flags)) {
1504 // Just skip over this operand, copying the operands verbatim.
1505 Ops.insert(Ops.end(), InOps.begin()+i,
1506 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1507 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1509 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1510 "Memory operand with multiple values?");
1511 // Otherwise, this is a memory operand. Ask the target to select it.
1512 std::vector<SDValue> SelOps;
1513 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1514 report_fatal_error("Could not match memory address. Inline asm"
1517 // Add this to the output node.
1519 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1520 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1521 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1526 // Add the glue input back if present.
1527 if (e != InOps.size())
1528 Ops.push_back(InOps.back());
1531 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1534 static SDNode *findGlueUse(SDNode *N) {
1535 unsigned FlagResNo = N->getNumValues()-1;
1536 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1537 SDUse &Use = I.getUse();
1538 if (Use.getResNo() == FlagResNo)
1539 return Use.getUser();
1544 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1545 /// This function recursively traverses up the operand chain, ignoring
1547 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1548 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1549 bool IgnoreChains) {
1550 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1551 // greater than all of its (recursive) operands. If we scan to a point where
1552 // 'use' is smaller than the node we're scanning for, then we know we will
1555 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1556 // happen because we scan down to newly selected nodes in the case of glue
1558 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1561 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1562 // won't fail if we scan it again.
1563 if (!Visited.insert(Use))
1566 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1567 // Ignore chain uses, they are validated by HandleMergeInputChains.
1568 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1571 SDNode *N = Use->getOperand(i).getNode();
1573 if (Use == ImmedUse || Use == Root)
1574 continue; // We are not looking for immediate use.
1579 // Traverse up the operand chain.
1580 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1586 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1587 /// operand node N of U during instruction selection that starts at Root.
1588 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1589 SDNode *Root) const {
1590 if (OptLevel == CodeGenOpt::None) return false;
1591 return N.hasOneUse();
1594 /// IsLegalToFold - Returns true if the specific operand node N of
1595 /// U can be folded during instruction selection that starts at Root.
1596 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1597 CodeGenOpt::Level OptLevel,
1598 bool IgnoreChains) {
1599 if (OptLevel == CodeGenOpt::None) return false;
1601 // If Root use can somehow reach N through a path that that doesn't contain
1602 // U then folding N would create a cycle. e.g. In the following
1603 // diagram, Root can reach N through X. If N is folded into into Root, then
1604 // X is both a predecessor and a successor of U.
1615 // * indicates nodes to be folded together.
1617 // If Root produces glue, then it gets (even more) interesting. Since it
1618 // will be "glued" together with its glue use in the scheduler, we need to
1619 // check if it might reach N.
1638 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1639 // (call it Fold), then X is a predecessor of GU and a successor of
1640 // Fold. But since Fold and GU are glued together, this will create
1641 // a cycle in the scheduling graph.
1643 // If the node has glue, walk down the graph to the "lowest" node in the
1645 EVT VT = Root->getValueType(Root->getNumValues()-1);
1646 while (VT == MVT::Glue) {
1647 SDNode *GU = findGlueUse(Root);
1651 VT = Root->getValueType(Root->getNumValues()-1);
1653 // If our query node has a glue result with a use, we've walked up it. If
1654 // the user (which has already been selected) has a chain or indirectly uses
1655 // the chain, our WalkChainUsers predicate will not consider it. Because of
1656 // this, we cannot ignore chains in this predicate.
1657 IgnoreChains = false;
1661 SmallPtrSet<SDNode*, 16> Visited;
1662 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1665 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1666 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1667 SelectInlineAsmMemoryOperands(Ops);
1669 std::vector<EVT> VTs;
1670 VTs.push_back(MVT::Other);
1671 VTs.push_back(MVT::Glue);
1672 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1673 VTs, &Ops[0], Ops.size());
1675 return New.getNode();
1678 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1679 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1682 /// GetVBR - decode a vbr encoding whose top bit is set.
1683 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1684 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1685 assert(Val >= 128 && "Not a VBR");
1686 Val &= 127; // Remove first vbr bit.
1691 NextBits = MatcherTable[Idx++];
1692 Val |= (NextBits&127) << Shift;
1694 } while (NextBits & 128);
1700 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1701 /// interior glue and chain results to use the new glue and chain results.
1702 void SelectionDAGISel::
1703 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1704 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1706 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1707 bool isMorphNodeTo) {
1708 SmallVector<SDNode*, 4> NowDeadNodes;
1710 ISelUpdater ISU(ISelPosition);
1712 // Now that all the normal results are replaced, we replace the chain and
1713 // glue results if present.
1714 if (!ChainNodesMatched.empty()) {
1715 assert(InputChain.getNode() != 0 &&
1716 "Matched input chains but didn't produce a chain");
1717 // Loop over all of the nodes we matched that produced a chain result.
1718 // Replace all the chain results with the final chain we ended up with.
1719 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1720 SDNode *ChainNode = ChainNodesMatched[i];
1722 // If this node was already deleted, don't look at it.
1723 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1726 // Don't replace the results of the root node if we're doing a
1728 if (ChainNode == NodeToMatch && isMorphNodeTo)
1731 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1732 if (ChainVal.getValueType() == MVT::Glue)
1733 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1734 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1735 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1737 // If the node became dead and we haven't already seen it, delete it.
1738 if (ChainNode->use_empty() &&
1739 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1740 NowDeadNodes.push_back(ChainNode);
1744 // If the result produces glue, update any glue results in the matched
1745 // pattern with the glue result.
1746 if (InputGlue.getNode() != 0) {
1747 // Handle any interior nodes explicitly marked.
1748 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1749 SDNode *FRN = GlueResultNodesMatched[i];
1751 // If this node was already deleted, don't look at it.
1752 if (FRN->getOpcode() == ISD::DELETED_NODE)
1755 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1756 "Doesn't have a glue result");
1757 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1760 // If the node became dead and we haven't already seen it, delete it.
1761 if (FRN->use_empty() &&
1762 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1763 NowDeadNodes.push_back(FRN);
1767 if (!NowDeadNodes.empty())
1768 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1770 DEBUG(errs() << "ISEL: Match complete!\n");
1776 CR_LeadsToInteriorNode
1779 /// WalkChainUsers - Walk down the users of the specified chained node that is
1780 /// part of the pattern we're matching, looking at all of the users we find.
1781 /// This determines whether something is an interior node, whether we have a
1782 /// non-pattern node in between two pattern nodes (which prevent folding because
1783 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1784 /// between pattern nodes (in which case the TF becomes part of the pattern).
1786 /// The walk we do here is guaranteed to be small because we quickly get down to
1787 /// already selected nodes "below" us.
1789 WalkChainUsers(SDNode *ChainedNode,
1790 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1791 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1792 ChainResult Result = CR_Simple;
1794 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1795 E = ChainedNode->use_end(); UI != E; ++UI) {
1796 // Make sure the use is of the chain, not some other value we produce.
1797 if (UI.getUse().getValueType() != MVT::Other) continue;
1801 // If we see an already-selected machine node, then we've gone beyond the
1802 // pattern that we're selecting down into the already selected chunk of the
1804 if (User->isMachineOpcode() ||
1805 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1808 if (User->getOpcode() == ISD::CopyToReg ||
1809 User->getOpcode() == ISD::CopyFromReg ||
1810 User->getOpcode() == ISD::INLINEASM ||
1811 User->getOpcode() == ISD::EH_LABEL) {
1812 // If their node ID got reset to -1 then they've already been selected.
1813 // Treat them like a MachineOpcode.
1814 if (User->getNodeId() == -1)
1818 // If we have a TokenFactor, we handle it specially.
1819 if (User->getOpcode() != ISD::TokenFactor) {
1820 // If the node isn't a token factor and isn't part of our pattern, then it
1821 // must be a random chained node in between two nodes we're selecting.
1822 // This happens when we have something like:
1827 // Because we structurally match the load/store as a read/modify/write,
1828 // but the call is chained between them. We cannot fold in this case
1829 // because it would induce a cycle in the graph.
1830 if (!std::count(ChainedNodesInPattern.begin(),
1831 ChainedNodesInPattern.end(), User))
1832 return CR_InducesCycle;
1834 // Otherwise we found a node that is part of our pattern. For example in:
1838 // This would happen when we're scanning down from the load and see the
1839 // store as a user. Record that there is a use of ChainedNode that is
1840 // part of the pattern and keep scanning uses.
1841 Result = CR_LeadsToInteriorNode;
1842 InteriorChainedNodes.push_back(User);
1846 // If we found a TokenFactor, there are two cases to consider: first if the
1847 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1848 // uses of the TF are in our pattern) we just want to ignore it. Second,
1849 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1855 // | \ DAG's like cheese
1858 // [TokenFactor] [Op]
1865 // In this case, the TokenFactor becomes part of our match and we rewrite it
1866 // as a new TokenFactor.
1868 // To distinguish these two cases, do a recursive walk down the uses.
1869 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1871 // If the uses of the TokenFactor are just already-selected nodes, ignore
1872 // it, it is "below" our pattern.
1874 case CR_InducesCycle:
1875 // If the uses of the TokenFactor lead to nodes that are not part of our
1876 // pattern that are not selected, folding would turn this into a cycle,
1878 return CR_InducesCycle;
1879 case CR_LeadsToInteriorNode:
1880 break; // Otherwise, keep processing.
1883 // Okay, we know we're in the interesting interior case. The TokenFactor
1884 // is now going to be considered part of the pattern so that we rewrite its
1885 // uses (it may have uses that are not part of the pattern) with the
1886 // ultimate chain result of the generated code. We will also add its chain
1887 // inputs as inputs to the ultimate TokenFactor we create.
1888 Result = CR_LeadsToInteriorNode;
1889 ChainedNodesInPattern.push_back(User);
1890 InteriorChainedNodes.push_back(User);
1897 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1898 /// operation for when the pattern matched at least one node with a chains. The
1899 /// input vector contains a list of all of the chained nodes that we match. We
1900 /// must determine if this is a valid thing to cover (i.e. matching it won't
1901 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1902 /// be used as the input node chain for the generated nodes.
1904 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1905 SelectionDAG *CurDAG) {
1906 // Walk all of the chained nodes we've matched, recursively scanning down the
1907 // users of the chain result. This adds any TokenFactor nodes that are caught
1908 // in between chained nodes to the chained and interior nodes list.
1909 SmallVector<SDNode*, 3> InteriorChainedNodes;
1910 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1911 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1912 InteriorChainedNodes) == CR_InducesCycle)
1913 return SDValue(); // Would induce a cycle.
1916 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1917 // that we are interested in. Form our input TokenFactor node.
1918 SmallVector<SDValue, 3> InputChains;
1919 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1920 // Add the input chain of this node to the InputChains list (which will be
1921 // the operands of the generated TokenFactor) if it's not an interior node.
1922 SDNode *N = ChainNodesMatched[i];
1923 if (N->getOpcode() != ISD::TokenFactor) {
1924 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1927 // Otherwise, add the input chain.
1928 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1929 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1930 InputChains.push_back(InChain);
1934 // If we have a token factor, we want to add all inputs of the token factor
1935 // that are not part of the pattern we're matching.
1936 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1937 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1938 N->getOperand(op).getNode()))
1939 InputChains.push_back(N->getOperand(op));
1944 if (InputChains.size() == 1)
1945 return InputChains[0];
1946 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1947 MVT::Other, &InputChains[0], InputChains.size());
1950 /// MorphNode - Handle morphing a node in place for the selector.
1951 SDNode *SelectionDAGISel::
1952 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1953 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1954 // It is possible we're using MorphNodeTo to replace a node with no
1955 // normal results with one that has a normal result (or we could be
1956 // adding a chain) and the input could have glue and chains as well.
1957 // In this case we need to shift the operands down.
1958 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1959 // than the old isel though.
1960 int OldGlueResultNo = -1, OldChainResultNo = -1;
1962 unsigned NTMNumResults = Node->getNumValues();
1963 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1964 OldGlueResultNo = NTMNumResults-1;
1965 if (NTMNumResults != 1 &&
1966 Node->getValueType(NTMNumResults-2) == MVT::Other)
1967 OldChainResultNo = NTMNumResults-2;
1968 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1969 OldChainResultNo = NTMNumResults-1;
1971 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1972 // that this deletes operands of the old node that become dead.
1973 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1975 // MorphNodeTo can operate in two ways: if an existing node with the
1976 // specified operands exists, it can just return it. Otherwise, it
1977 // updates the node in place to have the requested operands.
1979 // If we updated the node in place, reset the node ID. To the isel,
1980 // this should be just like a newly allocated machine node.
1984 unsigned ResNumResults = Res->getNumValues();
1985 // Move the glue if needed.
1986 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1987 (unsigned)OldGlueResultNo != ResNumResults-1)
1988 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1989 SDValue(Res, ResNumResults-1));
1991 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1994 // Move the chain reference if needed.
1995 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1996 (unsigned)OldChainResultNo != ResNumResults-1)
1997 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1998 SDValue(Res, ResNumResults-1));
2000 // Otherwise, no replacement happened because the node already exists. Replace
2001 // Uses of the old node with the new one.
2003 CurDAG->ReplaceAllUsesWith(Node, Res);
2008 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2009 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2010 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2012 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2013 // Accept if it is exactly the same as a previously recorded node.
2014 unsigned RecNo = MatcherTable[MatcherIndex++];
2015 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2016 return N == RecordedNodes[RecNo].first;
2019 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2020 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2021 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2022 SelectionDAGISel &SDISel) {
2023 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2026 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2027 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2028 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2029 SelectionDAGISel &SDISel, SDNode *N) {
2030 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2033 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2034 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2036 uint16_t Opc = MatcherTable[MatcherIndex++];
2037 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2038 return N->getOpcode() == Opc;
2041 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2042 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2043 SDValue N, const TargetLowering &TLI) {
2044 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2045 if (N.getValueType() == VT) return true;
2047 // Handle the case when VT is iPTR.
2048 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
2051 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2052 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2053 SDValue N, const TargetLowering &TLI,
2055 if (ChildNo >= N.getNumOperands())
2056 return false; // Match fails if out of range child #.
2057 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2061 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2062 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2064 return cast<CondCodeSDNode>(N)->get() ==
2065 (ISD::CondCode)MatcherTable[MatcherIndex++];
2068 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2069 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2070 SDValue N, const TargetLowering &TLI) {
2071 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2072 if (cast<VTSDNode>(N)->getVT() == VT)
2075 // Handle the case when VT is iPTR.
2076 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2079 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2080 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2082 int64_t Val = MatcherTable[MatcherIndex++];
2084 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2086 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2087 return C != 0 && C->getSExtValue() == Val;
2090 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2091 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2092 SDValue N, SelectionDAGISel &SDISel) {
2093 int64_t Val = MatcherTable[MatcherIndex++];
2095 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2097 if (N->getOpcode() != ISD::AND) return false;
2099 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2100 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2103 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2104 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2105 SDValue N, SelectionDAGISel &SDISel) {
2106 int64_t Val = MatcherTable[MatcherIndex++];
2108 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2110 if (N->getOpcode() != ISD::OR) return false;
2112 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2113 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2116 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2117 /// scope, evaluate the current node. If the current predicate is known to
2118 /// fail, set Result=true and return anything. If the current predicate is
2119 /// known to pass, set Result=false and return the MatcherIndex to continue
2120 /// with. If the current predicate is unknown, set Result=false and return the
2121 /// MatcherIndex to continue with.
2122 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2123 unsigned Index, SDValue N,
2124 bool &Result, SelectionDAGISel &SDISel,
2125 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2126 switch (Table[Index++]) {
2129 return Index-1; // Could not evaluate this predicate.
2130 case SelectionDAGISel::OPC_CheckSame:
2131 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2133 case SelectionDAGISel::OPC_CheckPatternPredicate:
2134 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2136 case SelectionDAGISel::OPC_CheckPredicate:
2137 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2139 case SelectionDAGISel::OPC_CheckOpcode:
2140 Result = !::CheckOpcode(Table, Index, N.getNode());
2142 case SelectionDAGISel::OPC_CheckType:
2143 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2145 case SelectionDAGISel::OPC_CheckChild0Type:
2146 case SelectionDAGISel::OPC_CheckChild1Type:
2147 case SelectionDAGISel::OPC_CheckChild2Type:
2148 case SelectionDAGISel::OPC_CheckChild3Type:
2149 case SelectionDAGISel::OPC_CheckChild4Type:
2150 case SelectionDAGISel::OPC_CheckChild5Type:
2151 case SelectionDAGISel::OPC_CheckChild6Type:
2152 case SelectionDAGISel::OPC_CheckChild7Type:
2153 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2154 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2156 case SelectionDAGISel::OPC_CheckCondCode:
2157 Result = !::CheckCondCode(Table, Index, N);
2159 case SelectionDAGISel::OPC_CheckValueType:
2160 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2162 case SelectionDAGISel::OPC_CheckInteger:
2163 Result = !::CheckInteger(Table, Index, N);
2165 case SelectionDAGISel::OPC_CheckAndImm:
2166 Result = !::CheckAndImm(Table, Index, N, SDISel);
2168 case SelectionDAGISel::OPC_CheckOrImm:
2169 Result = !::CheckOrImm(Table, Index, N, SDISel);
2177 /// FailIndex - If this match fails, this is the index to continue with.
2180 /// NodeStack - The node stack when the scope was formed.
2181 SmallVector<SDValue, 4> NodeStack;
2183 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2184 unsigned NumRecordedNodes;
2186 /// NumMatchedMemRefs - The number of matched memref entries.
2187 unsigned NumMatchedMemRefs;
2189 /// InputChain/InputGlue - The current chain/glue
2190 SDValue InputChain, InputGlue;
2192 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2193 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2198 SDNode *SelectionDAGISel::
2199 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2200 unsigned TableSize) {
2201 // FIXME: Should these even be selected? Handle these cases in the caller?
2202 switch (NodeToMatch->getOpcode()) {
2205 case ISD::EntryToken: // These nodes remain the same.
2206 case ISD::BasicBlock:
2208 //case ISD::VALUETYPE:
2209 //case ISD::CONDCODE:
2210 case ISD::HANDLENODE:
2211 case ISD::MDNODE_SDNODE:
2212 case ISD::TargetConstant:
2213 case ISD::TargetConstantFP:
2214 case ISD::TargetConstantPool:
2215 case ISD::TargetFrameIndex:
2216 case ISD::TargetExternalSymbol:
2217 case ISD::TargetBlockAddress:
2218 case ISD::TargetJumpTable:
2219 case ISD::TargetGlobalTLSAddress:
2220 case ISD::TargetGlobalAddress:
2221 case ISD::TokenFactor:
2222 case ISD::CopyFromReg:
2223 case ISD::CopyToReg:
2225 NodeToMatch->setNodeId(-1); // Mark selected.
2227 case ISD::AssertSext:
2228 case ISD::AssertZext:
2229 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2230 NodeToMatch->getOperand(0));
2232 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2233 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2236 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2238 // Set up the node stack with NodeToMatch as the only node on the stack.
2239 SmallVector<SDValue, 8> NodeStack;
2240 SDValue N = SDValue(NodeToMatch, 0);
2241 NodeStack.push_back(N);
2243 // MatchScopes - Scopes used when matching, if a match failure happens, this
2244 // indicates where to continue checking.
2245 SmallVector<MatchScope, 8> MatchScopes;
2247 // RecordedNodes - This is the set of nodes that have been recorded by the
2248 // state machine. The second value is the parent of the node, or null if the
2249 // root is recorded.
2250 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2252 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2254 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2256 // These are the current input chain and glue for use when generating nodes.
2257 // Various Emit operations change these. For example, emitting a copytoreg
2258 // uses and updates these.
2259 SDValue InputChain, InputGlue;
2261 // ChainNodesMatched - If a pattern matches nodes that have input/output
2262 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2263 // which ones they are. The result is captured into this list so that we can
2264 // update the chain results when the pattern is complete.
2265 SmallVector<SDNode*, 3> ChainNodesMatched;
2266 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2268 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2269 NodeToMatch->dump(CurDAG);
2272 // Determine where to start the interpreter. Normally we start at opcode #0,
2273 // but if the state machine starts with an OPC_SwitchOpcode, then we
2274 // accelerate the first lookup (which is guaranteed to be hot) with the
2275 // OpcodeOffset table.
2276 unsigned MatcherIndex = 0;
2278 if (!OpcodeOffset.empty()) {
2279 // Already computed the OpcodeOffset table, just index into it.
2280 if (N.getOpcode() < OpcodeOffset.size())
2281 MatcherIndex = OpcodeOffset[N.getOpcode()];
2282 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2284 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2285 // Otherwise, the table isn't computed, but the state machine does start
2286 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2287 // is the first time we're selecting an instruction.
2290 // Get the size of this case.
2291 unsigned CaseSize = MatcherTable[Idx++];
2293 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2294 if (CaseSize == 0) break;
2296 // Get the opcode, add the index to the table.
2297 uint16_t Opc = MatcherTable[Idx++];
2298 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2299 if (Opc >= OpcodeOffset.size())
2300 OpcodeOffset.resize((Opc+1)*2);
2301 OpcodeOffset[Opc] = Idx;
2305 // Okay, do the lookup for the first opcode.
2306 if (N.getOpcode() < OpcodeOffset.size())
2307 MatcherIndex = OpcodeOffset[N.getOpcode()];
2311 assert(MatcherIndex < TableSize && "Invalid index");
2313 unsigned CurrentOpcodeIndex = MatcherIndex;
2315 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2318 // Okay, the semantics of this operation are that we should push a scope
2319 // then evaluate the first child. However, pushing a scope only to have
2320 // the first check fail (which then pops it) is inefficient. If we can
2321 // determine immediately that the first check (or first several) will
2322 // immediately fail, don't even bother pushing a scope for them.
2326 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2327 if (NumToSkip & 128)
2328 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2329 // Found the end of the scope with no match.
2330 if (NumToSkip == 0) {
2335 FailIndex = MatcherIndex+NumToSkip;
2337 unsigned MatcherIndexOfPredicate = MatcherIndex;
2338 (void)MatcherIndexOfPredicate; // silence warning.
2340 // If we can't evaluate this predicate without pushing a scope (e.g. if
2341 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2342 // push the scope and evaluate the full predicate chain.
2344 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2345 Result, *this, RecordedNodes);
2349 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2350 << "index " << MatcherIndexOfPredicate
2351 << ", continuing at " << FailIndex << "\n");
2352 ++NumDAGIselRetries;
2354 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2355 // move to the next case.
2356 MatcherIndex = FailIndex;
2359 // If the whole scope failed to match, bail.
2360 if (FailIndex == 0) break;
2362 // Push a MatchScope which indicates where to go if the first child fails
2364 MatchScope NewEntry;
2365 NewEntry.FailIndex = FailIndex;
2366 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2367 NewEntry.NumRecordedNodes = RecordedNodes.size();
2368 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2369 NewEntry.InputChain = InputChain;
2370 NewEntry.InputGlue = InputGlue;
2371 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2372 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2373 MatchScopes.push_back(NewEntry);
2376 case OPC_RecordNode: {
2377 // Remember this node, it may end up being an operand in the pattern.
2379 if (NodeStack.size() > 1)
2380 Parent = NodeStack[NodeStack.size()-2].getNode();
2381 RecordedNodes.push_back(std::make_pair(N, Parent));
2385 case OPC_RecordChild0: case OPC_RecordChild1:
2386 case OPC_RecordChild2: case OPC_RecordChild3:
2387 case OPC_RecordChild4: case OPC_RecordChild5:
2388 case OPC_RecordChild6: case OPC_RecordChild7: {
2389 unsigned ChildNo = Opcode-OPC_RecordChild0;
2390 if (ChildNo >= N.getNumOperands())
2391 break; // Match fails if out of range child #.
2393 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2397 case OPC_RecordMemRef:
2398 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2401 case OPC_CaptureGlueInput:
2402 // If the current node has an input glue, capture it in InputGlue.
2403 if (N->getNumOperands() != 0 &&
2404 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2405 InputGlue = N->getOperand(N->getNumOperands()-1);
2408 case OPC_MoveChild: {
2409 unsigned ChildNo = MatcherTable[MatcherIndex++];
2410 if (ChildNo >= N.getNumOperands())
2411 break; // Match fails if out of range child #.
2412 N = N.getOperand(ChildNo);
2413 NodeStack.push_back(N);
2417 case OPC_MoveParent:
2418 // Pop the current node off the NodeStack.
2419 NodeStack.pop_back();
2420 assert(!NodeStack.empty() && "Node stack imbalance!");
2421 N = NodeStack.back();
2425 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2427 case OPC_CheckPatternPredicate:
2428 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2430 case OPC_CheckPredicate:
2431 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2435 case OPC_CheckComplexPat: {
2436 unsigned CPNum = MatcherTable[MatcherIndex++];
2437 unsigned RecNo = MatcherTable[MatcherIndex++];
2438 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2439 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2440 RecordedNodes[RecNo].first, CPNum,
2445 case OPC_CheckOpcode:
2446 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2450 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2453 case OPC_SwitchOpcode: {
2454 unsigned CurNodeOpcode = N.getOpcode();
2455 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2458 // Get the size of this case.
2459 CaseSize = MatcherTable[MatcherIndex++];
2461 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2462 if (CaseSize == 0) break;
2464 uint16_t Opc = MatcherTable[MatcherIndex++];
2465 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2467 // If the opcode matches, then we will execute this case.
2468 if (CurNodeOpcode == Opc)
2471 // Otherwise, skip over this case.
2472 MatcherIndex += CaseSize;
2475 // If no cases matched, bail out.
2476 if (CaseSize == 0) break;
2478 // Otherwise, execute the case we found.
2479 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2480 << " to " << MatcherIndex << "\n");
2484 case OPC_SwitchType: {
2485 MVT CurNodeVT = N.getValueType().getSimpleVT();
2486 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2489 // Get the size of this case.
2490 CaseSize = MatcherTable[MatcherIndex++];
2492 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2493 if (CaseSize == 0) break;
2495 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2496 if (CaseVT == MVT::iPTR)
2497 CaseVT = TLI.getPointerTy();
2499 // If the VT matches, then we will execute this case.
2500 if (CurNodeVT == CaseVT)
2503 // Otherwise, skip over this case.
2504 MatcherIndex += CaseSize;
2507 // If no cases matched, bail out.
2508 if (CaseSize == 0) break;
2510 // Otherwise, execute the case we found.
2511 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2512 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2515 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2516 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2517 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2518 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2519 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2520 Opcode-OPC_CheckChild0Type))
2523 case OPC_CheckCondCode:
2524 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2526 case OPC_CheckValueType:
2527 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2529 case OPC_CheckInteger:
2530 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2532 case OPC_CheckAndImm:
2533 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2535 case OPC_CheckOrImm:
2536 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2539 case OPC_CheckFoldableChainNode: {
2540 assert(NodeStack.size() != 1 && "No parent node");
2541 // Verify that all intermediate nodes between the root and this one have
2543 bool HasMultipleUses = false;
2544 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2545 if (!NodeStack[i].hasOneUse()) {
2546 HasMultipleUses = true;
2549 if (HasMultipleUses) break;
2551 // Check to see that the target thinks this is profitable to fold and that
2552 // we can fold it without inducing cycles in the graph.
2553 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2555 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2556 NodeToMatch, OptLevel,
2557 true/*We validate our own chains*/))
2562 case OPC_EmitInteger: {
2563 MVT::SimpleValueType VT =
2564 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2565 int64_t Val = MatcherTable[MatcherIndex++];
2567 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2568 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2569 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2572 case OPC_EmitRegister: {
2573 MVT::SimpleValueType VT =
2574 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2575 unsigned RegNo = MatcherTable[MatcherIndex++];
2576 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2577 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2580 case OPC_EmitRegister2: {
2581 // For targets w/ more than 256 register names, the register enum
2582 // values are stored in two bytes in the matcher table (just like
2584 MVT::SimpleValueType VT =
2585 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2586 unsigned RegNo = MatcherTable[MatcherIndex++];
2587 RegNo |= MatcherTable[MatcherIndex++] << 8;
2588 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2589 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2593 case OPC_EmitConvertToTarget: {
2594 // Convert from IMM/FPIMM to target version.
2595 unsigned RecNo = MatcherTable[MatcherIndex++];
2596 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2597 SDValue Imm = RecordedNodes[RecNo].first;
2599 if (Imm->getOpcode() == ISD::Constant) {
2600 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2601 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2602 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2603 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2604 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2607 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2611 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2612 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2613 // These are space-optimized forms of OPC_EmitMergeInputChains.
2614 assert(InputChain.getNode() == 0 &&
2615 "EmitMergeInputChains should be the first chain producing node");
2616 assert(ChainNodesMatched.empty() &&
2617 "Should only have one EmitMergeInputChains per match");
2619 // Read all of the chained nodes.
2620 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2621 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2622 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2624 // FIXME: What if other value results of the node have uses not matched
2626 if (ChainNodesMatched.back() != NodeToMatch &&
2627 !RecordedNodes[RecNo].first.hasOneUse()) {
2628 ChainNodesMatched.clear();
2632 // Merge the input chains if they are not intra-pattern references.
2633 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2635 if (InputChain.getNode() == 0)
2636 break; // Failed to merge.
2640 case OPC_EmitMergeInputChains: {
2641 assert(InputChain.getNode() == 0 &&
2642 "EmitMergeInputChains should be the first chain producing node");
2643 // This node gets a list of nodes we matched in the input that have
2644 // chains. We want to token factor all of the input chains to these nodes
2645 // together. However, if any of the input chains is actually one of the
2646 // nodes matched in this pattern, then we have an intra-match reference.
2647 // Ignore these because the newly token factored chain should not refer to
2649 unsigned NumChains = MatcherTable[MatcherIndex++];
2650 assert(NumChains != 0 && "Can't TF zero chains");
2652 assert(ChainNodesMatched.empty() &&
2653 "Should only have one EmitMergeInputChains per match");
2655 // Read all of the chained nodes.
2656 for (unsigned i = 0; i != NumChains; ++i) {
2657 unsigned RecNo = MatcherTable[MatcherIndex++];
2658 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2659 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2661 // FIXME: What if other value results of the node have uses not matched
2663 if (ChainNodesMatched.back() != NodeToMatch &&
2664 !RecordedNodes[RecNo].first.hasOneUse()) {
2665 ChainNodesMatched.clear();
2670 // If the inner loop broke out, the match fails.
2671 if (ChainNodesMatched.empty())
2674 // Merge the input chains if they are not intra-pattern references.
2675 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2677 if (InputChain.getNode() == 0)
2678 break; // Failed to merge.
2683 case OPC_EmitCopyToReg: {
2684 unsigned RecNo = MatcherTable[MatcherIndex++];
2685 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2686 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2688 if (InputChain.getNode() == 0)
2689 InputChain = CurDAG->getEntryNode();
2691 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2692 DestPhysReg, RecordedNodes[RecNo].first,
2695 InputGlue = InputChain.getValue(1);
2699 case OPC_EmitNodeXForm: {
2700 unsigned XFormNo = MatcherTable[MatcherIndex++];
2701 unsigned RecNo = MatcherTable[MatcherIndex++];
2702 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2703 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2704 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2709 case OPC_MorphNodeTo: {
2710 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2711 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2712 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2713 // Get the result VT list.
2714 unsigned NumVTs = MatcherTable[MatcherIndex++];
2715 SmallVector<EVT, 4> VTs;
2716 for (unsigned i = 0; i != NumVTs; ++i) {
2717 MVT::SimpleValueType VT =
2718 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2719 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2723 if (EmitNodeInfo & OPFL_Chain)
2724 VTs.push_back(MVT::Other);
2725 if (EmitNodeInfo & OPFL_GlueOutput)
2726 VTs.push_back(MVT::Glue);
2728 // This is hot code, so optimize the two most common cases of 1 and 2
2731 if (VTs.size() == 1)
2732 VTList = CurDAG->getVTList(VTs[0]);
2733 else if (VTs.size() == 2)
2734 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2736 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2738 // Get the operand list.
2739 unsigned NumOps = MatcherTable[MatcherIndex++];
2740 SmallVector<SDValue, 8> Ops;
2741 for (unsigned i = 0; i != NumOps; ++i) {
2742 unsigned RecNo = MatcherTable[MatcherIndex++];
2744 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2746 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2747 Ops.push_back(RecordedNodes[RecNo].first);
2750 // If there are variadic operands to add, handle them now.
2751 if (EmitNodeInfo & OPFL_VariadicInfo) {
2752 // Determine the start index to copy from.
2753 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2754 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2755 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2756 "Invalid variadic node");
2757 // Copy all of the variadic operands, not including a potential glue
2759 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2761 SDValue V = NodeToMatch->getOperand(i);
2762 if (V.getValueType() == MVT::Glue) break;
2767 // If this has chain/glue inputs, add them.
2768 if (EmitNodeInfo & OPFL_Chain)
2769 Ops.push_back(InputChain);
2770 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2771 Ops.push_back(InputGlue);
2775 if (Opcode != OPC_MorphNodeTo) {
2776 // If this is a normal EmitNode command, just create the new node and
2777 // add the results to the RecordedNodes list.
2778 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2779 VTList, Ops.data(), Ops.size());
2781 // Add all the non-glue/non-chain results to the RecordedNodes list.
2782 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2783 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2784 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2789 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2793 // If the node had chain/glue results, update our notion of the current
2795 if (EmitNodeInfo & OPFL_GlueOutput) {
2796 InputGlue = SDValue(Res, VTs.size()-1);
2797 if (EmitNodeInfo & OPFL_Chain)
2798 InputChain = SDValue(Res, VTs.size()-2);
2799 } else if (EmitNodeInfo & OPFL_Chain)
2800 InputChain = SDValue(Res, VTs.size()-1);
2802 // If the OPFL_MemRefs glue is set on this node, slap all of the
2803 // accumulated memrefs onto it.
2805 // FIXME: This is vastly incorrect for patterns with multiple outputs
2806 // instructions that access memory and for ComplexPatterns that match
2808 if (EmitNodeInfo & OPFL_MemRefs) {
2809 // Only attach load or store memory operands if the generated
2810 // instruction may load or store.
2811 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2812 bool mayLoad = MCID.mayLoad();
2813 bool mayStore = MCID.mayStore();
2815 unsigned NumMemRefs = 0;
2816 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2817 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2818 if ((*I)->isLoad()) {
2821 } else if ((*I)->isStore()) {
2829 MachineSDNode::mmo_iterator MemRefs =
2830 MF->allocateMemRefsArray(NumMemRefs);
2832 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2833 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2834 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2835 if ((*I)->isLoad()) {
2838 } else if ((*I)->isStore()) {
2846 cast<MachineSDNode>(Res)
2847 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2851 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2852 << " node: "; Res->dump(CurDAG); errs() << "\n");
2854 // If this was a MorphNodeTo then we're completely done!
2855 if (Opcode == OPC_MorphNodeTo) {
2856 // Update chain and glue uses.
2857 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2858 InputGlue, GlueResultNodesMatched, true);
2865 case OPC_MarkGlueResults: {
2866 unsigned NumNodes = MatcherTable[MatcherIndex++];
2868 // Read and remember all the glue-result nodes.
2869 for (unsigned i = 0; i != NumNodes; ++i) {
2870 unsigned RecNo = MatcherTable[MatcherIndex++];
2872 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2874 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2875 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2880 case OPC_CompleteMatch: {
2881 // The match has been completed, and any new nodes (if any) have been
2882 // created. Patch up references to the matched dag to use the newly
2884 unsigned NumResults = MatcherTable[MatcherIndex++];
2886 for (unsigned i = 0; i != NumResults; ++i) {
2887 unsigned ResSlot = MatcherTable[MatcherIndex++];
2889 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2891 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2892 SDValue Res = RecordedNodes[ResSlot].first;
2894 assert(i < NodeToMatch->getNumValues() &&
2895 NodeToMatch->getValueType(i) != MVT::Other &&
2896 NodeToMatch->getValueType(i) != MVT::Glue &&
2897 "Invalid number of results to complete!");
2898 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2899 NodeToMatch->getValueType(i) == MVT::iPTR ||
2900 Res.getValueType() == MVT::iPTR ||
2901 NodeToMatch->getValueType(i).getSizeInBits() ==
2902 Res.getValueType().getSizeInBits()) &&
2903 "invalid replacement");
2904 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2907 // If the root node defines glue, add it to the glue nodes to update list.
2908 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2909 GlueResultNodesMatched.push_back(NodeToMatch);
2911 // Update chain and glue uses.
2912 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2913 InputGlue, GlueResultNodesMatched, false);
2915 assert(NodeToMatch->use_empty() &&
2916 "Didn't replace all uses of the node?");
2918 // FIXME: We just return here, which interacts correctly with SelectRoot
2919 // above. We should fix this to not return an SDNode* anymore.
2924 // If the code reached this point, then the match failed. See if there is
2925 // another child to try in the current 'Scope', otherwise pop it until we
2926 // find a case to check.
2927 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2928 ++NumDAGIselRetries;
2930 if (MatchScopes.empty()) {
2931 CannotYetSelect(NodeToMatch);
2935 // Restore the interpreter state back to the point where the scope was
2937 MatchScope &LastScope = MatchScopes.back();
2938 RecordedNodes.resize(LastScope.NumRecordedNodes);
2940 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2941 N = NodeStack.back();
2943 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2944 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2945 MatcherIndex = LastScope.FailIndex;
2947 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2949 InputChain = LastScope.InputChain;
2950 InputGlue = LastScope.InputGlue;
2951 if (!LastScope.HasChainNodesMatched)
2952 ChainNodesMatched.clear();
2953 if (!LastScope.HasGlueResultNodesMatched)
2954 GlueResultNodesMatched.clear();
2956 // Check to see what the offset is at the new MatcherIndex. If it is zero
2957 // we have reached the end of this scope, otherwise we have another child
2958 // in the current scope to try.
2959 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2960 if (NumToSkip & 128)
2961 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2963 // If we have another child in this scope to match, update FailIndex and
2965 if (NumToSkip != 0) {
2966 LastScope.FailIndex = MatcherIndex+NumToSkip;
2970 // End of this scope, pop it and try the next child in the containing
2972 MatchScopes.pop_back();
2979 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2981 raw_string_ostream Msg(msg);
2982 Msg << "Cannot select: ";
2984 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2985 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2986 N->getOpcode() != ISD::INTRINSIC_VOID) {
2987 N->printrFull(Msg, CurDAG);
2989 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2991 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2992 if (iid < Intrinsic::num_intrinsics)
2993 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2994 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2995 Msg << "target intrinsic %" << TII->getName(iid);
2997 Msg << "unknown intrinsic #" << iid;
2999 report_fatal_error(Msg.str());
3002 char SelectionDAGISel::ID = 0;