1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/CFG.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/DebugInfo.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/IntrinsicInst.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/IR/LLVMContext.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/Timer.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/Target/TargetInstrInfo.h"
51 #include "llvm/Target/TargetIntrinsicInfo.h"
52 #include "llvm/Target/TargetLibraryInfo.h"
53 #include "llvm/Target/TargetLowering.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Target/TargetOptions.h"
56 #include "llvm/Target/TargetRegisterInfo.h"
57 #include "llvm/Target/TargetSubtargetInfo.h"
58 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
62 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
63 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
64 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
65 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
66 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
68 STATISTIC(NumFastIselFailLowerArguments,
69 "Number of entry blocks where fast isel failed to lower arguments");
73 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
74 cl::desc("Enable extra verbose messages in the \"fast\" "
75 "instruction selector"));
78 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
79 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
80 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
81 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
82 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
83 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
84 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
86 // Standard binary operators...
87 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
88 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
89 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
90 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
91 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
92 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
93 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
94 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
95 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
96 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
97 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
98 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
100 // Logical operators...
101 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
102 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
103 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
105 // Memory instructions...
106 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
107 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
108 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
109 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
110 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
111 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
112 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
114 // Convert instructions...
115 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
116 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
117 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
118 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
119 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
120 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
121 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
122 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
123 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
124 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
125 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
126 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
128 // Other instructions...
129 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
130 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
131 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
132 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
133 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
134 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
135 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
136 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
137 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
138 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
139 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
140 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
141 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
142 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
143 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
147 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
148 cl::desc("Enable verbose messages in the \"fast\" "
149 "instruction selector"));
151 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
152 cl::desc("Enable abort calls when \"fast\" instruction selection "
153 "fails to lower an instruction"));
155 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
156 cl::desc("Enable abort calls when \"fast\" instruction selection "
157 "fails to lower a formal argument"));
161 cl::desc("use Machine Branch Probability Info"),
162 cl::init(true), cl::Hidden);
166 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
167 cl::desc("Pop up a window to show dags before the first "
168 "dag combine pass"));
170 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
171 cl::desc("Pop up a window to show dags before legalize types"));
173 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
174 cl::desc("Pop up a window to show dags before legalize"));
176 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
177 cl::desc("Pop up a window to show dags before the second "
178 "dag combine pass"));
180 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
181 cl::desc("Pop up a window to show dags before the post legalize types"
182 " dag combine pass"));
184 ViewISelDAGs("view-isel-dags", cl::Hidden,
185 cl::desc("Pop up a window to show isel dags as they are selected"));
187 ViewSchedDAGs("view-sched-dags", cl::Hidden,
188 cl::desc("Pop up a window to show sched dags as they are processed"));
190 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
191 cl::desc("Pop up a window to show SUnit dags after they are processed"));
193 static const bool ViewDAGCombine1 = false,
194 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
195 ViewDAGCombine2 = false,
196 ViewDAGCombineLT = false,
197 ViewISelDAGs = false, ViewSchedDAGs = false,
198 ViewSUnitDAGs = false;
201 //===---------------------------------------------------------------------===//
203 /// RegisterScheduler class - Track the registration of instruction schedulers.
205 //===---------------------------------------------------------------------===//
206 MachinePassRegistry RegisterScheduler::Registry;
208 //===---------------------------------------------------------------------===//
210 /// ISHeuristic command line option for instruction schedulers.
212 //===---------------------------------------------------------------------===//
213 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
214 RegisterPassParser<RegisterScheduler> >
215 ISHeuristic("pre-RA-sched",
216 cl::init(&createDefaultScheduler),
217 cl::desc("Instruction schedulers available (before register"
220 static RegisterScheduler
221 defaultListDAGScheduler("default", "Best scheduler for the target",
222 createDefaultScheduler);
225 //===--------------------------------------------------------------------===//
226 /// \brief This struct is used by SelectionDAGISel to temporarily override
227 /// the optimization level on a per-function basis.
228 class OptLevelChanger {
229 SelectionDAGISel &IS;
230 CodeGenOpt::Level SavedOptLevel;
233 OptLevelChanger(SelectionDAGISel &ISel,
234 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
235 SavedOptLevel = IS.OptLevel;
236 if (NewOptLevel == SavedOptLevel)
238 IS.OptLevel = NewOptLevel;
239 IS.TM.setOptLevel(NewOptLevel);
240 DEBUG(dbgs() << "\nChanging optimization level for Function "
241 << IS.MF->getFunction()->getName() << "\n");
242 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
243 << " ; After: -O" << NewOptLevel << "\n");
247 if (IS.OptLevel == SavedOptLevel)
249 DEBUG(dbgs() << "\nRestoring optimization level for Function "
250 << IS.MF->getFunction()->getName() << "\n");
251 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
252 << " ; After: -O" << SavedOptLevel << "\n");
253 IS.OptLevel = SavedOptLevel;
254 IS.TM.setOptLevel(SavedOptLevel);
258 //===--------------------------------------------------------------------===//
259 /// createDefaultScheduler - This creates an instruction scheduler appropriate
261 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
262 CodeGenOpt::Level OptLevel) {
263 const TargetLowering *TLI = IS->getTargetLowering();
264 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
266 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
267 TLI->getSchedulingPreference() == Sched::Source)
268 return createSourceListDAGScheduler(IS, OptLevel);
269 if (TLI->getSchedulingPreference() == Sched::RegPressure)
270 return createBURRListDAGScheduler(IS, OptLevel);
271 if (TLI->getSchedulingPreference() == Sched::Hybrid)
272 return createHybridListDAGScheduler(IS, OptLevel);
273 if (TLI->getSchedulingPreference() == Sched::VLIW)
274 return createVLIWDAGScheduler(IS, OptLevel);
275 assert(TLI->getSchedulingPreference() == Sched::ILP &&
276 "Unknown sched type!");
277 return createILPListDAGScheduler(IS, OptLevel);
281 // EmitInstrWithCustomInserter - This method should be implemented by targets
282 // that mark instructions with the 'usesCustomInserter' flag. These
283 // instructions are special in various ways, which require special support to
284 // insert. The specified MachineInstr is created but not inserted into any
285 // basic blocks, and this method is called to expand it into a sequence of
286 // instructions, potentially also creating new basic blocks and control flow.
287 // When new basic blocks are inserted and the edges from MBB to its successors
288 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
291 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
292 MachineBasicBlock *MBB) const {
294 dbgs() << "If a target marks an instruction with "
295 "'usesCustomInserter', it must implement "
296 "TargetLowering::EmitInstrWithCustomInserter!";
301 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
302 SDNode *Node) const {
303 assert(!MI->hasPostISelHook() &&
304 "If a target marks an instruction with 'hasPostISelHook', "
305 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
308 //===----------------------------------------------------------------------===//
309 // SelectionDAGISel code
310 //===----------------------------------------------------------------------===//
312 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
313 CodeGenOpt::Level OL) :
314 MachineFunctionPass(ID), TM(tm),
315 FuncInfo(new FunctionLoweringInfo(TM)),
316 CurDAG(new SelectionDAG(tm, OL)),
317 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
321 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
322 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
323 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
324 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
327 SelectionDAGISel::~SelectionDAGISel() {
333 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
334 AU.addRequired<AliasAnalysis>();
335 AU.addPreserved<AliasAnalysis>();
336 AU.addRequired<GCModuleInfo>();
337 AU.addPreserved<GCModuleInfo>();
338 AU.addRequired<TargetLibraryInfo>();
339 if (UseMBPI && OptLevel != CodeGenOpt::None)
340 AU.addRequired<BranchProbabilityInfo>();
341 MachineFunctionPass::getAnalysisUsage(AU);
344 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
345 /// may trap on it. In this case we have to split the edge so that the path
346 /// through the predecessor block that doesn't go to the phi block doesn't
347 /// execute the possibly trapping instruction.
349 /// This is required for correctness, so it must be done at -O0.
351 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
352 // Loop for blocks with phi nodes.
353 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
354 PHINode *PN = dyn_cast<PHINode>(BB->begin());
355 if (PN == 0) continue;
358 // For each block with a PHI node, check to see if any of the input values
359 // are potentially trapping constant expressions. Constant expressions are
360 // the only potentially trapping value that can occur as the argument to a
362 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
363 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
364 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
365 if (CE == 0 || !CE->canTrap()) continue;
367 // The only case we have to worry about is when the edge is critical.
368 // Since this block has a PHI Node, we assume it has multiple input
369 // edges: check to see if the pred has multiple successors.
370 BasicBlock *Pred = PN->getIncomingBlock(i);
371 if (Pred->getTerminator()->getNumSuccessors() == 1)
374 // Okay, we have to split this edge.
375 SplitCriticalEdge(Pred->getTerminator(),
376 GetSuccessorNumber(Pred, BB), SDISel, true);
382 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
383 // Do some sanity-checking on the command-line options.
384 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
385 "-fast-isel-verbose requires -fast-isel");
386 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
387 "-fast-isel-abort requires -fast-isel");
389 const Function &Fn = *mf.getFunction();
390 const TargetInstrInfo &TII = *TM.getInstrInfo();
391 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
392 const TargetLowering *TLI = TM.getTargetLowering();
395 RegInfo = &MF->getRegInfo();
396 AA = &getAnalysis<AliasAnalysis>();
397 LibInfo = &getAnalysis<TargetLibraryInfo>();
398 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
399 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
401 TargetSubtargetInfo &ST =
402 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
403 ST.resetSubtargetFeatures(MF);
404 TM.resetTargetOptions(MF);
406 // Reset OptLevel to None for optnone functions.
407 CodeGenOpt::Level NewOptLevel = OptLevel;
408 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
409 NewOptLevel = CodeGenOpt::None;
410 OptLevelChanger OLC(*this, NewOptLevel);
412 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
414 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
416 CurDAG->init(*MF, TTI, TLI);
417 FuncInfo->set(Fn, *MF);
419 if (UseMBPI && OptLevel != CodeGenOpt::None)
420 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
424 SDB->init(GFI, *AA, LibInfo);
426 MF->setHasMSInlineAsm(false);
427 SelectAllBasicBlocks(Fn);
429 // If the first basic block in the function has live ins that need to be
430 // copied into vregs, emit the copies into the top of the block before
431 // emitting the code for the block.
432 MachineBasicBlock *EntryMBB = MF->begin();
433 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
435 DenseMap<unsigned, unsigned> LiveInMap;
436 if (!FuncInfo->ArgDbgValues.empty())
437 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
438 E = RegInfo->livein_end(); LI != E; ++LI)
440 LiveInMap.insert(std::make_pair(LI->first, LI->second));
442 // Insert DBG_VALUE instructions for function arguments to the entry block.
443 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
444 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
445 bool hasFI = MI->getOperand(0).isFI();
447 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
448 if (TargetRegisterInfo::isPhysicalRegister(Reg))
449 EntryMBB->insert(EntryMBB->begin(), MI);
451 MachineInstr *Def = RegInfo->getVRegDef(Reg);
453 MachineBasicBlock::iterator InsertPos = Def;
454 // FIXME: VR def may not be in entry block.
455 Def->getParent()->insert(llvm::next(InsertPos), MI);
457 DEBUG(dbgs() << "Dropping debug info for dead vreg"
458 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
461 // If Reg is live-in then update debug info to track its copy in a vreg.
462 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
463 if (LDI != LiveInMap.end()) {
464 assert(!hasFI && "There's no handling of frame pointer updating here yet "
466 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
467 MachineBasicBlock::iterator InsertPos = Def;
468 const MDNode *Variable =
469 MI->getOperand(MI->getNumOperands()-1).getMetadata();
470 bool IsIndirect = MI->isIndirectDebugValue();
471 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
472 // Def is never a terminator here, so it is ok to increment InsertPos.
473 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
474 TII.get(TargetOpcode::DBG_VALUE),
476 LDI->second, Offset, Variable);
478 // If this vreg is directly copied into an exported register then
479 // that COPY instructions also need DBG_VALUE, if it is the only
480 // user of LDI->second.
481 MachineInstr *CopyUseMI = NULL;
482 for (MachineRegisterInfo::use_iterator
483 UI = RegInfo->use_begin(LDI->second);
484 MachineInstr *UseMI = UI.skipInstruction();) {
485 if (UseMI->isDebugValue()) continue;
486 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
487 CopyUseMI = UseMI; continue;
489 // Otherwise this is another use or second copy use.
490 CopyUseMI = NULL; break;
493 MachineInstr *NewMI =
494 BuildMI(*MF, CopyUseMI->getDebugLoc(),
495 TII.get(TargetOpcode::DBG_VALUE),
497 CopyUseMI->getOperand(0).getReg(),
499 MachineBasicBlock::iterator Pos = CopyUseMI;
500 EntryMBB->insertAfter(Pos, NewMI);
505 // Determine if there are any calls in this machine function.
506 MachineFrameInfo *MFI = MF->getFrameInfo();
507 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
510 if (MFI->hasCalls() && MF->hasMSInlineAsm())
513 const MachineBasicBlock *MBB = I;
514 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
516 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
517 if ((MCID.isCall() && !MCID.isReturn()) ||
518 II->isStackAligningInlineAsm()) {
519 MFI->setHasCalls(true);
521 if (II->isMSInlineAsm()) {
522 MF->setHasMSInlineAsm(true);
527 // Determine if there is a call to setjmp in the machine function.
528 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
530 // Replace forward-declared registers with the registers containing
531 // the desired value.
532 MachineRegisterInfo &MRI = MF->getRegInfo();
533 for (DenseMap<unsigned, unsigned>::iterator
534 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
536 unsigned From = I->first;
537 unsigned To = I->second;
538 // If To is also scheduled to be replaced, find what its ultimate
541 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
545 // Make sure the new register has a sufficiently constrained register class.
546 if (TargetRegisterInfo::isVirtualRegister(From) &&
547 TargetRegisterInfo::isVirtualRegister(To))
548 MRI.constrainRegClass(To, MRI.getRegClass(From));
550 MRI.replaceRegWith(From, To);
553 // Freeze the set of reserved registers now that MachineFrameInfo has been
554 // set up. All the information required by getReservedRegs() should be
556 MRI.freezeReservedRegs(*MF);
558 // Release function-specific state. SDB and CurDAG are already cleared
565 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
566 BasicBlock::const_iterator End,
568 // Lower all of the non-terminator instructions. If a call is emitted
569 // as a tail call, cease emitting nodes for this block. Terminators
570 // are handled below.
571 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
574 // Make sure the root of the DAG is up-to-date.
575 CurDAG->setRoot(SDB->getControlRoot());
576 HadTailCall = SDB->HasTailCall;
579 // Final step, emit the lowered DAG as machine code.
583 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
584 SmallPtrSet<SDNode*, 128> VisitedNodes;
585 SmallVector<SDNode*, 128> Worklist;
587 Worklist.push_back(CurDAG->getRoot().getNode());
593 SDNode *N = Worklist.pop_back_val();
595 // If we've already seen this node, ignore it.
596 if (!VisitedNodes.insert(N))
599 // Otherwise, add all chain operands to the worklist.
600 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
601 if (N->getOperand(i).getValueType() == MVT::Other)
602 Worklist.push_back(N->getOperand(i).getNode());
604 // If this is a CopyToReg with a vreg dest, process it.
605 if (N->getOpcode() != ISD::CopyToReg)
608 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
609 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
612 // Ignore non-scalar or non-integer values.
613 SDValue Src = N->getOperand(2);
614 EVT SrcVT = Src.getValueType();
615 if (!SrcVT.isInteger() || SrcVT.isVector())
618 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
619 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
620 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
621 } while (!Worklist.empty());
624 void SelectionDAGISel::CodeGenAndEmitDAG() {
625 std::string GroupName;
626 if (TimePassesIsEnabled)
627 GroupName = "Instruction Selection and Scheduling";
628 std::string BlockName;
629 int BlockNumber = -1;
632 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
633 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
637 BlockNumber = FuncInfo->MBB->getNumber();
638 BlockName = MF->getName().str() + ":" +
639 FuncInfo->MBB->getBasicBlock()->getName().str();
641 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
642 << " '" << BlockName << "'\n"; CurDAG->dump());
644 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
646 // Run the DAG combiner in pre-legalize mode.
648 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
649 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
652 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
653 << " '" << BlockName << "'\n"; CurDAG->dump());
655 // Second step, hack on the DAG until it only uses operations and types that
656 // the target supports.
657 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
662 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
663 Changed = CurDAG->LegalizeTypes();
666 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
667 << " '" << BlockName << "'\n"; CurDAG->dump());
670 if (ViewDAGCombineLT)
671 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
673 // Run the DAG combiner in post-type-legalize mode.
675 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
676 TimePassesIsEnabled);
677 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
680 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
681 << " '" << BlockName << "'\n"; CurDAG->dump());
686 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
687 Changed = CurDAG->LegalizeVectors();
692 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
693 CurDAG->LegalizeTypes();
696 if (ViewDAGCombineLT)
697 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
699 // Run the DAG combiner in post-type-legalize mode.
701 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
702 TimePassesIsEnabled);
703 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
706 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
707 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
710 CurDAG->NewNodesMustHaveLegalTypes = true;
712 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
715 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
719 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
720 << " '" << BlockName << "'\n"; CurDAG->dump());
722 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
724 // Run the DAG combiner in post-legalize mode.
726 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
727 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
730 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
731 << " '" << BlockName << "'\n"; CurDAG->dump());
733 if (OptLevel != CodeGenOpt::None)
734 ComputeLiveOutVRegInfo();
736 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
738 // Third, instruction select all of the operations to machine code, adding the
739 // code to the MachineBasicBlock.
741 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
742 DoInstructionSelection();
745 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
746 << " '" << BlockName << "'\n"; CurDAG->dump());
748 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
750 // Schedule machine code.
751 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
753 NamedRegionTimer T("Instruction Scheduling", GroupName,
754 TimePassesIsEnabled);
755 Scheduler->Run(CurDAG, FuncInfo->MBB);
758 if (ViewSUnitDAGs) Scheduler->viewGraph();
760 // Emit machine code to BB. This can change 'BB' to the last block being
762 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
764 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
766 // FuncInfo->InsertPt is passed by reference and set to the end of the
767 // scheduled instructions.
768 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
771 // If the block was split, make sure we update any references that are used to
772 // update PHI nodes later on.
773 if (FirstMBB != LastMBB)
774 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
776 // Free the scheduler state.
778 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
779 TimePassesIsEnabled);
783 // Free the SelectionDAG state, now that we're finished with it.
788 /// ISelUpdater - helper class to handle updates of the instruction selection
790 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
791 SelectionDAG::allnodes_iterator &ISelPosition;
793 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
794 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
796 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
797 /// deleted is the current ISelPosition node, update ISelPosition.
799 virtual void NodeDeleted(SDNode *N, SDNode *E) {
800 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
804 } // end anonymous namespace
806 void SelectionDAGISel::DoInstructionSelection() {
807 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
808 << FuncInfo->MBB->getNumber()
809 << " '" << FuncInfo->MBB->getName() << "'\n");
813 // Select target instructions for the DAG.
815 // Number all nodes with a topological order and set DAGSize.
816 DAGSize = CurDAG->AssignTopologicalOrder();
818 // Create a dummy node (which is not added to allnodes), that adds
819 // a reference to the root node, preventing it from being deleted,
820 // and tracking any changes of the root.
821 HandleSDNode Dummy(CurDAG->getRoot());
822 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
825 // Make sure that ISelPosition gets properly updated when nodes are deleted
826 // in calls made from this function.
827 ISelUpdater ISU(*CurDAG, ISelPosition);
829 // The AllNodes list is now topological-sorted. Visit the
830 // nodes by starting at the end of the list (the root of the
831 // graph) and preceding back toward the beginning (the entry
833 while (ISelPosition != CurDAG->allnodes_begin()) {
834 SDNode *Node = --ISelPosition;
835 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
836 // but there are currently some corner cases that it misses. Also, this
837 // makes it theoretically possible to disable the DAGCombiner.
838 if (Node->use_empty())
841 SDNode *ResNode = Select(Node);
843 // FIXME: This is pretty gross. 'Select' should be changed to not return
844 // anything at all and this code should be nuked with a tactical strike.
846 // If node should not be replaced, continue with the next one.
847 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
851 ReplaceUses(Node, ResNode);
854 // If after the replacement this node is not used any more,
855 // remove this dead node.
856 if (Node->use_empty()) // Don't delete EntryToken, etc.
857 CurDAG->RemoveDeadNode(Node);
860 CurDAG->setRoot(Dummy.getValue());
863 DEBUG(dbgs() << "===== Instruction selection ends:\n");
865 PostprocessISelDAG();
868 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
869 /// do other setup for EH landing-pad blocks.
870 void SelectionDAGISel::PrepareEHLandingPad() {
871 MachineBasicBlock *MBB = FuncInfo->MBB;
873 // Add a label to mark the beginning of the landing pad. Deletion of the
874 // landing pad can thus be detected via the MachineModuleInfo.
875 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
877 // Assign the call site to the landing pad's begin label.
878 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
880 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
881 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
884 // Mark exception register as live in.
885 const TargetLowering *TLI = getTargetLowering();
886 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
887 if (unsigned Reg = TLI->getExceptionPointerRegister())
888 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
890 // Mark exception selector register as live in.
891 if (unsigned Reg = TLI->getExceptionSelectorRegister())
892 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
895 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
896 /// side-effect free and is either dead or folded into a generated instruction.
897 /// Return false if it needs to be emitted.
898 static bool isFoldedOrDeadInstruction(const Instruction *I,
899 FunctionLoweringInfo *FuncInfo) {
900 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
901 !isa<TerminatorInst>(I) && // Terminators aren't folded.
902 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
903 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
904 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
908 // Collect per Instruction statistics for fast-isel misses. Only those
909 // instructions that cause the bail are accounted for. It does not account for
910 // instructions higher in the block. Thus, summing the per instructions stats
911 // will not add up to what is reported by NumFastIselFailures.
912 static void collectFailStats(const Instruction *I) {
913 switch (I->getOpcode()) {
914 default: assert (0 && "<Invalid operator> ");
917 case Instruction::Ret: NumFastIselFailRet++; return;
918 case Instruction::Br: NumFastIselFailBr++; return;
919 case Instruction::Switch: NumFastIselFailSwitch++; return;
920 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
921 case Instruction::Invoke: NumFastIselFailInvoke++; return;
922 case Instruction::Resume: NumFastIselFailResume++; return;
923 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
925 // Standard binary operators...
926 case Instruction::Add: NumFastIselFailAdd++; return;
927 case Instruction::FAdd: NumFastIselFailFAdd++; return;
928 case Instruction::Sub: NumFastIselFailSub++; return;
929 case Instruction::FSub: NumFastIselFailFSub++; return;
930 case Instruction::Mul: NumFastIselFailMul++; return;
931 case Instruction::FMul: NumFastIselFailFMul++; return;
932 case Instruction::UDiv: NumFastIselFailUDiv++; return;
933 case Instruction::SDiv: NumFastIselFailSDiv++; return;
934 case Instruction::FDiv: NumFastIselFailFDiv++; return;
935 case Instruction::URem: NumFastIselFailURem++; return;
936 case Instruction::SRem: NumFastIselFailSRem++; return;
937 case Instruction::FRem: NumFastIselFailFRem++; return;
939 // Logical operators...
940 case Instruction::And: NumFastIselFailAnd++; return;
941 case Instruction::Or: NumFastIselFailOr++; return;
942 case Instruction::Xor: NumFastIselFailXor++; return;
944 // Memory instructions...
945 case Instruction::Alloca: NumFastIselFailAlloca++; return;
946 case Instruction::Load: NumFastIselFailLoad++; return;
947 case Instruction::Store: NumFastIselFailStore++; return;
948 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
949 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
950 case Instruction::Fence: NumFastIselFailFence++; return;
951 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
953 // Convert instructions...
954 case Instruction::Trunc: NumFastIselFailTrunc++; return;
955 case Instruction::ZExt: NumFastIselFailZExt++; return;
956 case Instruction::SExt: NumFastIselFailSExt++; return;
957 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
958 case Instruction::FPExt: NumFastIselFailFPExt++; return;
959 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
960 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
961 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
962 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
963 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
964 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
965 case Instruction::BitCast: NumFastIselFailBitCast++; return;
967 // Other instructions...
968 case Instruction::ICmp: NumFastIselFailICmp++; return;
969 case Instruction::FCmp: NumFastIselFailFCmp++; return;
970 case Instruction::PHI: NumFastIselFailPHI++; return;
971 case Instruction::Select: NumFastIselFailSelect++; return;
972 case Instruction::Call: NumFastIselFailCall++; return;
973 case Instruction::Shl: NumFastIselFailShl++; return;
974 case Instruction::LShr: NumFastIselFailLShr++; return;
975 case Instruction::AShr: NumFastIselFailAShr++; return;
976 case Instruction::VAArg: NumFastIselFailVAArg++; return;
977 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
978 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
979 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
980 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
981 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
982 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
987 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
988 // Initialize the Fast-ISel state, if needed.
989 FastISel *FastIS = 0;
990 if (TM.Options.EnableFastISel || Fn.hasFnAttribute(Attribute::OptimizeNone))
991 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo);
993 // Iterate over all basic blocks in the function.
994 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
995 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
996 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
997 const BasicBlock *LLVMBB = *I;
999 if (OptLevel != CodeGenOpt::None) {
1000 bool AllPredsVisited = true;
1001 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1003 if (!FuncInfo->VisitedBBs.count(*PI)) {
1004 AllPredsVisited = false;
1009 if (AllPredsVisited) {
1010 for (BasicBlock::const_iterator I = LLVMBB->begin();
1011 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1012 FuncInfo->ComputePHILiveOutRegInfo(PN);
1014 for (BasicBlock::const_iterator I = LLVMBB->begin();
1015 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1016 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1019 FuncInfo->VisitedBBs.insert(LLVMBB);
1022 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1023 BasicBlock::const_iterator const End = LLVMBB->end();
1024 BasicBlock::const_iterator BI = End;
1026 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1027 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1029 // Setup an EH landing-pad block.
1030 FuncInfo->ExceptionPointerVirtReg = 0;
1031 FuncInfo->ExceptionSelectorVirtReg = 0;
1032 if (FuncInfo->MBB->isLandingPad())
1033 PrepareEHLandingPad();
1035 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1037 FastIS->startNewBlock();
1039 // Emit code for any incoming arguments. This must happen before
1040 // beginning FastISel on the entry block.
1041 if (LLVMBB == &Fn.getEntryBlock()) {
1044 // Lower any arguments needed in this block if this is the entry block.
1045 if (!FastIS->LowerArguments()) {
1046 // Fast isel failed to lower these arguments
1047 ++NumFastIselFailLowerArguments;
1048 if (EnableFastISelAbortArgs)
1049 llvm_unreachable("FastISel didn't lower all arguments");
1051 // Use SelectionDAG argument lowering
1053 CurDAG->setRoot(SDB->getControlRoot());
1055 CodeGenAndEmitDAG();
1058 // If we inserted any instructions at the beginning, make a note of
1059 // where they are, so we can be sure to emit subsequent instructions
1061 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1062 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1064 FastIS->setLastLocalValue(0);
1067 unsigned NumFastIselRemaining = std::distance(Begin, End);
1068 // Do FastISel on as many instructions as possible.
1069 for (; BI != Begin; --BI) {
1070 const Instruction *Inst = llvm::prior(BI);
1072 // If we no longer require this instruction, skip it.
1073 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1074 --NumFastIselRemaining;
1078 // Bottom-up: reset the insert pos at the top, after any local-value
1080 FastIS->recomputeInsertPt();
1082 // Try to select the instruction with FastISel.
1083 if (FastIS->SelectInstruction(Inst)) {
1084 --NumFastIselRemaining;
1085 ++NumFastIselSuccess;
1086 // If fast isel succeeded, skip over all the folded instructions, and
1087 // then see if there is a load right before the selected instructions.
1088 // Try to fold the load if so.
1089 const Instruction *BeforeInst = Inst;
1090 while (BeforeInst != Begin) {
1091 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1092 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1095 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1096 BeforeInst->hasOneUse() &&
1097 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1098 // If we succeeded, don't re-select the load.
1099 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1100 --NumFastIselRemaining;
1101 ++NumFastIselSuccess;
1107 if (EnableFastISelVerbose2)
1108 collectFailStats(Inst);
1111 // Then handle certain instructions as single-LLVM-Instruction blocks.
1112 if (isa<CallInst>(Inst)) {
1114 if (EnableFastISelVerbose || EnableFastISelAbort) {
1115 dbgs() << "FastISel missed call: ";
1119 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1120 unsigned &R = FuncInfo->ValueMap[Inst];
1122 R = FuncInfo->CreateRegs(Inst->getType());
1125 bool HadTailCall = false;
1126 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1127 SelectBasicBlock(Inst, BI, HadTailCall);
1129 // If the call was emitted as a tail call, we're done with the block.
1130 // We also need to delete any previously emitted instructions.
1132 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1137 // Recompute NumFastIselRemaining as Selection DAG instruction
1138 // selection may have handled the call, input args, etc.
1139 unsigned RemainingNow = std::distance(Begin, BI);
1140 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1141 NumFastIselRemaining = RemainingNow;
1145 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1146 // Don't abort, and use a different message for terminator misses.
1147 NumFastIselFailures += NumFastIselRemaining;
1148 if (EnableFastISelVerbose || EnableFastISelAbort) {
1149 dbgs() << "FastISel missed terminator: ";
1153 NumFastIselFailures += NumFastIselRemaining;
1154 if (EnableFastISelVerbose || EnableFastISelAbort) {
1155 dbgs() << "FastISel miss: ";
1158 if (EnableFastISelAbort)
1159 // The "fast" selector couldn't handle something and bailed.
1160 // For the purpose of debugging, just abort.
1161 llvm_unreachable("FastISel didn't select the entire block");
1166 FastIS->recomputeInsertPt();
1168 // Lower any arguments needed in this block if this is the entry block.
1169 if (LLVMBB == &Fn.getEntryBlock()) {
1178 ++NumFastIselBlocks;
1181 // Run SelectionDAG instruction selection on the remainder of the block
1182 // not handled by FastISel. If FastISel is not run, this is the entire
1185 SelectBasicBlock(Begin, BI, HadTailCall);
1189 FuncInfo->PHINodesToUpdate.clear();
1193 SDB->clearDanglingDebugInfo();
1194 SDB->SPDescriptor.resetPerFunctionState();
1197 /// Given that the input MI is before a partial terminator sequence TSeq, return
1198 /// true if M + TSeq also a partial terminator sequence.
1200 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1201 /// lowering copy vregs into physical registers, which are then passed into
1202 /// terminator instructors so we can satisfy ABI constraints. A partial
1203 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1204 /// may be the whole terminator sequence).
1205 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1206 // If we do not have a copy or an implicit def, we return true if and only if
1207 // MI is a debug value.
1208 if (!MI->isCopy() && !MI->isImplicitDef())
1209 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1210 // physical registers if there is debug info associated with the terminator
1211 // of our mbb. We want to include said debug info in our terminator
1212 // sequence, so we return true in that case.
1213 return MI->isDebugValue();
1215 // We have left the terminator sequence if we are not doing one of the
1218 // 1. Copying a vreg into a physical register.
1219 // 2. Copying a vreg into a vreg.
1220 // 3. Defining a register via an implicit def.
1222 // OPI should always be a register definition...
1223 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1224 if (!OPI->isReg() || !OPI->isDef())
1227 // Defining any register via an implicit def is always ok.
1228 if (MI->isImplicitDef())
1231 // Grab the copy source...
1232 MachineInstr::const_mop_iterator OPI2 = OPI;
1234 assert(OPI2 != MI->operands_end()
1235 && "Should have a copy implying we should have 2 arguments.");
1237 // Make sure that the copy dest is not a vreg when the copy source is a
1238 // physical register.
1239 if (!OPI2->isReg() ||
1240 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1241 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1247 /// Find the split point at which to splice the end of BB into its success stack
1248 /// protector check machine basic block.
1250 /// On many platforms, due to ABI constraints, terminators, even before register
1251 /// allocation, use physical registers. This creates an issue for us since
1252 /// physical registers at this point can not travel across basic
1253 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1254 /// when they enter functions and moves them through a sequence of copies back
1255 /// into the physical registers right before the terminator creating a
1256 /// ``Terminator Sequence''. This function is searching for the beginning of the
1257 /// terminator sequence so that we can ensure that we splice off not just the
1258 /// terminator, but additionally the copies that move the vregs into the
1259 /// physical registers.
1260 static MachineBasicBlock::iterator
1261 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1262 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1264 if (SplitPoint == BB->begin())
1267 MachineBasicBlock::iterator Start = BB->begin();
1268 MachineBasicBlock::iterator Previous = SplitPoint;
1271 while (MIIsInTerminatorSequence(Previous)) {
1272 SplitPoint = Previous;
1273 if (Previous == Start)
1282 SelectionDAGISel::FinishBasicBlock() {
1284 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1285 << FuncInfo->PHINodesToUpdate.size() << "\n";
1286 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1287 dbgs() << "Node " << i << " : ("
1288 << FuncInfo->PHINodesToUpdate[i].first
1289 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1291 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1292 SDB->JTCases.empty() &&
1293 SDB->BitTestCases.empty();
1295 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1296 // PHI nodes in successors.
1297 if (MustUpdatePHINodes) {
1298 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1299 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1300 assert(PHI->isPHI() &&
1301 "This is not a machine PHI node that we are updating!");
1302 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1304 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1308 // Handle stack protector.
1309 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1310 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1311 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1313 // Find the split point to split the parent mbb. At the same time copy all
1314 // physical registers used in the tail of parent mbb into virtual registers
1315 // before the split point and back into physical registers after the split
1316 // point. This prevents us needing to deal with Live-ins and many other
1317 // register allocation issues caused by us splitting the parent mbb. The
1318 // register allocator will clean up said virtual copies later on.
1319 MachineBasicBlock::iterator SplitPoint =
1320 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1322 // Splice the terminator of ParentMBB into SuccessMBB.
1323 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1327 // Add compare/jump on neq/jump to the parent BB.
1328 FuncInfo->MBB = ParentMBB;
1329 FuncInfo->InsertPt = ParentMBB->end();
1330 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1331 CurDAG->setRoot(SDB->getRoot());
1333 CodeGenAndEmitDAG();
1335 // CodeGen Failure MBB if we have not codegened it yet.
1336 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1337 if (!FailureMBB->size()) {
1338 FuncInfo->MBB = FailureMBB;
1339 FuncInfo->InsertPt = FailureMBB->end();
1340 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1341 CurDAG->setRoot(SDB->getRoot());
1343 CodeGenAndEmitDAG();
1346 // Clear the Per-BB State.
1347 SDB->SPDescriptor.resetPerBBState();
1350 // If we updated PHI Nodes, return early.
1351 if (MustUpdatePHINodes)
1354 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1355 // Lower header first, if it wasn't already lowered
1356 if (!SDB->BitTestCases[i].Emitted) {
1357 // Set the current basic block to the mbb we wish to insert the code into
1358 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1359 FuncInfo->InsertPt = FuncInfo->MBB->end();
1361 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1362 CurDAG->setRoot(SDB->getRoot());
1364 CodeGenAndEmitDAG();
1367 uint32_t UnhandledWeight = 0;
1368 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1369 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1371 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1372 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1373 // Set the current basic block to the mbb we wish to insert the code into
1374 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1375 FuncInfo->InsertPt = FuncInfo->MBB->end();
1378 SDB->visitBitTestCase(SDB->BitTestCases[i],
1379 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1381 SDB->BitTestCases[i].Reg,
1382 SDB->BitTestCases[i].Cases[j],
1385 SDB->visitBitTestCase(SDB->BitTestCases[i],
1386 SDB->BitTestCases[i].Default,
1388 SDB->BitTestCases[i].Reg,
1389 SDB->BitTestCases[i].Cases[j],
1393 CurDAG->setRoot(SDB->getRoot());
1395 CodeGenAndEmitDAG();
1399 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1401 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1402 MachineBasicBlock *PHIBB = PHI->getParent();
1403 assert(PHI->isPHI() &&
1404 "This is not a machine PHI node that we are updating!");
1405 // This is "default" BB. We have two jumps to it. From "header" BB and
1406 // from last "case" BB.
1407 if (PHIBB == SDB->BitTestCases[i].Default)
1408 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1409 .addMBB(SDB->BitTestCases[i].Parent)
1410 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1411 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1412 // One of "cases" BB.
1413 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1415 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1416 if (cBB->isSuccessor(PHIBB))
1417 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1421 SDB->BitTestCases.clear();
1423 // If the JumpTable record is filled in, then we need to emit a jump table.
1424 // Updating the PHI nodes is tricky in this case, since we need to determine
1425 // whether the PHI is a successor of the range check MBB or the jump table MBB
1426 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1427 // Lower header first, if it wasn't already lowered
1428 if (!SDB->JTCases[i].first.Emitted) {
1429 // Set the current basic block to the mbb we wish to insert the code into
1430 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1431 FuncInfo->InsertPt = FuncInfo->MBB->end();
1433 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1435 CurDAG->setRoot(SDB->getRoot());
1437 CodeGenAndEmitDAG();
1440 // Set the current basic block to the mbb we wish to insert the code into
1441 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1442 FuncInfo->InsertPt = FuncInfo->MBB->end();
1444 SDB->visitJumpTable(SDB->JTCases[i].second);
1445 CurDAG->setRoot(SDB->getRoot());
1447 CodeGenAndEmitDAG();
1450 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1452 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1453 MachineBasicBlock *PHIBB = PHI->getParent();
1454 assert(PHI->isPHI() &&
1455 "This is not a machine PHI node that we are updating!");
1456 // "default" BB. We can go there only from header BB.
1457 if (PHIBB == SDB->JTCases[i].second.Default)
1458 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1459 .addMBB(SDB->JTCases[i].first.HeaderBB);
1460 // JT BB. Just iterate over successors here
1461 if (FuncInfo->MBB->isSuccessor(PHIBB))
1462 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1465 SDB->JTCases.clear();
1467 // If the switch block involved a branch to one of the actual successors, we
1468 // need to update PHI nodes in that block.
1469 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1470 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1471 assert(PHI->isPHI() &&
1472 "This is not a machine PHI node that we are updating!");
1473 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1474 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1477 // If we generated any switch lowering information, build and codegen any
1478 // additional DAGs necessary.
1479 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1480 // Set the current basic block to the mbb we wish to insert the code into
1481 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1482 FuncInfo->InsertPt = FuncInfo->MBB->end();
1484 // Determine the unique successors.
1485 SmallVector<MachineBasicBlock *, 2> Succs;
1486 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1487 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1488 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1490 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1491 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1492 CurDAG->setRoot(SDB->getRoot());
1494 CodeGenAndEmitDAG();
1496 // Remember the last block, now that any splitting is done, for use in
1497 // populating PHI nodes in successors.
1498 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1500 // Handle any PHI nodes in successors of this chunk, as if we were coming
1501 // from the original BB before switch expansion. Note that PHI nodes can
1502 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1503 // handle them the right number of times.
1504 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1505 FuncInfo->MBB = Succs[i];
1506 FuncInfo->InsertPt = FuncInfo->MBB->end();
1507 // FuncInfo->MBB may have been removed from the CFG if a branch was
1509 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1510 for (MachineBasicBlock::iterator
1511 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1512 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1513 MachineInstrBuilder PHI(*MF, MBBI);
1514 // This value for this PHI node is recorded in PHINodesToUpdate.
1515 for (unsigned pn = 0; ; ++pn) {
1516 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1517 "Didn't find PHI entry!");
1518 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1519 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1527 SDB->SwitchCases.clear();
1531 /// Create the scheduler. If a specific scheduler was specified
1532 /// via the SchedulerRegistry, use it, otherwise select the
1533 /// one preferred by the target.
1535 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1536 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1540 RegisterScheduler::setDefault(Ctor);
1543 return Ctor(this, OptLevel);
1546 //===----------------------------------------------------------------------===//
1547 // Helper functions used by the generated instruction selector.
1548 //===----------------------------------------------------------------------===//
1549 // Calls to these methods are generated by tblgen.
1551 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1552 /// the dag combiner simplified the 255, we still want to match. RHS is the
1553 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1554 /// specified in the .td file (e.g. 255).
1555 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1556 int64_t DesiredMaskS) const {
1557 const APInt &ActualMask = RHS->getAPIntValue();
1558 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1560 // If the actual mask exactly matches, success!
1561 if (ActualMask == DesiredMask)
1564 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1565 if (ActualMask.intersects(~DesiredMask))
1568 // Otherwise, the DAG Combiner may have proven that the value coming in is
1569 // either already zero or is not demanded. Check for known zero input bits.
1570 APInt NeededMask = DesiredMask & ~ActualMask;
1571 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1574 // TODO: check to see if missing bits are just not demanded.
1576 // Otherwise, this pattern doesn't match.
1580 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1581 /// the dag combiner simplified the 255, we still want to match. RHS is the
1582 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1583 /// specified in the .td file (e.g. 255).
1584 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1585 int64_t DesiredMaskS) const {
1586 const APInt &ActualMask = RHS->getAPIntValue();
1587 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1589 // If the actual mask exactly matches, success!
1590 if (ActualMask == DesiredMask)
1593 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1594 if (ActualMask.intersects(~DesiredMask))
1597 // Otherwise, the DAG Combiner may have proven that the value coming in is
1598 // either already zero or is not demanded. Check for known zero input bits.
1599 APInt NeededMask = DesiredMask & ~ActualMask;
1601 APInt KnownZero, KnownOne;
1602 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1604 // If all the missing bits in the or are already known to be set, match!
1605 if ((NeededMask & KnownOne) == NeededMask)
1608 // TODO: check to see if missing bits are just not demanded.
1610 // Otherwise, this pattern doesn't match.
1615 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1616 /// by tblgen. Others should not call it.
1617 void SelectionDAGISel::
1618 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1619 std::vector<SDValue> InOps;
1620 std::swap(InOps, Ops);
1622 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1623 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1624 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1625 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1627 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1628 if (InOps[e-1].getValueType() == MVT::Glue)
1629 --e; // Don't process a glue operand if it is here.
1632 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1633 if (!InlineAsm::isMemKind(Flags)) {
1634 // Just skip over this operand, copying the operands verbatim.
1635 Ops.insert(Ops.end(), InOps.begin()+i,
1636 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1637 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1639 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1640 "Memory operand with multiple values?");
1641 // Otherwise, this is a memory operand. Ask the target to select it.
1642 std::vector<SDValue> SelOps;
1643 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1644 report_fatal_error("Could not match memory address. Inline asm"
1647 // Add this to the output node.
1649 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1650 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1651 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1656 // Add the glue input back if present.
1657 if (e != InOps.size())
1658 Ops.push_back(InOps.back());
1661 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1664 static SDNode *findGlueUse(SDNode *N) {
1665 unsigned FlagResNo = N->getNumValues()-1;
1666 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1667 SDUse &Use = I.getUse();
1668 if (Use.getResNo() == FlagResNo)
1669 return Use.getUser();
1674 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1675 /// This function recursively traverses up the operand chain, ignoring
1677 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1678 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1679 bool IgnoreChains) {
1680 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1681 // greater than all of its (recursive) operands. If we scan to a point where
1682 // 'use' is smaller than the node we're scanning for, then we know we will
1685 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1686 // happen because we scan down to newly selected nodes in the case of glue
1688 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1691 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1692 // won't fail if we scan it again.
1693 if (!Visited.insert(Use))
1696 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1697 // Ignore chain uses, they are validated by HandleMergeInputChains.
1698 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1701 SDNode *N = Use->getOperand(i).getNode();
1703 if (Use == ImmedUse || Use == Root)
1704 continue; // We are not looking for immediate use.
1709 // Traverse up the operand chain.
1710 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1716 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1717 /// operand node N of U during instruction selection that starts at Root.
1718 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1719 SDNode *Root) const {
1720 if (OptLevel == CodeGenOpt::None) return false;
1721 return N.hasOneUse();
1724 /// IsLegalToFold - Returns true if the specific operand node N of
1725 /// U can be folded during instruction selection that starts at Root.
1726 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1727 CodeGenOpt::Level OptLevel,
1728 bool IgnoreChains) {
1729 if (OptLevel == CodeGenOpt::None) return false;
1731 // If Root use can somehow reach N through a path that that doesn't contain
1732 // U then folding N would create a cycle. e.g. In the following
1733 // diagram, Root can reach N through X. If N is folded into into Root, then
1734 // X is both a predecessor and a successor of U.
1745 // * indicates nodes to be folded together.
1747 // If Root produces glue, then it gets (even more) interesting. Since it
1748 // will be "glued" together with its glue use in the scheduler, we need to
1749 // check if it might reach N.
1768 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1769 // (call it Fold), then X is a predecessor of GU and a successor of
1770 // Fold. But since Fold and GU are glued together, this will create
1771 // a cycle in the scheduling graph.
1773 // If the node has glue, walk down the graph to the "lowest" node in the
1775 EVT VT = Root->getValueType(Root->getNumValues()-1);
1776 while (VT == MVT::Glue) {
1777 SDNode *GU = findGlueUse(Root);
1781 VT = Root->getValueType(Root->getNumValues()-1);
1783 // If our query node has a glue result with a use, we've walked up it. If
1784 // the user (which has already been selected) has a chain or indirectly uses
1785 // the chain, our WalkChainUsers predicate will not consider it. Because of
1786 // this, we cannot ignore chains in this predicate.
1787 IgnoreChains = false;
1791 SmallPtrSet<SDNode*, 16> Visited;
1792 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1795 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1796 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1797 SelectInlineAsmMemoryOperands(Ops);
1799 EVT VTs[] = { MVT::Other, MVT::Glue };
1800 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
1801 VTs, &Ops[0], Ops.size());
1803 return New.getNode();
1806 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1807 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1810 /// GetVBR - decode a vbr encoding whose top bit is set.
1811 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1812 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1813 assert(Val >= 128 && "Not a VBR");
1814 Val &= 127; // Remove first vbr bit.
1819 NextBits = MatcherTable[Idx++];
1820 Val |= (NextBits&127) << Shift;
1822 } while (NextBits & 128);
1828 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1829 /// interior glue and chain results to use the new glue and chain results.
1830 void SelectionDAGISel::
1831 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1832 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1834 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1835 bool isMorphNodeTo) {
1836 SmallVector<SDNode*, 4> NowDeadNodes;
1838 // Now that all the normal results are replaced, we replace the chain and
1839 // glue results if present.
1840 if (!ChainNodesMatched.empty()) {
1841 assert(InputChain.getNode() != 0 &&
1842 "Matched input chains but didn't produce a chain");
1843 // Loop over all of the nodes we matched that produced a chain result.
1844 // Replace all the chain results with the final chain we ended up with.
1845 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1846 SDNode *ChainNode = ChainNodesMatched[i];
1848 // If this node was already deleted, don't look at it.
1849 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1852 // Don't replace the results of the root node if we're doing a
1854 if (ChainNode == NodeToMatch && isMorphNodeTo)
1857 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1858 if (ChainVal.getValueType() == MVT::Glue)
1859 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1860 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1861 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1863 // If the node became dead and we haven't already seen it, delete it.
1864 if (ChainNode->use_empty() &&
1865 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1866 NowDeadNodes.push_back(ChainNode);
1870 // If the result produces glue, update any glue results in the matched
1871 // pattern with the glue result.
1872 if (InputGlue.getNode() != 0) {
1873 // Handle any interior nodes explicitly marked.
1874 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1875 SDNode *FRN = GlueResultNodesMatched[i];
1877 // If this node was already deleted, don't look at it.
1878 if (FRN->getOpcode() == ISD::DELETED_NODE)
1881 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1882 "Doesn't have a glue result");
1883 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1886 // If the node became dead and we haven't already seen it, delete it.
1887 if (FRN->use_empty() &&
1888 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1889 NowDeadNodes.push_back(FRN);
1893 if (!NowDeadNodes.empty())
1894 CurDAG->RemoveDeadNodes(NowDeadNodes);
1896 DEBUG(dbgs() << "ISEL: Match complete!\n");
1902 CR_LeadsToInteriorNode
1905 /// WalkChainUsers - Walk down the users of the specified chained node that is
1906 /// part of the pattern we're matching, looking at all of the users we find.
1907 /// This determines whether something is an interior node, whether we have a
1908 /// non-pattern node in between two pattern nodes (which prevent folding because
1909 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1910 /// between pattern nodes (in which case the TF becomes part of the pattern).
1912 /// The walk we do here is guaranteed to be small because we quickly get down to
1913 /// already selected nodes "below" us.
1915 WalkChainUsers(const SDNode *ChainedNode,
1916 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1917 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1918 ChainResult Result = CR_Simple;
1920 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1921 E = ChainedNode->use_end(); UI != E; ++UI) {
1922 // Make sure the use is of the chain, not some other value we produce.
1923 if (UI.getUse().getValueType() != MVT::Other) continue;
1927 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1930 // If we see an already-selected machine node, then we've gone beyond the
1931 // pattern that we're selecting down into the already selected chunk of the
1933 unsigned UserOpcode = User->getOpcode();
1934 if (User->isMachineOpcode() ||
1935 UserOpcode == ISD::CopyToReg ||
1936 UserOpcode == ISD::CopyFromReg ||
1937 UserOpcode == ISD::INLINEASM ||
1938 UserOpcode == ISD::EH_LABEL ||
1939 UserOpcode == ISD::LIFETIME_START ||
1940 UserOpcode == ISD::LIFETIME_END) {
1941 // If their node ID got reset to -1 then they've already been selected.
1942 // Treat them like a MachineOpcode.
1943 if (User->getNodeId() == -1)
1947 // If we have a TokenFactor, we handle it specially.
1948 if (User->getOpcode() != ISD::TokenFactor) {
1949 // If the node isn't a token factor and isn't part of our pattern, then it
1950 // must be a random chained node in between two nodes we're selecting.
1951 // This happens when we have something like:
1956 // Because we structurally match the load/store as a read/modify/write,
1957 // but the call is chained between them. We cannot fold in this case
1958 // because it would induce a cycle in the graph.
1959 if (!std::count(ChainedNodesInPattern.begin(),
1960 ChainedNodesInPattern.end(), User))
1961 return CR_InducesCycle;
1963 // Otherwise we found a node that is part of our pattern. For example in:
1967 // This would happen when we're scanning down from the load and see the
1968 // store as a user. Record that there is a use of ChainedNode that is
1969 // part of the pattern and keep scanning uses.
1970 Result = CR_LeadsToInteriorNode;
1971 InteriorChainedNodes.push_back(User);
1975 // If we found a TokenFactor, there are two cases to consider: first if the
1976 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1977 // uses of the TF are in our pattern) we just want to ignore it. Second,
1978 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1984 // | \ DAG's like cheese
1987 // [TokenFactor] [Op]
1994 // In this case, the TokenFactor becomes part of our match and we rewrite it
1995 // as a new TokenFactor.
1997 // To distinguish these two cases, do a recursive walk down the uses.
1998 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2000 // If the uses of the TokenFactor are just already-selected nodes, ignore
2001 // it, it is "below" our pattern.
2003 case CR_InducesCycle:
2004 // If the uses of the TokenFactor lead to nodes that are not part of our
2005 // pattern that are not selected, folding would turn this into a cycle,
2007 return CR_InducesCycle;
2008 case CR_LeadsToInteriorNode:
2009 break; // Otherwise, keep processing.
2012 // Okay, we know we're in the interesting interior case. The TokenFactor
2013 // is now going to be considered part of the pattern so that we rewrite its
2014 // uses (it may have uses that are not part of the pattern) with the
2015 // ultimate chain result of the generated code. We will also add its chain
2016 // inputs as inputs to the ultimate TokenFactor we create.
2017 Result = CR_LeadsToInteriorNode;
2018 ChainedNodesInPattern.push_back(User);
2019 InteriorChainedNodes.push_back(User);
2026 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2027 /// operation for when the pattern matched at least one node with a chains. The
2028 /// input vector contains a list of all of the chained nodes that we match. We
2029 /// must determine if this is a valid thing to cover (i.e. matching it won't
2030 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2031 /// be used as the input node chain for the generated nodes.
2033 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2034 SelectionDAG *CurDAG) {
2035 // Walk all of the chained nodes we've matched, recursively scanning down the
2036 // users of the chain result. This adds any TokenFactor nodes that are caught
2037 // in between chained nodes to the chained and interior nodes list.
2038 SmallVector<SDNode*, 3> InteriorChainedNodes;
2039 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2040 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2041 InteriorChainedNodes) == CR_InducesCycle)
2042 return SDValue(); // Would induce a cycle.
2045 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2046 // that we are interested in. Form our input TokenFactor node.
2047 SmallVector<SDValue, 3> InputChains;
2048 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2049 // Add the input chain of this node to the InputChains list (which will be
2050 // the operands of the generated TokenFactor) if it's not an interior node.
2051 SDNode *N = ChainNodesMatched[i];
2052 if (N->getOpcode() != ISD::TokenFactor) {
2053 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2056 // Otherwise, add the input chain.
2057 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2058 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2059 InputChains.push_back(InChain);
2063 // If we have a token factor, we want to add all inputs of the token factor
2064 // that are not part of the pattern we're matching.
2065 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2066 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2067 N->getOperand(op).getNode()))
2068 InputChains.push_back(N->getOperand(op));
2072 if (InputChains.size() == 1)
2073 return InputChains[0];
2074 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2075 MVT::Other, &InputChains[0], InputChains.size());
2078 /// MorphNode - Handle morphing a node in place for the selector.
2079 SDNode *SelectionDAGISel::
2080 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2081 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
2082 // It is possible we're using MorphNodeTo to replace a node with no
2083 // normal results with one that has a normal result (or we could be
2084 // adding a chain) and the input could have glue and chains as well.
2085 // In this case we need to shift the operands down.
2086 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2087 // than the old isel though.
2088 int OldGlueResultNo = -1, OldChainResultNo = -1;
2090 unsigned NTMNumResults = Node->getNumValues();
2091 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2092 OldGlueResultNo = NTMNumResults-1;
2093 if (NTMNumResults != 1 &&
2094 Node->getValueType(NTMNumResults-2) == MVT::Other)
2095 OldChainResultNo = NTMNumResults-2;
2096 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2097 OldChainResultNo = NTMNumResults-1;
2099 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2100 // that this deletes operands of the old node that become dead.
2101 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
2103 // MorphNodeTo can operate in two ways: if an existing node with the
2104 // specified operands exists, it can just return it. Otherwise, it
2105 // updates the node in place to have the requested operands.
2107 // If we updated the node in place, reset the node ID. To the isel,
2108 // this should be just like a newly allocated machine node.
2112 unsigned ResNumResults = Res->getNumValues();
2113 // Move the glue if needed.
2114 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2115 (unsigned)OldGlueResultNo != ResNumResults-1)
2116 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2117 SDValue(Res, ResNumResults-1));
2119 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2122 // Move the chain reference if needed.
2123 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2124 (unsigned)OldChainResultNo != ResNumResults-1)
2125 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2126 SDValue(Res, ResNumResults-1));
2128 // Otherwise, no replacement happened because the node already exists. Replace
2129 // Uses of the old node with the new one.
2131 CurDAG->ReplaceAllUsesWith(Node, Res);
2136 /// CheckSame - Implements OP_CheckSame.
2137 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2138 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2140 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2141 // Accept if it is exactly the same as a previously recorded node.
2142 unsigned RecNo = MatcherTable[MatcherIndex++];
2143 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2144 return N == RecordedNodes[RecNo].first;
2147 /// CheckChildSame - Implements OP_CheckChildXSame.
2148 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2149 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2151 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2153 if (ChildNo >= N.getNumOperands())
2154 return false; // Match fails if out of range child #.
2155 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2159 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2160 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2161 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2162 const SelectionDAGISel &SDISel) {
2163 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2166 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2167 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2168 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2169 const SelectionDAGISel &SDISel, SDNode *N) {
2170 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2173 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2174 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2176 uint16_t Opc = MatcherTable[MatcherIndex++];
2177 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2178 return N->getOpcode() == Opc;
2181 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2182 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2183 SDValue N, const TargetLowering *TLI) {
2184 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2185 if (N.getValueType() == VT) return true;
2187 // Handle the case when VT is iPTR.
2188 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2191 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2192 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2193 SDValue N, const TargetLowering *TLI,
2195 if (ChildNo >= N.getNumOperands())
2196 return false; // Match fails if out of range child #.
2197 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2200 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2201 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2203 return cast<CondCodeSDNode>(N)->get() ==
2204 (ISD::CondCode)MatcherTable[MatcherIndex++];
2207 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2208 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2209 SDValue N, const TargetLowering *TLI) {
2210 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2211 if (cast<VTSDNode>(N)->getVT() == VT)
2214 // Handle the case when VT is iPTR.
2215 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2218 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2219 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2221 int64_t Val = MatcherTable[MatcherIndex++];
2223 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2225 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2226 return C != 0 && C->getSExtValue() == Val;
2229 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2230 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2231 SDValue N, const SelectionDAGISel &SDISel) {
2232 int64_t Val = MatcherTable[MatcherIndex++];
2234 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2236 if (N->getOpcode() != ISD::AND) return false;
2238 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2239 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2242 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2243 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2244 SDValue N, const SelectionDAGISel &SDISel) {
2245 int64_t Val = MatcherTable[MatcherIndex++];
2247 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2249 if (N->getOpcode() != ISD::OR) return false;
2251 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2252 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2255 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2256 /// scope, evaluate the current node. If the current predicate is known to
2257 /// fail, set Result=true and return anything. If the current predicate is
2258 /// known to pass, set Result=false and return the MatcherIndex to continue
2259 /// with. If the current predicate is unknown, set Result=false and return the
2260 /// MatcherIndex to continue with.
2261 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2262 unsigned Index, SDValue N,
2264 const SelectionDAGISel &SDISel,
2265 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2266 switch (Table[Index++]) {
2269 return Index-1; // Could not evaluate this predicate.
2270 case SelectionDAGISel::OPC_CheckSame:
2271 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2273 case SelectionDAGISel::OPC_CheckChild0Same:
2274 case SelectionDAGISel::OPC_CheckChild1Same:
2275 case SelectionDAGISel::OPC_CheckChild2Same:
2276 case SelectionDAGISel::OPC_CheckChild3Same:
2277 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2278 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2280 case SelectionDAGISel::OPC_CheckPatternPredicate:
2281 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2283 case SelectionDAGISel::OPC_CheckPredicate:
2284 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2286 case SelectionDAGISel::OPC_CheckOpcode:
2287 Result = !::CheckOpcode(Table, Index, N.getNode());
2289 case SelectionDAGISel::OPC_CheckType:
2290 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering());
2292 case SelectionDAGISel::OPC_CheckChild0Type:
2293 case SelectionDAGISel::OPC_CheckChild1Type:
2294 case SelectionDAGISel::OPC_CheckChild2Type:
2295 case SelectionDAGISel::OPC_CheckChild3Type:
2296 case SelectionDAGISel::OPC_CheckChild4Type:
2297 case SelectionDAGISel::OPC_CheckChild5Type:
2298 case SelectionDAGISel::OPC_CheckChild6Type:
2299 case SelectionDAGISel::OPC_CheckChild7Type:
2300 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(),
2301 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2303 case SelectionDAGISel::OPC_CheckCondCode:
2304 Result = !::CheckCondCode(Table, Index, N);
2306 case SelectionDAGISel::OPC_CheckValueType:
2307 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering());
2309 case SelectionDAGISel::OPC_CheckInteger:
2310 Result = !::CheckInteger(Table, Index, N);
2312 case SelectionDAGISel::OPC_CheckAndImm:
2313 Result = !::CheckAndImm(Table, Index, N, SDISel);
2315 case SelectionDAGISel::OPC_CheckOrImm:
2316 Result = !::CheckOrImm(Table, Index, N, SDISel);
2324 /// FailIndex - If this match fails, this is the index to continue with.
2327 /// NodeStack - The node stack when the scope was formed.
2328 SmallVector<SDValue, 4> NodeStack;
2330 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2331 unsigned NumRecordedNodes;
2333 /// NumMatchedMemRefs - The number of matched memref entries.
2334 unsigned NumMatchedMemRefs;
2336 /// InputChain/InputGlue - The current chain/glue
2337 SDValue InputChain, InputGlue;
2339 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2340 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2345 SDNode *SelectionDAGISel::
2346 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2347 unsigned TableSize) {
2348 // FIXME: Should these even be selected? Handle these cases in the caller?
2349 switch (NodeToMatch->getOpcode()) {
2352 case ISD::EntryToken: // These nodes remain the same.
2353 case ISD::BasicBlock:
2355 case ISD::RegisterMask:
2356 //case ISD::VALUETYPE:
2357 //case ISD::CONDCODE:
2358 case ISD::HANDLENODE:
2359 case ISD::MDNODE_SDNODE:
2360 case ISD::TargetConstant:
2361 case ISD::TargetConstantFP:
2362 case ISD::TargetConstantPool:
2363 case ISD::TargetFrameIndex:
2364 case ISD::TargetExternalSymbol:
2365 case ISD::TargetBlockAddress:
2366 case ISD::TargetJumpTable:
2367 case ISD::TargetGlobalTLSAddress:
2368 case ISD::TargetGlobalAddress:
2369 case ISD::TokenFactor:
2370 case ISD::CopyFromReg:
2371 case ISD::CopyToReg:
2373 case ISD::LIFETIME_START:
2374 case ISD::LIFETIME_END:
2375 NodeToMatch->setNodeId(-1); // Mark selected.
2377 case ISD::AssertSext:
2378 case ISD::AssertZext:
2379 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2380 NodeToMatch->getOperand(0));
2382 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2383 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2386 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2388 // Set up the node stack with NodeToMatch as the only node on the stack.
2389 SmallVector<SDValue, 8> NodeStack;
2390 SDValue N = SDValue(NodeToMatch, 0);
2391 NodeStack.push_back(N);
2393 // MatchScopes - Scopes used when matching, if a match failure happens, this
2394 // indicates where to continue checking.
2395 SmallVector<MatchScope, 8> MatchScopes;
2397 // RecordedNodes - This is the set of nodes that have been recorded by the
2398 // state machine. The second value is the parent of the node, or null if the
2399 // root is recorded.
2400 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2402 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2404 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2406 // These are the current input chain and glue for use when generating nodes.
2407 // Various Emit operations change these. For example, emitting a copytoreg
2408 // uses and updates these.
2409 SDValue InputChain, InputGlue;
2411 // ChainNodesMatched - If a pattern matches nodes that have input/output
2412 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2413 // which ones they are. The result is captured into this list so that we can
2414 // update the chain results when the pattern is complete.
2415 SmallVector<SDNode*, 3> ChainNodesMatched;
2416 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2418 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2419 NodeToMatch->dump(CurDAG);
2422 // Determine where to start the interpreter. Normally we start at opcode #0,
2423 // but if the state machine starts with an OPC_SwitchOpcode, then we
2424 // accelerate the first lookup (which is guaranteed to be hot) with the
2425 // OpcodeOffset table.
2426 unsigned MatcherIndex = 0;
2428 if (!OpcodeOffset.empty()) {
2429 // Already computed the OpcodeOffset table, just index into it.
2430 if (N.getOpcode() < OpcodeOffset.size())
2431 MatcherIndex = OpcodeOffset[N.getOpcode()];
2432 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2434 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2435 // Otherwise, the table isn't computed, but the state machine does start
2436 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2437 // is the first time we're selecting an instruction.
2440 // Get the size of this case.
2441 unsigned CaseSize = MatcherTable[Idx++];
2443 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2444 if (CaseSize == 0) break;
2446 // Get the opcode, add the index to the table.
2447 uint16_t Opc = MatcherTable[Idx++];
2448 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2449 if (Opc >= OpcodeOffset.size())
2450 OpcodeOffset.resize((Opc+1)*2);
2451 OpcodeOffset[Opc] = Idx;
2455 // Okay, do the lookup for the first opcode.
2456 if (N.getOpcode() < OpcodeOffset.size())
2457 MatcherIndex = OpcodeOffset[N.getOpcode()];
2461 assert(MatcherIndex < TableSize && "Invalid index");
2463 unsigned CurrentOpcodeIndex = MatcherIndex;
2465 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2468 // Okay, the semantics of this operation are that we should push a scope
2469 // then evaluate the first child. However, pushing a scope only to have
2470 // the first check fail (which then pops it) is inefficient. If we can
2471 // determine immediately that the first check (or first several) will
2472 // immediately fail, don't even bother pushing a scope for them.
2476 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2477 if (NumToSkip & 128)
2478 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2479 // Found the end of the scope with no match.
2480 if (NumToSkip == 0) {
2485 FailIndex = MatcherIndex+NumToSkip;
2487 unsigned MatcherIndexOfPredicate = MatcherIndex;
2488 (void)MatcherIndexOfPredicate; // silence warning.
2490 // If we can't evaluate this predicate without pushing a scope (e.g. if
2491 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2492 // push the scope and evaluate the full predicate chain.
2494 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2495 Result, *this, RecordedNodes);
2499 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2500 << "index " << MatcherIndexOfPredicate
2501 << ", continuing at " << FailIndex << "\n");
2502 ++NumDAGIselRetries;
2504 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2505 // move to the next case.
2506 MatcherIndex = FailIndex;
2509 // If the whole scope failed to match, bail.
2510 if (FailIndex == 0) break;
2512 // Push a MatchScope which indicates where to go if the first child fails
2514 MatchScope NewEntry;
2515 NewEntry.FailIndex = FailIndex;
2516 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2517 NewEntry.NumRecordedNodes = RecordedNodes.size();
2518 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2519 NewEntry.InputChain = InputChain;
2520 NewEntry.InputGlue = InputGlue;
2521 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2522 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2523 MatchScopes.push_back(NewEntry);
2526 case OPC_RecordNode: {
2527 // Remember this node, it may end up being an operand in the pattern.
2529 if (NodeStack.size() > 1)
2530 Parent = NodeStack[NodeStack.size()-2].getNode();
2531 RecordedNodes.push_back(std::make_pair(N, Parent));
2535 case OPC_RecordChild0: case OPC_RecordChild1:
2536 case OPC_RecordChild2: case OPC_RecordChild3:
2537 case OPC_RecordChild4: case OPC_RecordChild5:
2538 case OPC_RecordChild6: case OPC_RecordChild7: {
2539 unsigned ChildNo = Opcode-OPC_RecordChild0;
2540 if (ChildNo >= N.getNumOperands())
2541 break; // Match fails if out of range child #.
2543 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2547 case OPC_RecordMemRef:
2548 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2551 case OPC_CaptureGlueInput:
2552 // If the current node has an input glue, capture it in InputGlue.
2553 if (N->getNumOperands() != 0 &&
2554 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2555 InputGlue = N->getOperand(N->getNumOperands()-1);
2558 case OPC_MoveChild: {
2559 unsigned ChildNo = MatcherTable[MatcherIndex++];
2560 if (ChildNo >= N.getNumOperands())
2561 break; // Match fails if out of range child #.
2562 N = N.getOperand(ChildNo);
2563 NodeStack.push_back(N);
2567 case OPC_MoveParent:
2568 // Pop the current node off the NodeStack.
2569 NodeStack.pop_back();
2570 assert(!NodeStack.empty() && "Node stack imbalance!");
2571 N = NodeStack.back();
2575 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2578 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2579 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2580 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2581 Opcode-OPC_CheckChild0Same))
2585 case OPC_CheckPatternPredicate:
2586 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2588 case OPC_CheckPredicate:
2589 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2593 case OPC_CheckComplexPat: {
2594 unsigned CPNum = MatcherTable[MatcherIndex++];
2595 unsigned RecNo = MatcherTable[MatcherIndex++];
2596 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2597 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2598 RecordedNodes[RecNo].first, CPNum,
2603 case OPC_CheckOpcode:
2604 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2608 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2612 case OPC_SwitchOpcode: {
2613 unsigned CurNodeOpcode = N.getOpcode();
2614 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2617 // Get the size of this case.
2618 CaseSize = MatcherTable[MatcherIndex++];
2620 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2621 if (CaseSize == 0) break;
2623 uint16_t Opc = MatcherTable[MatcherIndex++];
2624 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2626 // If the opcode matches, then we will execute this case.
2627 if (CurNodeOpcode == Opc)
2630 // Otherwise, skip over this case.
2631 MatcherIndex += CaseSize;
2634 // If no cases matched, bail out.
2635 if (CaseSize == 0) break;
2637 // Otherwise, execute the case we found.
2638 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2639 << " to " << MatcherIndex << "\n");
2643 case OPC_SwitchType: {
2644 MVT CurNodeVT = N.getSimpleValueType();
2645 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2648 // Get the size of this case.
2649 CaseSize = MatcherTable[MatcherIndex++];
2651 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2652 if (CaseSize == 0) break;
2654 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2655 if (CaseVT == MVT::iPTR)
2656 CaseVT = getTargetLowering()->getPointerTy();
2658 // If the VT matches, then we will execute this case.
2659 if (CurNodeVT == CaseVT)
2662 // Otherwise, skip over this case.
2663 MatcherIndex += CaseSize;
2666 // If no cases matched, bail out.
2667 if (CaseSize == 0) break;
2669 // Otherwise, execute the case we found.
2670 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2671 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2674 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2675 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2676 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2677 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2678 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(),
2679 Opcode-OPC_CheckChild0Type))
2682 case OPC_CheckCondCode:
2683 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2685 case OPC_CheckValueType:
2686 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2689 case OPC_CheckInteger:
2690 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2692 case OPC_CheckAndImm:
2693 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2695 case OPC_CheckOrImm:
2696 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2699 case OPC_CheckFoldableChainNode: {
2700 assert(NodeStack.size() != 1 && "No parent node");
2701 // Verify that all intermediate nodes between the root and this one have
2703 bool HasMultipleUses = false;
2704 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2705 if (!NodeStack[i].hasOneUse()) {
2706 HasMultipleUses = true;
2709 if (HasMultipleUses) break;
2711 // Check to see that the target thinks this is profitable to fold and that
2712 // we can fold it without inducing cycles in the graph.
2713 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2715 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2716 NodeToMatch, OptLevel,
2717 true/*We validate our own chains*/))
2722 case OPC_EmitInteger: {
2723 MVT::SimpleValueType VT =
2724 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2725 int64_t Val = MatcherTable[MatcherIndex++];
2727 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2728 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2729 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2732 case OPC_EmitRegister: {
2733 MVT::SimpleValueType VT =
2734 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2735 unsigned RegNo = MatcherTable[MatcherIndex++];
2736 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2737 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2740 case OPC_EmitRegister2: {
2741 // For targets w/ more than 256 register names, the register enum
2742 // values are stored in two bytes in the matcher table (just like
2744 MVT::SimpleValueType VT =
2745 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2746 unsigned RegNo = MatcherTable[MatcherIndex++];
2747 RegNo |= MatcherTable[MatcherIndex++] << 8;
2748 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2749 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2753 case OPC_EmitConvertToTarget: {
2754 // Convert from IMM/FPIMM to target version.
2755 unsigned RecNo = MatcherTable[MatcherIndex++];
2756 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2757 SDValue Imm = RecordedNodes[RecNo].first;
2759 if (Imm->getOpcode() == ISD::Constant) {
2760 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2761 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2762 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2763 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2764 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2767 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2771 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2772 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2773 // These are space-optimized forms of OPC_EmitMergeInputChains.
2774 assert(InputChain.getNode() == 0 &&
2775 "EmitMergeInputChains should be the first chain producing node");
2776 assert(ChainNodesMatched.empty() &&
2777 "Should only have one EmitMergeInputChains per match");
2779 // Read all of the chained nodes.
2780 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2781 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2782 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2784 // FIXME: What if other value results of the node have uses not matched
2786 if (ChainNodesMatched.back() != NodeToMatch &&
2787 !RecordedNodes[RecNo].first.hasOneUse()) {
2788 ChainNodesMatched.clear();
2792 // Merge the input chains if they are not intra-pattern references.
2793 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2795 if (InputChain.getNode() == 0)
2796 break; // Failed to merge.
2800 case OPC_EmitMergeInputChains: {
2801 assert(InputChain.getNode() == 0 &&
2802 "EmitMergeInputChains should be the first chain producing node");
2803 // This node gets a list of nodes we matched in the input that have
2804 // chains. We want to token factor all of the input chains to these nodes
2805 // together. However, if any of the input chains is actually one of the
2806 // nodes matched in this pattern, then we have an intra-match reference.
2807 // Ignore these because the newly token factored chain should not refer to
2809 unsigned NumChains = MatcherTable[MatcherIndex++];
2810 assert(NumChains != 0 && "Can't TF zero chains");
2812 assert(ChainNodesMatched.empty() &&
2813 "Should only have one EmitMergeInputChains per match");
2815 // Read all of the chained nodes.
2816 for (unsigned i = 0; i != NumChains; ++i) {
2817 unsigned RecNo = MatcherTable[MatcherIndex++];
2818 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2819 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2821 // FIXME: What if other value results of the node have uses not matched
2823 if (ChainNodesMatched.back() != NodeToMatch &&
2824 !RecordedNodes[RecNo].first.hasOneUse()) {
2825 ChainNodesMatched.clear();
2830 // If the inner loop broke out, the match fails.
2831 if (ChainNodesMatched.empty())
2834 // Merge the input chains if they are not intra-pattern references.
2835 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2837 if (InputChain.getNode() == 0)
2838 break; // Failed to merge.
2843 case OPC_EmitCopyToReg: {
2844 unsigned RecNo = MatcherTable[MatcherIndex++];
2845 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
2846 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2848 if (InputChain.getNode() == 0)
2849 InputChain = CurDAG->getEntryNode();
2851 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
2852 DestPhysReg, RecordedNodes[RecNo].first,
2855 InputGlue = InputChain.getValue(1);
2859 case OPC_EmitNodeXForm: {
2860 unsigned XFormNo = MatcherTable[MatcherIndex++];
2861 unsigned RecNo = MatcherTable[MatcherIndex++];
2862 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
2863 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2864 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2869 case OPC_MorphNodeTo: {
2870 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2871 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2872 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2873 // Get the result VT list.
2874 unsigned NumVTs = MatcherTable[MatcherIndex++];
2875 SmallVector<EVT, 4> VTs;
2876 for (unsigned i = 0; i != NumVTs; ++i) {
2877 MVT::SimpleValueType VT =
2878 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2879 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy;
2883 if (EmitNodeInfo & OPFL_Chain)
2884 VTs.push_back(MVT::Other);
2885 if (EmitNodeInfo & OPFL_GlueOutput)
2886 VTs.push_back(MVT::Glue);
2888 // This is hot code, so optimize the two most common cases of 1 and 2
2891 if (VTs.size() == 1)
2892 VTList = CurDAG->getVTList(VTs[0]);
2893 else if (VTs.size() == 2)
2894 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2896 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2898 // Get the operand list.
2899 unsigned NumOps = MatcherTable[MatcherIndex++];
2900 SmallVector<SDValue, 8> Ops;
2901 for (unsigned i = 0; i != NumOps; ++i) {
2902 unsigned RecNo = MatcherTable[MatcherIndex++];
2904 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2906 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2907 Ops.push_back(RecordedNodes[RecNo].first);
2910 // If there are variadic operands to add, handle them now.
2911 if (EmitNodeInfo & OPFL_VariadicInfo) {
2912 // Determine the start index to copy from.
2913 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2914 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2915 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2916 "Invalid variadic node");
2917 // Copy all of the variadic operands, not including a potential glue
2919 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2921 SDValue V = NodeToMatch->getOperand(i);
2922 if (V.getValueType() == MVT::Glue) break;
2927 // If this has chain/glue inputs, add them.
2928 if (EmitNodeInfo & OPFL_Chain)
2929 Ops.push_back(InputChain);
2930 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2931 Ops.push_back(InputGlue);
2935 if (Opcode != OPC_MorphNodeTo) {
2936 // If this is a normal EmitNode command, just create the new node and
2937 // add the results to the RecordedNodes list.
2938 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
2941 // Add all the non-glue/non-chain results to the RecordedNodes list.
2942 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2943 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2944 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2948 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2949 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2952 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2953 // We will visit the equivalent node later.
2954 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2958 // If the node had chain/glue results, update our notion of the current
2960 if (EmitNodeInfo & OPFL_GlueOutput) {
2961 InputGlue = SDValue(Res, VTs.size()-1);
2962 if (EmitNodeInfo & OPFL_Chain)
2963 InputChain = SDValue(Res, VTs.size()-2);
2964 } else if (EmitNodeInfo & OPFL_Chain)
2965 InputChain = SDValue(Res, VTs.size()-1);
2967 // If the OPFL_MemRefs glue is set on this node, slap all of the
2968 // accumulated memrefs onto it.
2970 // FIXME: This is vastly incorrect for patterns with multiple outputs
2971 // instructions that access memory and for ComplexPatterns that match
2973 if (EmitNodeInfo & OPFL_MemRefs) {
2974 // Only attach load or store memory operands if the generated
2975 // instruction may load or store.
2976 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2977 bool mayLoad = MCID.mayLoad();
2978 bool mayStore = MCID.mayStore();
2980 unsigned NumMemRefs = 0;
2981 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
2982 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2983 if ((*I)->isLoad()) {
2986 } else if ((*I)->isStore()) {
2994 MachineSDNode::mmo_iterator MemRefs =
2995 MF->allocateMemRefsArray(NumMemRefs);
2997 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2998 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
2999 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3000 if ((*I)->isLoad()) {
3003 } else if ((*I)->isStore()) {
3011 cast<MachineSDNode>(Res)
3012 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3016 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3017 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3019 // If this was a MorphNodeTo then we're completely done!
3020 if (Opcode == OPC_MorphNodeTo) {
3021 // Update chain and glue uses.
3022 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3023 InputGlue, GlueResultNodesMatched, true);
3030 case OPC_MarkGlueResults: {
3031 unsigned NumNodes = MatcherTable[MatcherIndex++];
3033 // Read and remember all the glue-result nodes.
3034 for (unsigned i = 0; i != NumNodes; ++i) {
3035 unsigned RecNo = MatcherTable[MatcherIndex++];
3037 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3039 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3040 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3045 case OPC_CompleteMatch: {
3046 // The match has been completed, and any new nodes (if any) have been
3047 // created. Patch up references to the matched dag to use the newly
3049 unsigned NumResults = MatcherTable[MatcherIndex++];
3051 for (unsigned i = 0; i != NumResults; ++i) {
3052 unsigned ResSlot = MatcherTable[MatcherIndex++];
3054 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3056 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3057 SDValue Res = RecordedNodes[ResSlot].first;
3059 assert(i < NodeToMatch->getNumValues() &&
3060 NodeToMatch->getValueType(i) != MVT::Other &&
3061 NodeToMatch->getValueType(i) != MVT::Glue &&
3062 "Invalid number of results to complete!");
3063 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3064 NodeToMatch->getValueType(i) == MVT::iPTR ||
3065 Res.getValueType() == MVT::iPTR ||
3066 NodeToMatch->getValueType(i).getSizeInBits() ==
3067 Res.getValueType().getSizeInBits()) &&
3068 "invalid replacement");
3069 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3072 // If the root node defines glue, add it to the glue nodes to update list.
3073 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3074 GlueResultNodesMatched.push_back(NodeToMatch);
3076 // Update chain and glue uses.
3077 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3078 InputGlue, GlueResultNodesMatched, false);
3080 assert(NodeToMatch->use_empty() &&
3081 "Didn't replace all uses of the node?");
3083 // FIXME: We just return here, which interacts correctly with SelectRoot
3084 // above. We should fix this to not return an SDNode* anymore.
3089 // If the code reached this point, then the match failed. See if there is
3090 // another child to try in the current 'Scope', otherwise pop it until we
3091 // find a case to check.
3092 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3093 ++NumDAGIselRetries;
3095 if (MatchScopes.empty()) {
3096 CannotYetSelect(NodeToMatch);
3100 // Restore the interpreter state back to the point where the scope was
3102 MatchScope &LastScope = MatchScopes.back();
3103 RecordedNodes.resize(LastScope.NumRecordedNodes);
3105 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3106 N = NodeStack.back();
3108 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3109 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3110 MatcherIndex = LastScope.FailIndex;
3112 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3114 InputChain = LastScope.InputChain;
3115 InputGlue = LastScope.InputGlue;
3116 if (!LastScope.HasChainNodesMatched)
3117 ChainNodesMatched.clear();
3118 if (!LastScope.HasGlueResultNodesMatched)
3119 GlueResultNodesMatched.clear();
3121 // Check to see what the offset is at the new MatcherIndex. If it is zero
3122 // we have reached the end of this scope, otherwise we have another child
3123 // in the current scope to try.
3124 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3125 if (NumToSkip & 128)
3126 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3128 // If we have another child in this scope to match, update FailIndex and
3130 if (NumToSkip != 0) {
3131 LastScope.FailIndex = MatcherIndex+NumToSkip;
3135 // End of this scope, pop it and try the next child in the containing
3137 MatchScopes.pop_back();
3144 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3146 raw_string_ostream Msg(msg);
3147 Msg << "Cannot select: ";
3149 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3150 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3151 N->getOpcode() != ISD::INTRINSIC_VOID) {
3152 N->printrFull(Msg, CurDAG);
3153 Msg << "\nIn function: " << MF->getName();
3155 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3157 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3158 if (iid < Intrinsic::num_intrinsics)
3159 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3160 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3161 Msg << "target intrinsic %" << TII->getName(iid);
3163 Msg << "unknown intrinsic #" << iid;
3165 report_fatal_error(Msg.str());
3168 char SelectionDAGISel::ID = 0;