1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/Timer.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/ADT/Statistic.h"
55 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
56 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
59 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
60 cl::desc("Enable verbose messages in the \"fast\" "
61 "instruction selector"));
63 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
64 cl::desc("Enable abort calls when \"fast\" instruction fails"));
68 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
69 cl::desc("Pop up a window to show dags before the first "
72 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
73 cl::desc("Pop up a window to show dags before legalize types"));
75 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
76 cl::desc("Pop up a window to show dags before legalize"));
78 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the second "
82 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before the post legalize types"
84 " dag combine pass"));
86 ViewISelDAGs("view-isel-dags", cl::Hidden,
87 cl::desc("Pop up a window to show isel dags as they are selected"));
89 ViewSchedDAGs("view-sched-dags", cl::Hidden,
90 cl::desc("Pop up a window to show sched dags as they are processed"));
92 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
93 cl::desc("Pop up a window to show SUnit dags after they are processed"));
95 static const bool ViewDAGCombine1 = false,
96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
97 ViewDAGCombine2 = false,
98 ViewDAGCombineLT = false,
99 ViewISelDAGs = false, ViewSchedDAGs = false,
100 ViewSUnitDAGs = false;
103 //===---------------------------------------------------------------------===//
105 /// RegisterScheduler class - Track the registration of instruction schedulers.
107 //===---------------------------------------------------------------------===//
108 MachinePassRegistry RegisterScheduler::Registry;
110 //===---------------------------------------------------------------------===//
112 /// ISHeuristic command line option for instruction schedulers.
114 //===---------------------------------------------------------------------===//
115 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
116 RegisterPassParser<RegisterScheduler> >
117 ISHeuristic("pre-RA-sched",
118 cl::init(&createDefaultScheduler),
119 cl::desc("Instruction schedulers available (before register"
122 static RegisterScheduler
123 defaultListDAGScheduler("default", "Best scheduler for the target",
124 createDefaultScheduler);
127 //===--------------------------------------------------------------------===//
128 /// createDefaultScheduler - This creates an instruction scheduler appropriate
130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
131 CodeGenOpt::Level OptLevel) {
132 const TargetLowering &TLI = IS->getTargetLowering();
134 if (OptLevel == CodeGenOpt::None)
135 return createFastDAGScheduler(IS, OptLevel);
136 if (TLI.getSchedulingPreference() == Sched::Latency)
137 return createTDListDAGScheduler(IS, OptLevel);
138 if (TLI.getSchedulingPreference() == Sched::RegPressure)
139 return createBURRListDAGScheduler(IS, OptLevel);
140 assert(TLI.getSchedulingPreference() == Sched::Hybrid &&
141 "Unknown sched type!");
142 return createHybridListDAGScheduler(IS, OptLevel);
146 // EmitInstrWithCustomInserter - This method should be implemented by targets
147 // that mark instructions with the 'usesCustomInserter' flag. These
148 // instructions are special in various ways, which require special support to
149 // insert. The specified MachineInstr is created but not inserted into any
150 // basic blocks, and this method is called to expand it into a sequence of
151 // instructions, potentially also creating new basic blocks and control flow.
152 // When new basic blocks are inserted and the edges from MBB to its successors
153 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
156 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
157 MachineBasicBlock *MBB) const {
159 dbgs() << "If a target marks an instruction with "
160 "'usesCustomInserter', it must implement "
161 "TargetLowering::EmitInstrWithCustomInserter!";
167 //===----------------------------------------------------------------------===//
168 // SelectionDAGISel code
169 //===----------------------------------------------------------------------===//
171 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
172 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
173 FuncInfo(new FunctionLoweringInfo(TLI)),
174 CurDAG(new SelectionDAG(tm)),
175 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
181 SelectionDAGISel::~SelectionDAGISel() {
187 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
188 AU.addRequired<AliasAnalysis>();
189 AU.addPreserved<AliasAnalysis>();
190 AU.addRequired<GCModuleInfo>();
191 AU.addPreserved<GCModuleInfo>();
192 MachineFunctionPass::getAnalysisUsage(AU);
195 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
196 /// other function that gcc recognizes as "returning twice". This is used to
197 /// limit code-gen optimizations on the machine function.
199 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
200 static bool FunctionCallsSetJmp(const Function *F) {
201 const Module *M = F->getParent();
202 static const char *ReturnsTwiceFns[] = {
211 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
213 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
214 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
215 if (!Callee->use_empty())
216 for (Value::const_use_iterator
217 I = Callee->use_begin(), E = Callee->use_end();
219 if (const CallInst *CI = dyn_cast<CallInst>(I))
220 if (CI->getParent()->getParent() == F)
225 #undef NUM_RETURNS_TWICE_FNS
228 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
229 // Do some sanity-checking on the command-line options.
230 assert((!EnableFastISelVerbose || EnableFastISel) &&
231 "-fast-isel-verbose requires -fast-isel");
232 assert((!EnableFastISelAbort || EnableFastISel) &&
233 "-fast-isel-abort requires -fast-isel");
235 const Function &Fn = *mf.getFunction();
236 const TargetInstrInfo &TII = *TM.getInstrInfo();
237 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
240 RegInfo = &MF->getRegInfo();
241 AA = &getAnalysis<AliasAnalysis>();
242 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
244 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
247 FuncInfo->set(Fn, *MF);
250 SelectAllBasicBlocks(Fn);
252 // If the first basic block in the function has live ins that need to be
253 // copied into vregs, emit the copies into the top of the block before
254 // emitting the code for the block.
255 MachineBasicBlock *EntryMBB = MF->begin();
256 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
258 DenseMap<unsigned, unsigned> LiveInMap;
259 if (!FuncInfo->ArgDbgValues.empty())
260 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
261 E = RegInfo->livein_end(); LI != E; ++LI)
263 LiveInMap.insert(std::make_pair(LI->first, LI->second));
265 // Insert DBG_VALUE instructions for function arguments to the entry block.
266 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
267 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
268 unsigned Reg = MI->getOperand(0).getReg();
269 if (TargetRegisterInfo::isPhysicalRegister(Reg))
270 EntryMBB->insert(EntryMBB->begin(), MI);
272 MachineInstr *Def = RegInfo->getVRegDef(Reg);
273 MachineBasicBlock::iterator InsertPos = Def;
274 // FIXME: VR def may not be in entry block.
275 Def->getParent()->insert(llvm::next(InsertPos), MI);
278 // If Reg is live-in then update debug info to track its copy in a vreg.
279 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
280 if (LDI != LiveInMap.end()) {
281 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
282 MachineBasicBlock::iterator InsertPos = Def;
283 const MDNode *Variable =
284 MI->getOperand(MI->getNumOperands()-1).getMetadata();
285 unsigned Offset = MI->getOperand(1).getImm();
286 // Def is never a terminator here, so it is ok to increment InsertPos.
287 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
288 TII.get(TargetOpcode::DBG_VALUE))
289 .addReg(LDI->second, RegState::Debug)
290 .addImm(Offset).addMetadata(Variable);
294 // Determine if there are any calls in this machine function.
295 MachineFrameInfo *MFI = MF->getFrameInfo();
296 if (!MFI->hasCalls()) {
297 for (MachineFunction::const_iterator
298 I = MF->begin(), E = MF->end(); I != E; ++I) {
299 const MachineBasicBlock *MBB = I;
300 for (MachineBasicBlock::const_iterator
301 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
302 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
303 if (II->isInlineAsm() || (TID.isCall() && !TID.isReturn())) {
304 MFI->setHasCalls(true);
312 // Determine if there is a call to setjmp in the machine function.
313 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
315 // Release function-specific state. SDB and CurDAG are already cleared
323 SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB,
324 BasicBlock::const_iterator Begin,
325 BasicBlock::const_iterator End,
327 // Lower all of the non-terminator instructions. If a call is emitted
328 // as a tail call, cease emitting nodes for this block. Terminators
329 // are handled below.
330 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
333 // Make sure the root of the DAG is up-to-date.
334 CurDAG->setRoot(SDB->getControlRoot());
335 HadTailCall = SDB->HasTailCall;
338 // Final step, emit the lowered DAG as machine code.
339 return CodeGenAndEmitDAG(BB);
343 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
344 /// nodes from the worklist.
345 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
346 SmallVector<SDNode*, 128> &Worklist;
347 SmallPtrSet<SDNode*, 128> &InWorklist;
349 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
350 SmallPtrSet<SDNode*, 128> &inwl)
351 : Worklist(wl), InWorklist(inwl) {}
353 void RemoveFromWorklist(SDNode *N) {
354 if (!InWorklist.erase(N)) return;
356 SmallVector<SDNode*, 128>::iterator I =
357 std::find(Worklist.begin(), Worklist.end(), N);
358 assert(I != Worklist.end() && "Not in worklist");
360 *I = Worklist.back();
364 virtual void NodeDeleted(SDNode *N, SDNode *E) {
365 RemoveFromWorklist(N);
368 virtual void NodeUpdated(SDNode *N) {
374 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
375 SmallPtrSet<SDNode*, 128> VisitedNodes;
376 SmallVector<SDNode*, 128> Worklist;
378 Worklist.push_back(CurDAG->getRoot().getNode());
385 SDNode *N = Worklist.pop_back_val();
387 // If we've already seen this node, ignore it.
388 if (!VisitedNodes.insert(N))
391 // Otherwise, add all chain operands to the worklist.
392 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
393 if (N->getOperand(i).getValueType() == MVT::Other)
394 Worklist.push_back(N->getOperand(i).getNode());
396 // If this is a CopyToReg with a vreg dest, process it.
397 if (N->getOpcode() != ISD::CopyToReg)
400 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
401 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
404 // Ignore non-scalar or non-integer values.
405 SDValue Src = N->getOperand(2);
406 EVT SrcVT = Src.getValueType();
407 if (!SrcVT.isInteger() || SrcVT.isVector())
410 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
411 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
412 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
414 // Only install this information if it tells us something.
415 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
416 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
417 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
418 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
419 FunctionLoweringInfo::LiveOutInfo &LOI =
420 FuncInfo->LiveOutRegInfo[DestReg];
421 LOI.NumSignBits = NumSignBits;
422 LOI.KnownOne = KnownOne;
423 LOI.KnownZero = KnownZero;
425 } while (!Worklist.empty());
428 MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) {
429 std::string GroupName;
430 if (TimePassesIsEnabled)
431 GroupName = "Instruction Selection and Scheduling";
432 std::string BlockName;
433 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
434 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
436 BlockName = MF->getFunction()->getNameStr() + ":" +
437 BB->getBasicBlock()->getNameStr();
439 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
441 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
443 // Run the DAG combiner in pre-legalize mode.
445 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
446 CurDAG->Combine(Unrestricted, *AA, OptLevel);
449 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump());
451 // Second step, hack on the DAG until it only uses operations and types that
452 // the target supports.
453 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
458 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
459 Changed = CurDAG->LegalizeTypes();
462 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump());
465 if (ViewDAGCombineLT)
466 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
468 // Run the DAG combiner in post-type-legalize mode.
470 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
471 TimePassesIsEnabled);
472 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
475 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n";
480 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
481 Changed = CurDAG->LegalizeVectors();
486 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
487 CurDAG->LegalizeTypes();
490 if (ViewDAGCombineLT)
491 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
493 // Run the DAG combiner in post-type-legalize mode.
495 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
496 TimePassesIsEnabled);
497 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
500 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n";
504 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
507 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
508 CurDAG->Legalize(OptLevel);
511 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump());
513 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
515 // Run the DAG combiner in post-legalize mode.
517 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
518 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
521 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump());
523 if (OptLevel != CodeGenOpt::None)
524 ComputeLiveOutVRegInfo();
526 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
528 // Third, instruction select all of the operations to machine code, adding the
529 // code to the MachineBasicBlock.
531 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
532 DoInstructionSelection();
535 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump());
537 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
539 // Schedule machine code.
540 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
542 NamedRegionTimer T("Instruction Scheduling", GroupName,
543 TimePassesIsEnabled);
544 Scheduler->Run(CurDAG, BB, BB->end());
547 if (ViewSUnitDAGs) Scheduler->viewGraph();
549 // Emit machine code to BB. This can change 'BB' to the last block being
552 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
553 BB = Scheduler->EmitSchedule();
556 // Free the scheduler state.
558 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
559 TimePassesIsEnabled);
563 // Free the SelectionDAG state, now that we're finished with it.
569 void SelectionDAGISel::DoInstructionSelection() {
570 DEBUG(errs() << "===== Instruction selection begins:\n");
574 // Select target instructions for the DAG.
576 // Number all nodes with a topological order and set DAGSize.
577 DAGSize = CurDAG->AssignTopologicalOrder();
579 // Create a dummy node (which is not added to allnodes), that adds
580 // a reference to the root node, preventing it from being deleted,
581 // and tracking any changes of the root.
582 HandleSDNode Dummy(CurDAG->getRoot());
583 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
586 // The AllNodes list is now topological-sorted. Visit the
587 // nodes by starting at the end of the list (the root of the
588 // graph) and preceding back toward the beginning (the entry
590 while (ISelPosition != CurDAG->allnodes_begin()) {
591 SDNode *Node = --ISelPosition;
592 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
593 // but there are currently some corner cases that it misses. Also, this
594 // makes it theoretically possible to disable the DAGCombiner.
595 if (Node->use_empty())
598 SDNode *ResNode = Select(Node);
600 // FIXME: This is pretty gross. 'Select' should be changed to not return
601 // anything at all and this code should be nuked with a tactical strike.
603 // If node should not be replaced, continue with the next one.
604 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
608 ReplaceUses(Node, ResNode);
610 // If after the replacement this node is not used any more,
611 // remove this dead node.
612 if (Node->use_empty()) { // Don't delete EntryToken, etc.
613 ISelUpdater ISU(ISelPosition);
614 CurDAG->RemoveDeadNode(Node, &ISU);
618 CurDAG->setRoot(Dummy.getValue());
621 DEBUG(errs() << "===== Instruction selection ends:\n");
623 PostprocessISelDAG();
626 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
627 /// do other setup for EH landing-pad blocks.
628 void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) {
629 // Add a label to mark the beginning of the landing pad. Deletion of the
630 // landing pad can thus be detected via the MachineModuleInfo.
631 MCSymbol *Label = MF->getMMI().addLandingPad(BB);
633 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
634 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
636 // Mark exception register as live in.
637 unsigned Reg = TLI.getExceptionAddressRegister();
638 if (Reg) BB->addLiveIn(Reg);
640 // Mark exception selector register as live in.
641 Reg = TLI.getExceptionSelectorRegister();
642 if (Reg) BB->addLiveIn(Reg);
644 // FIXME: Hack around an exception handling flaw (PR1508): the personality
645 // function and list of typeids logically belong to the invoke (or, if you
646 // like, the basic block containing the invoke), and need to be associated
647 // with it in the dwarf exception handling tables. Currently however the
648 // information is provided by an intrinsic (eh.selector) that can be moved
649 // to unexpected places by the optimizers: if the unwind edge is critical,
650 // then breaking it can result in the intrinsics being in the successor of
651 // the landing pad, not the landing pad itself. This results
652 // in exceptions not being caught because no typeids are associated with
653 // the invoke. This may not be the only way things can go wrong, but it
654 // is the only way we try to work around for the moment.
655 const BasicBlock *LLVMBB = BB->getBasicBlock();
656 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
658 if (Br && Br->isUnconditional()) { // Critical edge?
659 BasicBlock::const_iterator I, E;
660 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
661 if (isa<EHSelectorInst>(I))
665 // No catch info found - try to extract some from the successor.
666 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
670 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
671 // Initialize the Fast-ISel state, if needed.
672 FastISel *FastIS = 0;
674 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
675 FuncInfo->StaticAllocaMap,
676 FuncInfo->PHINodesToUpdate
678 , FuncInfo->CatchInfoLost
682 // Iterate over all basic blocks in the function.
683 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
684 const BasicBlock *LLVMBB = &*I;
685 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB];
687 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
688 BasicBlock::const_iterator const End = LLVMBB->end();
689 BasicBlock::const_iterator BI = Begin;
691 // Lower any arguments needed in this block if this is the entry block.
692 if (LLVMBB == &Fn.getEntryBlock())
693 LowerArguments(LLVMBB);
695 // Setup an EH landing-pad block.
696 if (BB->isLandingPad())
697 PrepareEHLandingPad(BB);
699 // Before doing SelectionDAG ISel, see if FastISel has been requested.
701 // Emit code for any incoming arguments. This must happen before
702 // beginning FastISel on the entry block.
703 if (LLVMBB == &Fn.getEntryBlock()) {
704 CurDAG->setRoot(SDB->getControlRoot());
706 BB = CodeGenAndEmitDAG(BB);
708 FastIS->startNewBlock(BB);
709 // Do FastISel on as many instructions as possible.
710 for (; BI != End; ++BI) {
712 // Defer instructions with no side effects; they'll be emitted
714 if (BI->isSafeToSpeculativelyExecute() &&
715 !FuncInfo->isExportedInst(BI))
719 // Try to select the instruction with FastISel.
720 if (FastIS->SelectInstruction(BI))
723 // Then handle certain instructions as single-LLVM-Instruction blocks.
724 if (isa<CallInst>(BI)) {
725 ++NumFastIselFailures;
726 if (EnableFastISelVerbose || EnableFastISelAbort) {
727 dbgs() << "FastISel missed call: ";
731 if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
732 unsigned &R = FuncInfo->ValueMap[BI];
734 R = FuncInfo->CreateRegs(BI->getType());
737 bool HadTailCall = false;
738 BB = SelectBasicBlock(BB, BI, llvm::next(BI), HadTailCall);
740 // If the call was emitted as a tail call, we're done with the block.
746 // If the instruction was codegen'd with multiple blocks,
747 // inform the FastISel object where to resume inserting.
748 FastIS->setCurrentBlock(BB);
752 // Otherwise, give up on FastISel for the rest of the block.
753 // For now, be a little lenient about non-branch terminators.
754 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
755 ++NumFastIselFailures;
756 if (EnableFastISelVerbose || EnableFastISelAbort) {
757 dbgs() << "FastISel miss: ";
760 if (EnableFastISelAbort)
761 // The "fast" selector couldn't handle something and bailed.
762 // For the purpose of debugging, just abort.
763 llvm_unreachable("FastISel didn't select the entire block");
769 // Run SelectionDAG instruction selection on the remainder of the block
770 // not handled by FastISel. If FastISel is not run, this is the entire
774 BB = SelectBasicBlock(BB, BI, End, HadTailCall);
777 FinishBasicBlock(BB);
778 FuncInfo->PHINodesToUpdate.clear();
785 SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) {
787 DEBUG(dbgs() << "Total amount of phi nodes to update: "
788 << FuncInfo->PHINodesToUpdate.size() << "\n";
789 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
790 dbgs() << "Node " << i << " : ("
791 << FuncInfo->PHINodesToUpdate[i].first
792 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
794 // Next, now that we know what the last MBB the LLVM BB expanded is, update
795 // PHI nodes in successors.
796 if (SDB->SwitchCases.empty() &&
797 SDB->JTCases.empty() &&
798 SDB->BitTestCases.empty()) {
799 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
800 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
801 assert(PHI->isPHI() &&
802 "This is not a machine PHI node that we are updating!");
803 if (!BB->isSuccessor(PHI->getParent()))
806 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
807 PHI->addOperand(MachineOperand::CreateMBB(BB));
812 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
813 // Lower header first, if it wasn't already lowered
814 if (!SDB->BitTestCases[i].Emitted) {
815 // Set the current basic block to the mbb we wish to insert the code into
816 BB = SDB->BitTestCases[i].Parent;
818 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB);
819 CurDAG->setRoot(SDB->getRoot());
821 BB = CodeGenAndEmitDAG(BB);
824 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
825 // Set the current basic block to the mbb we wish to insert the code into
826 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
829 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
830 SDB->BitTestCases[i].Reg,
831 SDB->BitTestCases[i].Cases[j],
834 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
835 SDB->BitTestCases[i].Reg,
836 SDB->BitTestCases[i].Cases[j],
840 CurDAG->setRoot(SDB->getRoot());
842 BB = CodeGenAndEmitDAG(BB);
846 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
848 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
849 MachineBasicBlock *PHIBB = PHI->getParent();
850 assert(PHI->isPHI() &&
851 "This is not a machine PHI node that we are updating!");
852 // This is "default" BB. We have two jumps to it. From "header" BB and
853 // from last "case" BB.
854 if (PHIBB == SDB->BitTestCases[i].Default) {
855 PHI->addOperand(MachineOperand::
856 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
858 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
859 PHI->addOperand(MachineOperand::
860 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
862 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
865 // One of "cases" BB.
866 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
868 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
869 if (cBB->isSuccessor(PHIBB)) {
870 PHI->addOperand(MachineOperand::
871 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
873 PHI->addOperand(MachineOperand::CreateMBB(cBB));
878 SDB->BitTestCases.clear();
880 // If the JumpTable record is filled in, then we need to emit a jump table.
881 // Updating the PHI nodes is tricky in this case, since we need to determine
882 // whether the PHI is a successor of the range check MBB or the jump table MBB
883 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
884 // Lower header first, if it wasn't already lowered
885 if (!SDB->JTCases[i].first.Emitted) {
886 // Set the current basic block to the mbb we wish to insert the code into
887 BB = SDB->JTCases[i].first.HeaderBB;
889 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
891 CurDAG->setRoot(SDB->getRoot());
893 BB = CodeGenAndEmitDAG(BB);
896 // Set the current basic block to the mbb we wish to insert the code into
897 BB = SDB->JTCases[i].second.MBB;
899 SDB->visitJumpTable(SDB->JTCases[i].second);
900 CurDAG->setRoot(SDB->getRoot());
902 BB = CodeGenAndEmitDAG(BB);
905 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
907 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
908 MachineBasicBlock *PHIBB = PHI->getParent();
909 assert(PHI->isPHI() &&
910 "This is not a machine PHI node that we are updating!");
911 // "default" BB. We can go there only from header BB.
912 if (PHIBB == SDB->JTCases[i].second.Default) {
914 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
917 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
919 // JT BB. Just iterate over successors here
920 if (BB->isSuccessor(PHIBB)) {
922 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
924 PHI->addOperand(MachineOperand::CreateMBB(BB));
928 SDB->JTCases.clear();
930 // If the switch block involved a branch to one of the actual successors, we
931 // need to update PHI nodes in that block.
932 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
933 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
934 assert(PHI->isPHI() &&
935 "This is not a machine PHI node that we are updating!");
936 if (BB->isSuccessor(PHI->getParent())) {
938 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
939 PHI->addOperand(MachineOperand::CreateMBB(BB));
943 // If we generated any switch lowering information, build and codegen any
944 // additional DAGs necessary.
945 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
946 // Set the current basic block to the mbb we wish to insert the code into
947 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
949 // Determine the unique successors.
950 SmallVector<MachineBasicBlock *, 2> Succs;
951 Succs.push_back(SDB->SwitchCases[i].TrueBB);
952 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
953 Succs.push_back(SDB->SwitchCases[i].FalseBB);
955 // Emit the code. Note that this could result in ThisBB being split, so
956 // we need to check for updates.
957 SDB->visitSwitchCase(SDB->SwitchCases[i], BB);
958 CurDAG->setRoot(SDB->getRoot());
960 ThisBB = CodeGenAndEmitDAG(BB);
962 // Handle any PHI nodes in successors of this chunk, as if we were coming
963 // from the original BB before switch expansion. Note that PHI nodes can
964 // occur multiple times in PHINodesToUpdate. We have to be very careful to
965 // handle them the right number of times.
966 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
968 // BB may have been removed from the CFG if a branch was constant folded.
969 if (ThisBB->isSuccessor(BB)) {
970 for (MachineBasicBlock::iterator Phi = BB->begin();
971 Phi != BB->end() && Phi->isPHI();
973 // This value for this PHI node is recorded in PHINodesToUpdate.
974 for (unsigned pn = 0; ; ++pn) {
975 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
976 "Didn't find PHI entry!");
977 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
978 Phi->addOperand(MachineOperand::
979 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
981 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
989 SDB->SwitchCases.clear();
993 /// Create the scheduler. If a specific scheduler was specified
994 /// via the SchedulerRegistry, use it, otherwise select the
995 /// one preferred by the target.
997 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
998 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1002 RegisterScheduler::setDefault(Ctor);
1005 return Ctor(this, OptLevel);
1008 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1009 return new ScheduleHazardRecognizer();
1012 //===----------------------------------------------------------------------===//
1013 // Helper functions used by the generated instruction selector.
1014 //===----------------------------------------------------------------------===//
1015 // Calls to these methods are generated by tblgen.
1017 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1018 /// the dag combiner simplified the 255, we still want to match. RHS is the
1019 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1020 /// specified in the .td file (e.g. 255).
1021 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1022 int64_t DesiredMaskS) const {
1023 const APInt &ActualMask = RHS->getAPIntValue();
1024 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1026 // If the actual mask exactly matches, success!
1027 if (ActualMask == DesiredMask)
1030 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1031 if (ActualMask.intersects(~DesiredMask))
1034 // Otherwise, the DAG Combiner may have proven that the value coming in is
1035 // either already zero or is not demanded. Check for known zero input bits.
1036 APInt NeededMask = DesiredMask & ~ActualMask;
1037 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1040 // TODO: check to see if missing bits are just not demanded.
1042 // Otherwise, this pattern doesn't match.
1046 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1047 /// the dag combiner simplified the 255, we still want to match. RHS is the
1048 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1049 /// specified in the .td file (e.g. 255).
1050 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1051 int64_t DesiredMaskS) const {
1052 const APInt &ActualMask = RHS->getAPIntValue();
1053 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1055 // If the actual mask exactly matches, success!
1056 if (ActualMask == DesiredMask)
1059 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1060 if (ActualMask.intersects(~DesiredMask))
1063 // Otherwise, the DAG Combiner may have proven that the value coming in is
1064 // either already zero or is not demanded. Check for known zero input bits.
1065 APInt NeededMask = DesiredMask & ~ActualMask;
1067 APInt KnownZero, KnownOne;
1068 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1070 // If all the missing bits in the or are already known to be set, match!
1071 if ((NeededMask & KnownOne) == NeededMask)
1074 // TODO: check to see if missing bits are just not demanded.
1076 // Otherwise, this pattern doesn't match.
1081 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1082 /// by tblgen. Others should not call it.
1083 void SelectionDAGISel::
1084 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1085 std::vector<SDValue> InOps;
1086 std::swap(InOps, Ops);
1088 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1089 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1090 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1091 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3
1093 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1094 if (InOps[e-1].getValueType() == MVT::Flag)
1095 --e; // Don't process a flag operand if it is here.
1098 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1099 if (!InlineAsm::isMemKind(Flags)) {
1100 // Just skip over this operand, copying the operands verbatim.
1101 Ops.insert(Ops.end(), InOps.begin()+i,
1102 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1103 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1105 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1106 "Memory operand with multiple values?");
1107 // Otherwise, this is a memory operand. Ask the target to select it.
1108 std::vector<SDValue> SelOps;
1109 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1110 report_fatal_error("Could not match memory address. Inline asm"
1113 // Add this to the output node.
1115 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1116 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1117 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1122 // Add the flag input back if present.
1123 if (e != InOps.size())
1124 Ops.push_back(InOps.back());
1127 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1130 static SDNode *findFlagUse(SDNode *N) {
1131 unsigned FlagResNo = N->getNumValues()-1;
1132 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1133 SDUse &Use = I.getUse();
1134 if (Use.getResNo() == FlagResNo)
1135 return Use.getUser();
1140 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1141 /// This function recursively traverses up the operand chain, ignoring
1143 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1144 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1145 bool IgnoreChains) {
1146 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1147 // greater than all of its (recursive) operands. If we scan to a point where
1148 // 'use' is smaller than the node we're scanning for, then we know we will
1151 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1152 // happen because we scan down to newly selected nodes in the case of flag
1154 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1157 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1158 // won't fail if we scan it again.
1159 if (!Visited.insert(Use))
1162 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1163 // Ignore chain uses, they are validated by HandleMergeInputChains.
1164 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1167 SDNode *N = Use->getOperand(i).getNode();
1169 if (Use == ImmedUse || Use == Root)
1170 continue; // We are not looking for immediate use.
1175 // Traverse up the operand chain.
1176 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1182 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1183 /// operand node N of U during instruction selection that starts at Root.
1184 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1185 SDNode *Root) const {
1186 if (OptLevel == CodeGenOpt::None) return false;
1187 return N.hasOneUse();
1190 /// IsLegalToFold - Returns true if the specific operand node N of
1191 /// U can be folded during instruction selection that starts at Root.
1192 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1193 CodeGenOpt::Level OptLevel,
1194 bool IgnoreChains) {
1195 if (OptLevel == CodeGenOpt::None) return false;
1197 // If Root use can somehow reach N through a path that that doesn't contain
1198 // U then folding N would create a cycle. e.g. In the following
1199 // diagram, Root can reach N through X. If N is folded into into Root, then
1200 // X is both a predecessor and a successor of U.
1211 // * indicates nodes to be folded together.
1213 // If Root produces a flag, then it gets (even more) interesting. Since it
1214 // will be "glued" together with its flag use in the scheduler, we need to
1215 // check if it might reach N.
1234 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1235 // (call it Fold), then X is a predecessor of FU and a successor of
1236 // Fold. But since Fold and FU are flagged together, this will create
1237 // a cycle in the scheduling graph.
1239 // If the node has flags, walk down the graph to the "lowest" node in the
1241 EVT VT = Root->getValueType(Root->getNumValues()-1);
1242 while (VT == MVT::Flag) {
1243 SDNode *FU = findFlagUse(Root);
1247 VT = Root->getValueType(Root->getNumValues()-1);
1249 // If our query node has a flag result with a use, we've walked up it. If
1250 // the user (which has already been selected) has a chain or indirectly uses
1251 // the chain, our WalkChainUsers predicate will not consider it. Because of
1252 // this, we cannot ignore chains in this predicate.
1253 IgnoreChains = false;
1257 SmallPtrSet<SDNode*, 16> Visited;
1258 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1261 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1262 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1263 SelectInlineAsmMemoryOperands(Ops);
1265 std::vector<EVT> VTs;
1266 VTs.push_back(MVT::Other);
1267 VTs.push_back(MVT::Flag);
1268 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1269 VTs, &Ops[0], Ops.size());
1271 return New.getNode();
1274 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1275 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1278 /// GetVBR - decode a vbr encoding whose top bit is set.
1279 ALWAYS_INLINE static uint64_t
1280 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1281 assert(Val >= 128 && "Not a VBR");
1282 Val &= 127; // Remove first vbr bit.
1287 NextBits = MatcherTable[Idx++];
1288 Val |= (NextBits&127) << Shift;
1290 } while (NextBits & 128);
1296 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1297 /// interior flag and chain results to use the new flag and chain results.
1298 void SelectionDAGISel::
1299 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1300 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1302 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1303 bool isMorphNodeTo) {
1304 SmallVector<SDNode*, 4> NowDeadNodes;
1306 ISelUpdater ISU(ISelPosition);
1308 // Now that all the normal results are replaced, we replace the chain and
1309 // flag results if present.
1310 if (!ChainNodesMatched.empty()) {
1311 assert(InputChain.getNode() != 0 &&
1312 "Matched input chains but didn't produce a chain");
1313 // Loop over all of the nodes we matched that produced a chain result.
1314 // Replace all the chain results with the final chain we ended up with.
1315 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1316 SDNode *ChainNode = ChainNodesMatched[i];
1318 // If this node was already deleted, don't look at it.
1319 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1322 // Don't replace the results of the root node if we're doing a
1324 if (ChainNode == NodeToMatch && isMorphNodeTo)
1327 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1328 if (ChainVal.getValueType() == MVT::Flag)
1329 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1330 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1331 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1333 // If the node became dead and we haven't already seen it, delete it.
1334 if (ChainNode->use_empty() &&
1335 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1336 NowDeadNodes.push_back(ChainNode);
1340 // If the result produces a flag, update any flag results in the matched
1341 // pattern with the flag result.
1342 if (InputFlag.getNode() != 0) {
1343 // Handle any interior nodes explicitly marked.
1344 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1345 SDNode *FRN = FlagResultNodesMatched[i];
1347 // If this node was already deleted, don't look at it.
1348 if (FRN->getOpcode() == ISD::DELETED_NODE)
1351 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1352 "Doesn't have a flag result");
1353 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1356 // If the node became dead and we haven't already seen it, delete it.
1357 if (FRN->use_empty() &&
1358 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1359 NowDeadNodes.push_back(FRN);
1363 if (!NowDeadNodes.empty())
1364 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1366 DEBUG(errs() << "ISEL: Match complete!\n");
1372 CR_LeadsToInteriorNode
1375 /// WalkChainUsers - Walk down the users of the specified chained node that is
1376 /// part of the pattern we're matching, looking at all of the users we find.
1377 /// This determines whether something is an interior node, whether we have a
1378 /// non-pattern node in between two pattern nodes (which prevent folding because
1379 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1380 /// between pattern nodes (in which case the TF becomes part of the pattern).
1382 /// The walk we do here is guaranteed to be small because we quickly get down to
1383 /// already selected nodes "below" us.
1385 WalkChainUsers(SDNode *ChainedNode,
1386 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1387 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1388 ChainResult Result = CR_Simple;
1390 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1391 E = ChainedNode->use_end(); UI != E; ++UI) {
1392 // Make sure the use is of the chain, not some other value we produce.
1393 if (UI.getUse().getValueType() != MVT::Other) continue;
1397 // If we see an already-selected machine node, then we've gone beyond the
1398 // pattern that we're selecting down into the already selected chunk of the
1400 if (User->isMachineOpcode() ||
1401 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1404 if (User->getOpcode() == ISD::CopyToReg ||
1405 User->getOpcode() == ISD::CopyFromReg ||
1406 User->getOpcode() == ISD::INLINEASM ||
1407 User->getOpcode() == ISD::EH_LABEL) {
1408 // If their node ID got reset to -1 then they've already been selected.
1409 // Treat them like a MachineOpcode.
1410 if (User->getNodeId() == -1)
1414 // If we have a TokenFactor, we handle it specially.
1415 if (User->getOpcode() != ISD::TokenFactor) {
1416 // If the node isn't a token factor and isn't part of our pattern, then it
1417 // must be a random chained node in between two nodes we're selecting.
1418 // This happens when we have something like:
1423 // Because we structurally match the load/store as a read/modify/write,
1424 // but the call is chained between them. We cannot fold in this case
1425 // because it would induce a cycle in the graph.
1426 if (!std::count(ChainedNodesInPattern.begin(),
1427 ChainedNodesInPattern.end(), User))
1428 return CR_InducesCycle;
1430 // Otherwise we found a node that is part of our pattern. For example in:
1434 // This would happen when we're scanning down from the load and see the
1435 // store as a user. Record that there is a use of ChainedNode that is
1436 // part of the pattern and keep scanning uses.
1437 Result = CR_LeadsToInteriorNode;
1438 InteriorChainedNodes.push_back(User);
1442 // If we found a TokenFactor, there are two cases to consider: first if the
1443 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1444 // uses of the TF are in our pattern) we just want to ignore it. Second,
1445 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1451 // | \ DAG's like cheese
1454 // [TokenFactor] [Op]
1461 // In this case, the TokenFactor becomes part of our match and we rewrite it
1462 // as a new TokenFactor.
1464 // To distinguish these two cases, do a recursive walk down the uses.
1465 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1467 // If the uses of the TokenFactor are just already-selected nodes, ignore
1468 // it, it is "below" our pattern.
1470 case CR_InducesCycle:
1471 // If the uses of the TokenFactor lead to nodes that are not part of our
1472 // pattern that are not selected, folding would turn this into a cycle,
1474 return CR_InducesCycle;
1475 case CR_LeadsToInteriorNode:
1476 break; // Otherwise, keep processing.
1479 // Okay, we know we're in the interesting interior case. The TokenFactor
1480 // is now going to be considered part of the pattern so that we rewrite its
1481 // uses (it may have uses that are not part of the pattern) with the
1482 // ultimate chain result of the generated code. We will also add its chain
1483 // inputs as inputs to the ultimate TokenFactor we create.
1484 Result = CR_LeadsToInteriorNode;
1485 ChainedNodesInPattern.push_back(User);
1486 InteriorChainedNodes.push_back(User);
1493 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1494 /// operation for when the pattern matched at least one node with a chains. The
1495 /// input vector contains a list of all of the chained nodes that we match. We
1496 /// must determine if this is a valid thing to cover (i.e. matching it won't
1497 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1498 /// be used as the input node chain for the generated nodes.
1500 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1501 SelectionDAG *CurDAG) {
1502 // Walk all of the chained nodes we've matched, recursively scanning down the
1503 // users of the chain result. This adds any TokenFactor nodes that are caught
1504 // in between chained nodes to the chained and interior nodes list.
1505 SmallVector<SDNode*, 3> InteriorChainedNodes;
1506 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1507 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1508 InteriorChainedNodes) == CR_InducesCycle)
1509 return SDValue(); // Would induce a cycle.
1512 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1513 // that we are interested in. Form our input TokenFactor node.
1514 SmallVector<SDValue, 3> InputChains;
1515 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1516 // Add the input chain of this node to the InputChains list (which will be
1517 // the operands of the generated TokenFactor) if it's not an interior node.
1518 SDNode *N = ChainNodesMatched[i];
1519 if (N->getOpcode() != ISD::TokenFactor) {
1520 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1523 // Otherwise, add the input chain.
1524 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1525 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1526 InputChains.push_back(InChain);
1530 // If we have a token factor, we want to add all inputs of the token factor
1531 // that are not part of the pattern we're matching.
1532 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1533 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1534 N->getOperand(op).getNode()))
1535 InputChains.push_back(N->getOperand(op));
1540 if (InputChains.size() == 1)
1541 return InputChains[0];
1542 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1543 MVT::Other, &InputChains[0], InputChains.size());
1546 /// MorphNode - Handle morphing a node in place for the selector.
1547 SDNode *SelectionDAGISel::
1548 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1549 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1550 // It is possible we're using MorphNodeTo to replace a node with no
1551 // normal results with one that has a normal result (or we could be
1552 // adding a chain) and the input could have flags and chains as well.
1553 // In this case we need to shift the operands down.
1554 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1555 // than the old isel though.
1556 int OldFlagResultNo = -1, OldChainResultNo = -1;
1558 unsigned NTMNumResults = Node->getNumValues();
1559 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1560 OldFlagResultNo = NTMNumResults-1;
1561 if (NTMNumResults != 1 &&
1562 Node->getValueType(NTMNumResults-2) == MVT::Other)
1563 OldChainResultNo = NTMNumResults-2;
1564 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1565 OldChainResultNo = NTMNumResults-1;
1567 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1568 // that this deletes operands of the old node that become dead.
1569 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1571 // MorphNodeTo can operate in two ways: if an existing node with the
1572 // specified operands exists, it can just return it. Otherwise, it
1573 // updates the node in place to have the requested operands.
1575 // If we updated the node in place, reset the node ID. To the isel,
1576 // this should be just like a newly allocated machine node.
1580 unsigned ResNumResults = Res->getNumValues();
1581 // Move the flag if needed.
1582 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1583 (unsigned)OldFlagResultNo != ResNumResults-1)
1584 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1585 SDValue(Res, ResNumResults-1));
1587 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1590 // Move the chain reference if needed.
1591 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1592 (unsigned)OldChainResultNo != ResNumResults-1)
1593 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1594 SDValue(Res, ResNumResults-1));
1596 // Otherwise, no replacement happened because the node already exists. Replace
1597 // Uses of the old node with the new one.
1599 CurDAG->ReplaceAllUsesWith(Node, Res);
1604 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1605 ALWAYS_INLINE static bool
1606 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1607 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1608 // Accept if it is exactly the same as a previously recorded node.
1609 unsigned RecNo = MatcherTable[MatcherIndex++];
1610 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1611 return N == RecordedNodes[RecNo];
1614 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1615 ALWAYS_INLINE static bool
1616 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1617 SelectionDAGISel &SDISel) {
1618 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1621 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1622 ALWAYS_INLINE static bool
1623 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1624 SelectionDAGISel &SDISel, SDNode *N) {
1625 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1628 ALWAYS_INLINE static bool
1629 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1631 uint16_t Opc = MatcherTable[MatcherIndex++];
1632 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1633 return N->getOpcode() == Opc;
1636 ALWAYS_INLINE static bool
1637 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1638 SDValue N, const TargetLowering &TLI) {
1639 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1640 if (N.getValueType() == VT) return true;
1642 // Handle the case when VT is iPTR.
1643 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1646 ALWAYS_INLINE static bool
1647 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1648 SDValue N, const TargetLowering &TLI,
1650 if (ChildNo >= N.getNumOperands())
1651 return false; // Match fails if out of range child #.
1652 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1656 ALWAYS_INLINE static bool
1657 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1659 return cast<CondCodeSDNode>(N)->get() ==
1660 (ISD::CondCode)MatcherTable[MatcherIndex++];
1663 ALWAYS_INLINE static bool
1664 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1665 SDValue N, const TargetLowering &TLI) {
1666 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1667 if (cast<VTSDNode>(N)->getVT() == VT)
1670 // Handle the case when VT is iPTR.
1671 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1674 ALWAYS_INLINE static bool
1675 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1677 int64_t Val = MatcherTable[MatcherIndex++];
1679 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1681 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1682 return C != 0 && C->getSExtValue() == Val;
1685 ALWAYS_INLINE static bool
1686 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1687 SDValue N, SelectionDAGISel &SDISel) {
1688 int64_t Val = MatcherTable[MatcherIndex++];
1690 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1692 if (N->getOpcode() != ISD::AND) return false;
1694 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1695 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1698 ALWAYS_INLINE static bool
1699 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1700 SDValue N, SelectionDAGISel &SDISel) {
1701 int64_t Val = MatcherTable[MatcherIndex++];
1703 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1705 if (N->getOpcode() != ISD::OR) return false;
1707 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1708 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1711 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1712 /// scope, evaluate the current node. If the current predicate is known to
1713 /// fail, set Result=true and return anything. If the current predicate is
1714 /// known to pass, set Result=false and return the MatcherIndex to continue
1715 /// with. If the current predicate is unknown, set Result=false and return the
1716 /// MatcherIndex to continue with.
1717 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1718 unsigned Index, SDValue N,
1719 bool &Result, SelectionDAGISel &SDISel,
1720 SmallVectorImpl<SDValue> &RecordedNodes){
1721 switch (Table[Index++]) {
1724 return Index-1; // Could not evaluate this predicate.
1725 case SelectionDAGISel::OPC_CheckSame:
1726 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1728 case SelectionDAGISel::OPC_CheckPatternPredicate:
1729 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1731 case SelectionDAGISel::OPC_CheckPredicate:
1732 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1734 case SelectionDAGISel::OPC_CheckOpcode:
1735 Result = !::CheckOpcode(Table, Index, N.getNode());
1737 case SelectionDAGISel::OPC_CheckType:
1738 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1740 case SelectionDAGISel::OPC_CheckChild0Type:
1741 case SelectionDAGISel::OPC_CheckChild1Type:
1742 case SelectionDAGISel::OPC_CheckChild2Type:
1743 case SelectionDAGISel::OPC_CheckChild3Type:
1744 case SelectionDAGISel::OPC_CheckChild4Type:
1745 case SelectionDAGISel::OPC_CheckChild5Type:
1746 case SelectionDAGISel::OPC_CheckChild6Type:
1747 case SelectionDAGISel::OPC_CheckChild7Type:
1748 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1749 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1751 case SelectionDAGISel::OPC_CheckCondCode:
1752 Result = !::CheckCondCode(Table, Index, N);
1754 case SelectionDAGISel::OPC_CheckValueType:
1755 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1757 case SelectionDAGISel::OPC_CheckInteger:
1758 Result = !::CheckInteger(Table, Index, N);
1760 case SelectionDAGISel::OPC_CheckAndImm:
1761 Result = !::CheckAndImm(Table, Index, N, SDISel);
1763 case SelectionDAGISel::OPC_CheckOrImm:
1764 Result = !::CheckOrImm(Table, Index, N, SDISel);
1772 /// FailIndex - If this match fails, this is the index to continue with.
1775 /// NodeStack - The node stack when the scope was formed.
1776 SmallVector<SDValue, 4> NodeStack;
1778 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1779 unsigned NumRecordedNodes;
1781 /// NumMatchedMemRefs - The number of matched memref entries.
1782 unsigned NumMatchedMemRefs;
1784 /// InputChain/InputFlag - The current chain/flag
1785 SDValue InputChain, InputFlag;
1787 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1788 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1793 SDNode *SelectionDAGISel::
1794 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1795 unsigned TableSize) {
1796 // FIXME: Should these even be selected? Handle these cases in the caller?
1797 switch (NodeToMatch->getOpcode()) {
1800 case ISD::EntryToken: // These nodes remain the same.
1801 case ISD::BasicBlock:
1803 //case ISD::VALUETYPE:
1804 //case ISD::CONDCODE:
1805 case ISD::HANDLENODE:
1806 case ISD::MDNODE_SDNODE:
1807 case ISD::TargetConstant:
1808 case ISD::TargetConstantFP:
1809 case ISD::TargetConstantPool:
1810 case ISD::TargetFrameIndex:
1811 case ISD::TargetExternalSymbol:
1812 case ISD::TargetBlockAddress:
1813 case ISD::TargetJumpTable:
1814 case ISD::TargetGlobalTLSAddress:
1815 case ISD::TargetGlobalAddress:
1816 case ISD::TokenFactor:
1817 case ISD::CopyFromReg:
1818 case ISD::CopyToReg:
1820 NodeToMatch->setNodeId(-1); // Mark selected.
1822 case ISD::AssertSext:
1823 case ISD::AssertZext:
1824 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1825 NodeToMatch->getOperand(0));
1827 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1828 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1831 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1833 // Set up the node stack with NodeToMatch as the only node on the stack.
1834 SmallVector<SDValue, 8> NodeStack;
1835 SDValue N = SDValue(NodeToMatch, 0);
1836 NodeStack.push_back(N);
1838 // MatchScopes - Scopes used when matching, if a match failure happens, this
1839 // indicates where to continue checking.
1840 SmallVector<MatchScope, 8> MatchScopes;
1842 // RecordedNodes - This is the set of nodes that have been recorded by the
1844 SmallVector<SDValue, 8> RecordedNodes;
1846 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1848 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1850 // These are the current input chain and flag for use when generating nodes.
1851 // Various Emit operations change these. For example, emitting a copytoreg
1852 // uses and updates these.
1853 SDValue InputChain, InputFlag;
1855 // ChainNodesMatched - If a pattern matches nodes that have input/output
1856 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1857 // which ones they are. The result is captured into this list so that we can
1858 // update the chain results when the pattern is complete.
1859 SmallVector<SDNode*, 3> ChainNodesMatched;
1860 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1862 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1863 NodeToMatch->dump(CurDAG);
1866 // Determine where to start the interpreter. Normally we start at opcode #0,
1867 // but if the state machine starts with an OPC_SwitchOpcode, then we
1868 // accelerate the first lookup (which is guaranteed to be hot) with the
1869 // OpcodeOffset table.
1870 unsigned MatcherIndex = 0;
1872 if (!OpcodeOffset.empty()) {
1873 // Already computed the OpcodeOffset table, just index into it.
1874 if (N.getOpcode() < OpcodeOffset.size())
1875 MatcherIndex = OpcodeOffset[N.getOpcode()];
1876 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1878 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1879 // Otherwise, the table isn't computed, but the state machine does start
1880 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1881 // is the first time we're selecting an instruction.
1884 // Get the size of this case.
1885 unsigned CaseSize = MatcherTable[Idx++];
1887 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1888 if (CaseSize == 0) break;
1890 // Get the opcode, add the index to the table.
1891 uint16_t Opc = MatcherTable[Idx++];
1892 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1893 if (Opc >= OpcodeOffset.size())
1894 OpcodeOffset.resize((Opc+1)*2);
1895 OpcodeOffset[Opc] = Idx;
1899 // Okay, do the lookup for the first opcode.
1900 if (N.getOpcode() < OpcodeOffset.size())
1901 MatcherIndex = OpcodeOffset[N.getOpcode()];
1905 assert(MatcherIndex < TableSize && "Invalid index");
1907 unsigned CurrentOpcodeIndex = MatcherIndex;
1909 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1912 // Okay, the semantics of this operation are that we should push a scope
1913 // then evaluate the first child. However, pushing a scope only to have
1914 // the first check fail (which then pops it) is inefficient. If we can
1915 // determine immediately that the first check (or first several) will
1916 // immediately fail, don't even bother pushing a scope for them.
1920 unsigned NumToSkip = MatcherTable[MatcherIndex++];
1921 if (NumToSkip & 128)
1922 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
1923 // Found the end of the scope with no match.
1924 if (NumToSkip == 0) {
1929 FailIndex = MatcherIndex+NumToSkip;
1931 unsigned MatcherIndexOfPredicate = MatcherIndex;
1932 (void)MatcherIndexOfPredicate; // silence warning.
1934 // If we can't evaluate this predicate without pushing a scope (e.g. if
1935 // it is a 'MoveParent') or if the predicate succeeds on this node, we
1936 // push the scope and evaluate the full predicate chain.
1938 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
1939 Result, *this, RecordedNodes);
1943 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
1944 << "index " << MatcherIndexOfPredicate
1945 << ", continuing at " << FailIndex << "\n");
1946 ++NumDAGIselRetries;
1948 // Otherwise, we know that this case of the Scope is guaranteed to fail,
1949 // move to the next case.
1950 MatcherIndex = FailIndex;
1953 // If the whole scope failed to match, bail.
1954 if (FailIndex == 0) break;
1956 // Push a MatchScope which indicates where to go if the first child fails
1958 MatchScope NewEntry;
1959 NewEntry.FailIndex = FailIndex;
1960 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
1961 NewEntry.NumRecordedNodes = RecordedNodes.size();
1962 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
1963 NewEntry.InputChain = InputChain;
1964 NewEntry.InputFlag = InputFlag;
1965 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
1966 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
1967 MatchScopes.push_back(NewEntry);
1970 case OPC_RecordNode:
1971 // Remember this node, it may end up being an operand in the pattern.
1972 RecordedNodes.push_back(N);
1975 case OPC_RecordChild0: case OPC_RecordChild1:
1976 case OPC_RecordChild2: case OPC_RecordChild3:
1977 case OPC_RecordChild4: case OPC_RecordChild5:
1978 case OPC_RecordChild6: case OPC_RecordChild7: {
1979 unsigned ChildNo = Opcode-OPC_RecordChild0;
1980 if (ChildNo >= N.getNumOperands())
1981 break; // Match fails if out of range child #.
1983 RecordedNodes.push_back(N->getOperand(ChildNo));
1986 case OPC_RecordMemRef:
1987 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
1990 case OPC_CaptureFlagInput:
1991 // If the current node has an input flag, capture it in InputFlag.
1992 if (N->getNumOperands() != 0 &&
1993 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
1994 InputFlag = N->getOperand(N->getNumOperands()-1);
1997 case OPC_MoveChild: {
1998 unsigned ChildNo = MatcherTable[MatcherIndex++];
1999 if (ChildNo >= N.getNumOperands())
2000 break; // Match fails if out of range child #.
2001 N = N.getOperand(ChildNo);
2002 NodeStack.push_back(N);
2006 case OPC_MoveParent:
2007 // Pop the current node off the NodeStack.
2008 NodeStack.pop_back();
2009 assert(!NodeStack.empty() && "Node stack imbalance!");
2010 N = NodeStack.back();
2014 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2016 case OPC_CheckPatternPredicate:
2017 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2019 case OPC_CheckPredicate:
2020 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2024 case OPC_CheckComplexPat: {
2025 unsigned CPNum = MatcherTable[MatcherIndex++];
2026 unsigned RecNo = MatcherTable[MatcherIndex++];
2027 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2028 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2033 case OPC_CheckOpcode:
2034 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2038 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2041 case OPC_SwitchOpcode: {
2042 unsigned CurNodeOpcode = N.getOpcode();
2043 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2046 // Get the size of this case.
2047 CaseSize = MatcherTable[MatcherIndex++];
2049 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2050 if (CaseSize == 0) break;
2052 uint16_t Opc = MatcherTable[MatcherIndex++];
2053 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2055 // If the opcode matches, then we will execute this case.
2056 if (CurNodeOpcode == Opc)
2059 // Otherwise, skip over this case.
2060 MatcherIndex += CaseSize;
2063 // If no cases matched, bail out.
2064 if (CaseSize == 0) break;
2066 // Otherwise, execute the case we found.
2067 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2068 << " to " << MatcherIndex << "\n");
2072 case OPC_SwitchType: {
2073 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2074 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2077 // Get the size of this case.
2078 CaseSize = MatcherTable[MatcherIndex++];
2080 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2081 if (CaseSize == 0) break;
2083 MVT::SimpleValueType CaseVT =
2084 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2085 if (CaseVT == MVT::iPTR)
2086 CaseVT = TLI.getPointerTy().SimpleTy;
2088 // If the VT matches, then we will execute this case.
2089 if (CurNodeVT == CaseVT)
2092 // Otherwise, skip over this case.
2093 MatcherIndex += CaseSize;
2096 // If no cases matched, bail out.
2097 if (CaseSize == 0) break;
2099 // Otherwise, execute the case we found.
2100 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2101 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2104 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2105 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2106 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2107 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2108 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2109 Opcode-OPC_CheckChild0Type))
2112 case OPC_CheckCondCode:
2113 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2115 case OPC_CheckValueType:
2116 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2118 case OPC_CheckInteger:
2119 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2121 case OPC_CheckAndImm:
2122 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2124 case OPC_CheckOrImm:
2125 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2128 case OPC_CheckFoldableChainNode: {
2129 assert(NodeStack.size() != 1 && "No parent node");
2130 // Verify that all intermediate nodes between the root and this one have
2132 bool HasMultipleUses = false;
2133 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2134 if (!NodeStack[i].hasOneUse()) {
2135 HasMultipleUses = true;
2138 if (HasMultipleUses) break;
2140 // Check to see that the target thinks this is profitable to fold and that
2141 // we can fold it without inducing cycles in the graph.
2142 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2144 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2145 NodeToMatch, OptLevel,
2146 true/*We validate our own chains*/))
2151 case OPC_EmitInteger: {
2152 MVT::SimpleValueType VT =
2153 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2154 int64_t Val = MatcherTable[MatcherIndex++];
2156 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2157 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2160 case OPC_EmitRegister: {
2161 MVT::SimpleValueType VT =
2162 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2163 unsigned RegNo = MatcherTable[MatcherIndex++];
2164 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2168 case OPC_EmitConvertToTarget: {
2169 // Convert from IMM/FPIMM to target version.
2170 unsigned RecNo = MatcherTable[MatcherIndex++];
2171 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2172 SDValue Imm = RecordedNodes[RecNo];
2174 if (Imm->getOpcode() == ISD::Constant) {
2175 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2176 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2177 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2178 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2179 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2182 RecordedNodes.push_back(Imm);
2186 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2187 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2188 // These are space-optimized forms of OPC_EmitMergeInputChains.
2189 assert(InputChain.getNode() == 0 &&
2190 "EmitMergeInputChains should be the first chain producing node");
2191 assert(ChainNodesMatched.empty() &&
2192 "Should only have one EmitMergeInputChains per match");
2194 // Read all of the chained nodes.
2195 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2196 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2197 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2199 // FIXME: What if other value results of the node have uses not matched
2201 if (ChainNodesMatched.back() != NodeToMatch &&
2202 !RecordedNodes[RecNo].hasOneUse()) {
2203 ChainNodesMatched.clear();
2207 // Merge the input chains if they are not intra-pattern references.
2208 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2210 if (InputChain.getNode() == 0)
2211 break; // Failed to merge.
2215 case OPC_EmitMergeInputChains: {
2216 assert(InputChain.getNode() == 0 &&
2217 "EmitMergeInputChains should be the first chain producing node");
2218 // This node gets a list of nodes we matched in the input that have
2219 // chains. We want to token factor all of the input chains to these nodes
2220 // together. However, if any of the input chains is actually one of the
2221 // nodes matched in this pattern, then we have an intra-match reference.
2222 // Ignore these because the newly token factored chain should not refer to
2224 unsigned NumChains = MatcherTable[MatcherIndex++];
2225 assert(NumChains != 0 && "Can't TF zero chains");
2227 assert(ChainNodesMatched.empty() &&
2228 "Should only have one EmitMergeInputChains per match");
2230 // Read all of the chained nodes.
2231 for (unsigned i = 0; i != NumChains; ++i) {
2232 unsigned RecNo = MatcherTable[MatcherIndex++];
2233 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2234 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2236 // FIXME: What if other value results of the node have uses not matched
2238 if (ChainNodesMatched.back() != NodeToMatch &&
2239 !RecordedNodes[RecNo].hasOneUse()) {
2240 ChainNodesMatched.clear();
2245 // If the inner loop broke out, the match fails.
2246 if (ChainNodesMatched.empty())
2249 // Merge the input chains if they are not intra-pattern references.
2250 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2252 if (InputChain.getNode() == 0)
2253 break; // Failed to merge.
2258 case OPC_EmitCopyToReg: {
2259 unsigned RecNo = MatcherTable[MatcherIndex++];
2260 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2261 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2263 if (InputChain.getNode() == 0)
2264 InputChain = CurDAG->getEntryNode();
2266 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2267 DestPhysReg, RecordedNodes[RecNo],
2270 InputFlag = InputChain.getValue(1);
2274 case OPC_EmitNodeXForm: {
2275 unsigned XFormNo = MatcherTable[MatcherIndex++];
2276 unsigned RecNo = MatcherTable[MatcherIndex++];
2277 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2278 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2283 case OPC_MorphNodeTo: {
2284 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2285 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2286 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2287 // Get the result VT list.
2288 unsigned NumVTs = MatcherTable[MatcherIndex++];
2289 SmallVector<EVT, 4> VTs;
2290 for (unsigned i = 0; i != NumVTs; ++i) {
2291 MVT::SimpleValueType VT =
2292 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2293 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2297 if (EmitNodeInfo & OPFL_Chain)
2298 VTs.push_back(MVT::Other);
2299 if (EmitNodeInfo & OPFL_FlagOutput)
2300 VTs.push_back(MVT::Flag);
2302 // This is hot code, so optimize the two most common cases of 1 and 2
2305 if (VTs.size() == 1)
2306 VTList = CurDAG->getVTList(VTs[0]);
2307 else if (VTs.size() == 2)
2308 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2310 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2312 // Get the operand list.
2313 unsigned NumOps = MatcherTable[MatcherIndex++];
2314 SmallVector<SDValue, 8> Ops;
2315 for (unsigned i = 0; i != NumOps; ++i) {
2316 unsigned RecNo = MatcherTable[MatcherIndex++];
2318 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2320 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2321 Ops.push_back(RecordedNodes[RecNo]);
2324 // If there are variadic operands to add, handle them now.
2325 if (EmitNodeInfo & OPFL_VariadicInfo) {
2326 // Determine the start index to copy from.
2327 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2328 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2329 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2330 "Invalid variadic node");
2331 // Copy all of the variadic operands, not including a potential flag
2333 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2335 SDValue V = NodeToMatch->getOperand(i);
2336 if (V.getValueType() == MVT::Flag) break;
2341 // If this has chain/flag inputs, add them.
2342 if (EmitNodeInfo & OPFL_Chain)
2343 Ops.push_back(InputChain);
2344 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2345 Ops.push_back(InputFlag);
2349 if (Opcode != OPC_MorphNodeTo) {
2350 // If this is a normal EmitNode command, just create the new node and
2351 // add the results to the RecordedNodes list.
2352 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2353 VTList, Ops.data(), Ops.size());
2355 // Add all the non-flag/non-chain results to the RecordedNodes list.
2356 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2357 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2358 RecordedNodes.push_back(SDValue(Res, i));
2362 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2366 // If the node had chain/flag results, update our notion of the current
2368 if (EmitNodeInfo & OPFL_FlagOutput) {
2369 InputFlag = SDValue(Res, VTs.size()-1);
2370 if (EmitNodeInfo & OPFL_Chain)
2371 InputChain = SDValue(Res, VTs.size()-2);
2372 } else if (EmitNodeInfo & OPFL_Chain)
2373 InputChain = SDValue(Res, VTs.size()-1);
2375 // If the OPFL_MemRefs flag is set on this node, slap all of the
2376 // accumulated memrefs onto it.
2378 // FIXME: This is vastly incorrect for patterns with multiple outputs
2379 // instructions that access memory and for ComplexPatterns that match
2381 if (EmitNodeInfo & OPFL_MemRefs) {
2382 MachineSDNode::mmo_iterator MemRefs =
2383 MF->allocateMemRefsArray(MatchedMemRefs.size());
2384 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2385 cast<MachineSDNode>(Res)
2386 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2390 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2391 << " node: "; Res->dump(CurDAG); errs() << "\n");
2393 // If this was a MorphNodeTo then we're completely done!
2394 if (Opcode == OPC_MorphNodeTo) {
2395 // Update chain and flag uses.
2396 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2397 InputFlag, FlagResultNodesMatched, true);
2404 case OPC_MarkFlagResults: {
2405 unsigned NumNodes = MatcherTable[MatcherIndex++];
2407 // Read and remember all the flag-result nodes.
2408 for (unsigned i = 0; i != NumNodes; ++i) {
2409 unsigned RecNo = MatcherTable[MatcherIndex++];
2411 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2413 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2414 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2419 case OPC_CompleteMatch: {
2420 // The match has been completed, and any new nodes (if any) have been
2421 // created. Patch up references to the matched dag to use the newly
2423 unsigned NumResults = MatcherTable[MatcherIndex++];
2425 for (unsigned i = 0; i != NumResults; ++i) {
2426 unsigned ResSlot = MatcherTable[MatcherIndex++];
2428 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2430 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2431 SDValue Res = RecordedNodes[ResSlot];
2433 assert(i < NodeToMatch->getNumValues() &&
2434 NodeToMatch->getValueType(i) != MVT::Other &&
2435 NodeToMatch->getValueType(i) != MVT::Flag &&
2436 "Invalid number of results to complete!");
2437 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2438 NodeToMatch->getValueType(i) == MVT::iPTR ||
2439 Res.getValueType() == MVT::iPTR ||
2440 NodeToMatch->getValueType(i).getSizeInBits() ==
2441 Res.getValueType().getSizeInBits()) &&
2442 "invalid replacement");
2443 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2446 // If the root node defines a flag, add it to the flag nodes to update
2448 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2449 FlagResultNodesMatched.push_back(NodeToMatch);
2451 // Update chain and flag uses.
2452 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2453 InputFlag, FlagResultNodesMatched, false);
2455 assert(NodeToMatch->use_empty() &&
2456 "Didn't replace all uses of the node?");
2458 // FIXME: We just return here, which interacts correctly with SelectRoot
2459 // above. We should fix this to not return an SDNode* anymore.
2464 // If the code reached this point, then the match failed. See if there is
2465 // another child to try in the current 'Scope', otherwise pop it until we
2466 // find a case to check.
2467 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2468 ++NumDAGIselRetries;
2470 if (MatchScopes.empty()) {
2471 CannotYetSelect(NodeToMatch);
2475 // Restore the interpreter state back to the point where the scope was
2477 MatchScope &LastScope = MatchScopes.back();
2478 RecordedNodes.resize(LastScope.NumRecordedNodes);
2480 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2481 N = NodeStack.back();
2483 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2484 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2485 MatcherIndex = LastScope.FailIndex;
2487 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2489 InputChain = LastScope.InputChain;
2490 InputFlag = LastScope.InputFlag;
2491 if (!LastScope.HasChainNodesMatched)
2492 ChainNodesMatched.clear();
2493 if (!LastScope.HasFlagResultNodesMatched)
2494 FlagResultNodesMatched.clear();
2496 // Check to see what the offset is at the new MatcherIndex. If it is zero
2497 // we have reached the end of this scope, otherwise we have another child
2498 // in the current scope to try.
2499 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2500 if (NumToSkip & 128)
2501 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2503 // If we have another child in this scope to match, update FailIndex and
2505 if (NumToSkip != 0) {
2506 LastScope.FailIndex = MatcherIndex+NumToSkip;
2510 // End of this scope, pop it and try the next child in the containing
2512 MatchScopes.pop_back();
2519 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2521 raw_string_ostream Msg(msg);
2522 Msg << "Cannot yet select: ";
2524 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2525 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2526 N->getOpcode() != ISD::INTRINSIC_VOID) {
2527 N->printrFull(Msg, CurDAG);
2529 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2531 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2532 if (iid < Intrinsic::num_intrinsics)
2533 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2534 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2535 Msg << "target intrinsic %" << TII->getName(iid);
2537 Msg << "unknown intrinsic #" << iid;
2539 report_fatal_error(Msg.str());
2542 char SelectionDAGISel::ID = 0;