1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/Constants.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/GlobalVariable.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/ParameterAttributes.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleDAG.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetData.h"
42 #include "llvm/Target/TargetFrameInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLowering.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/Timer.h"
55 EnableValueProp("enable-value-prop", cl::Hidden);
57 EnableLegalizeTypes("enable-legalize-types", cl::Hidden);
59 EnableFastISel("fast-isel", cl::Hidden,
60 cl::desc("Enable the experimental \"fast\" instruction selector"));
62 DisableFastISelAbort("fast-isel-no-abort", cl::Hidden,
63 cl::desc("Use the SelectionDAGISel when \"fast\" instruction "
68 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
69 cl::desc("Pop up a window to show dags before the first "
72 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
73 cl::desc("Pop up a window to show dags before legalize types"));
75 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
76 cl::desc("Pop up a window to show dags before legalize"));
78 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the second "
82 ViewISelDAGs("view-isel-dags", cl::Hidden,
83 cl::desc("Pop up a window to show isel dags as they are selected"));
85 ViewSchedDAGs("view-sched-dags", cl::Hidden,
86 cl::desc("Pop up a window to show sched dags as they are processed"));
88 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
89 cl::desc("Pop up a window to show SUnit dags after they are processed"));
91 static const bool ViewDAGCombine1 = false,
92 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
93 ViewDAGCombine2 = false,
94 ViewISelDAGs = false, ViewSchedDAGs = false,
95 ViewSUnitDAGs = false;
98 //===---------------------------------------------------------------------===//
100 /// RegisterScheduler class - Track the registration of instruction schedulers.
102 //===---------------------------------------------------------------------===//
103 MachinePassRegistry RegisterScheduler::Registry;
105 //===---------------------------------------------------------------------===//
107 /// ISHeuristic command line option for instruction schedulers.
109 //===---------------------------------------------------------------------===//
110 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
111 RegisterPassParser<RegisterScheduler> >
112 ISHeuristic("pre-RA-sched",
113 cl::init(&createDefaultScheduler),
114 cl::desc("Instruction schedulers available (before register"
117 static RegisterScheduler
118 defaultListDAGScheduler("default", " Best scheduler for the target",
119 createDefaultScheduler);
121 namespace { struct SDISelAsmOperandInfo; }
123 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
124 /// insertvalue or extractvalue indices that identify a member, return
125 /// the linearized index of the start of the member.
127 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
128 const unsigned *Indices,
129 const unsigned *IndicesEnd,
130 unsigned CurIndex = 0) {
131 // Base case: We're done.
132 if (Indices && Indices == IndicesEnd)
135 // Given a struct type, recursively traverse the elements.
136 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
137 for (StructType::element_iterator EB = STy->element_begin(),
139 EE = STy->element_end();
141 if (Indices && *Indices == unsigned(EI - EB))
142 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
143 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
146 // Given an array type, recursively traverse the elements.
147 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
148 const Type *EltTy = ATy->getElementType();
149 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
150 if (Indices && *Indices == i)
151 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
152 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
155 // We haven't found the type we're looking for, so keep searching.
159 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
160 /// MVTs that represent all the individual underlying
161 /// non-aggregate types that comprise it.
163 /// If Offsets is non-null, it points to a vector to be filled in
164 /// with the in-memory offsets of each of the individual values.
166 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
167 SmallVectorImpl<MVT> &ValueVTs,
168 SmallVectorImpl<uint64_t> *Offsets = 0,
169 uint64_t StartingOffset = 0) {
170 // Given a struct type, recursively traverse the elements.
171 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
172 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
173 for (StructType::element_iterator EB = STy->element_begin(),
175 EE = STy->element_end();
177 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
178 StartingOffset + SL->getElementOffset(EI - EB));
181 // Given an array type, recursively traverse the elements.
182 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
183 const Type *EltTy = ATy->getElementType();
184 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
185 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
186 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
187 StartingOffset + i * EltSize);
190 // Base case: we can get an MVT for this LLVM IR type.
191 ValueVTs.push_back(TLI.getValueType(Ty));
193 Offsets->push_back(StartingOffset);
197 /// RegsForValue - This struct represents the registers (physical or virtual)
198 /// that a particular set of values is assigned, and the type information about
199 /// the value. The most common situation is to represent one value at a time,
200 /// but struct or array values are handled element-wise as multiple values.
201 /// The splitting of aggregates is performed recursively, so that we never
202 /// have aggregate-typed registers. The values at this point do not necessarily
203 /// have legal types, so each value may require one or more registers of some
206 struct VISIBILITY_HIDDEN RegsForValue {
207 /// TLI - The TargetLowering object.
209 const TargetLowering *TLI;
211 /// ValueVTs - The value types of the values, which may not be legal, and
212 /// may need be promoted or synthesized from one or more registers.
214 SmallVector<MVT, 4> ValueVTs;
216 /// RegVTs - The value types of the registers. This is the same size as
217 /// ValueVTs and it records, for each value, what the type of the assigned
218 /// register or registers are. (Individual values are never synthesized
219 /// from more than one type of register.)
221 /// With virtual registers, the contents of RegVTs is redundant with TLI's
222 /// getRegisterType member function, however when with physical registers
223 /// it is necessary to have a separate record of the types.
225 SmallVector<MVT, 4> RegVTs;
227 /// Regs - This list holds the registers assigned to the values.
228 /// Each legal or promoted value requires one register, and each
229 /// expanded value requires multiple registers.
231 SmallVector<unsigned, 4> Regs;
233 RegsForValue() : TLI(0) {}
235 RegsForValue(const TargetLowering &tli,
236 const SmallVector<unsigned, 4> ®s,
237 MVT regvt, MVT valuevt)
238 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
239 RegsForValue(const TargetLowering &tli,
240 const SmallVector<unsigned, 4> ®s,
241 const SmallVector<MVT, 4> ®vts,
242 const SmallVector<MVT, 4> &valuevts)
243 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
244 RegsForValue(const TargetLowering &tli,
245 unsigned Reg, const Type *Ty) : TLI(&tli) {
246 ComputeValueVTs(tli, Ty, ValueVTs);
248 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
249 MVT ValueVT = ValueVTs[Value];
250 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
251 MVT RegisterVT = TLI->getRegisterType(ValueVT);
252 for (unsigned i = 0; i != NumRegs; ++i)
253 Regs.push_back(Reg + i);
254 RegVTs.push_back(RegisterVT);
259 /// append - Add the specified values to this one.
260 void append(const RegsForValue &RHS) {
262 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
263 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
264 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
268 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
269 /// this value and returns the result as a ValueVTs value. This uses
270 /// Chain/Flag as the input and updates them for the output Chain/Flag.
271 /// If the Flag pointer is NULL, no flag is used.
272 SDValue getCopyFromRegs(SelectionDAG &DAG,
273 SDValue &Chain, SDValue *Flag) const;
275 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
276 /// specified value into the registers specified by this object. This uses
277 /// Chain/Flag as the input and updates them for the output Chain/Flag.
278 /// If the Flag pointer is NULL, no flag is used.
279 void getCopyToRegs(SDValue Val, SelectionDAG &DAG,
280 SDValue &Chain, SDValue *Flag) const;
282 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
283 /// operand list. This adds the code marker and includes the number of
284 /// values added into it.
285 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
286 std::vector<SDValue> &Ops) const;
291 //===--------------------------------------------------------------------===//
292 /// createDefaultScheduler - This creates an instruction scheduler appropriate
294 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
296 MachineBasicBlock *BB,
298 TargetLowering &TLI = IS->getTargetLowering();
300 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
301 return createTDListDAGScheduler(IS, DAG, BB, Fast);
303 assert(TLI.getSchedulingPreference() ==
304 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
305 return createBURRListDAGScheduler(IS, DAG, BB, Fast);
310 //===--------------------------------------------------------------------===//
311 /// FunctionLoweringInfo - This contains information that is global to a
312 /// function that is used when lowering a region of the function.
313 class FunctionLoweringInfo {
318 MachineRegisterInfo *RegInfo;
320 explicit FunctionLoweringInfo(TargetLowering &TLI);
322 /// set - Initialize this FunctionLoweringInfo with the given Function
323 /// and its associated MachineFunction.
325 void set(Function &Fn, MachineFunction &MF);
327 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
328 DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
330 /// ValueMap - Since we emit code for the function a basic block at a time,
331 /// we must remember which virtual registers hold the values for
332 /// cross-basic-block values.
333 DenseMap<const Value*, unsigned> ValueMap;
335 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
336 /// the entry block. This allows the allocas to be efficiently referenced
337 /// anywhere in the function.
338 DenseMap<const AllocaInst*, int> StaticAllocaMap;
341 SmallSet<Instruction*, 8> CatchInfoLost;
342 SmallSet<Instruction*, 8> CatchInfoFound;
345 unsigned MakeReg(MVT VT) {
346 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
349 /// isExportedInst - Return true if the specified value is an instruction
350 /// exported from its block.
351 bool isExportedInst(const Value *V) {
352 return ValueMap.count(V);
355 unsigned CreateRegForValue(const Value *V);
357 unsigned InitializeRegForValue(const Value *V) {
358 unsigned &R = ValueMap[V];
359 assert(R == 0 && "Already initialized this value register!");
360 return R = CreateRegForValue(V);
364 unsigned NumSignBits;
365 APInt KnownOne, KnownZero;
366 LiveOutInfo() : NumSignBits(0) {}
369 /// LiveOutRegInfo - Information about live out vregs, indexed by their
370 /// register number offset by 'FirstVirtualRegister'.
371 std::vector<LiveOutInfo> LiveOutRegInfo;
373 /// clear - Clear out all the function-specific state. This returns this
374 /// FunctionLoweringInfo to an empty state, ready to be used for a
375 /// different function.
379 StaticAllocaMap.clear();
381 CatchInfoLost.clear();
382 CatchInfoFound.clear();
384 LiveOutRegInfo.clear();
389 /// isSelector - Return true if this instruction is a call to the
390 /// eh.selector intrinsic.
391 static bool isSelector(Instruction *I) {
392 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
393 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
394 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
398 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
399 /// PHI nodes or outside of the basic block that defines it, or used by a
400 /// switch or atomic instruction, which may expand to multiple basic blocks.
401 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
402 if (isa<PHINode>(I)) return true;
403 BasicBlock *BB = I->getParent();
404 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
405 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
406 // FIXME: Remove switchinst special case.
407 isa<SwitchInst>(*UI))
412 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
413 /// entry block, return true. This includes arguments used by switches, since
414 /// the switch may expand into multiple basic blocks.
415 static bool isOnlyUsedInEntryBlock(Argument *A) {
416 // With FastISel active, we may be splitting blocks, so force creation
417 // of virtual registers for all non-dead arguments.
419 return A->use_empty();
421 BasicBlock *Entry = A->getParent()->begin();
422 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
423 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
424 return false; // Use not in entry block.
428 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
432 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf) {
435 RegInfo = &MF->getRegInfo();
437 // Create a vreg for each argument register that is not dead and is used
438 // outside of the entry block for the function.
439 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
441 if (!isOnlyUsedInEntryBlock(AI))
442 InitializeRegForValue(AI);
444 // Initialize the mapping of values to registers. This is only set up for
445 // instruction values that are used outside of the block that defines
447 Function::iterator BB = Fn->begin(), EB = Fn->end();
448 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
449 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
450 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
451 const Type *Ty = AI->getAllocatedType();
452 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
454 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
457 TySize *= CUI->getZExtValue(); // Get total allocated size.
458 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
459 StaticAllocaMap[AI] =
460 MF->getFrameInfo()->CreateStackObject(TySize, Align);
463 for (; BB != EB; ++BB)
464 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
465 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
466 if (!isa<AllocaInst>(I) ||
467 !StaticAllocaMap.count(cast<AllocaInst>(I)))
468 InitializeRegForValue(I);
470 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
471 // also creates the initial PHI MachineInstrs, though none of the input
472 // operands are populated.
473 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
474 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
478 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
481 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
482 if (PN->use_empty()) continue;
484 unsigned PHIReg = ValueMap[PN];
485 assert(PHIReg && "PHI node does not have an assigned virtual register!");
487 SmallVector<MVT, 4> ValueVTs;
488 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
489 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
490 MVT VT = ValueVTs[vti];
491 unsigned NumRegisters = TLI.getNumRegisters(VT);
492 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
493 for (unsigned i = 0; i != NumRegisters; ++i)
494 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
495 PHIReg += NumRegisters;
501 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
502 /// the correctly promoted or expanded types. Assign these registers
503 /// consecutive vreg numbers and return the first assigned number.
505 /// In the case that the given value has struct or array type, this function
506 /// will assign registers for each member or element.
508 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
509 SmallVector<MVT, 4> ValueVTs;
510 ComputeValueVTs(TLI, V->getType(), ValueVTs);
512 unsigned FirstReg = 0;
513 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
514 MVT ValueVT = ValueVTs[Value];
515 MVT RegisterVT = TLI.getRegisterType(ValueVT);
517 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
518 for (unsigned i = 0; i != NumRegs; ++i) {
519 unsigned R = MakeReg(RegisterVT);
520 if (!FirstReg) FirstReg = R;
528 /// CaseBlock - This structure is used to communicate between SDLowering and
529 /// SDISel for the code generation of additional basic blocks needed by multi-
530 /// case switch statements.
532 CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
533 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
534 MachineBasicBlock *me)
535 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
536 TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
537 // CC - the condition code to use for the case block's setcc node
539 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
540 // Emit by default LHS op RHS. MHS is used for range comparisons:
541 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
542 Value *CmpLHS, *CmpMHS, *CmpRHS;
543 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
544 MachineBasicBlock *TrueBB, *FalseBB;
545 // ThisBB - the block into which to emit the code for the setcc and branches
546 MachineBasicBlock *ThisBB;
549 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
550 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
552 /// Reg - the virtual register containing the index of the jump table entry
555 /// JTI - the JumpTableIndex for this jump table in the function.
557 /// MBB - the MBB into which to emit the code for the indirect jump.
558 MachineBasicBlock *MBB;
559 /// Default - the MBB of the default bb, which is a successor of the range
560 /// check MBB. This is when updating PHI nodes in successors.
561 MachineBasicBlock *Default;
563 struct JumpTableHeader {
564 JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
566 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
570 MachineBasicBlock *HeaderBB;
573 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
576 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
577 Mask(M), ThisBB(T), TargetBB(Tr) { }
579 MachineBasicBlock* ThisBB;
580 MachineBasicBlock* TargetBB;
583 typedef SmallVector<BitTestCase, 3> BitTestInfo;
585 struct BitTestBlock {
586 BitTestBlock(uint64_t F, uint64_t R, Value* SV,
588 MachineBasicBlock* P, MachineBasicBlock* D,
589 const BitTestInfo& C):
590 First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
591 Parent(P), Default(D), Cases(C) { }
597 MachineBasicBlock *Parent;
598 MachineBasicBlock *Default;
602 } // end anonymous namespace
604 //===----------------------------------------------------------------------===//
605 /// SelectionDAGLowering - This is the common target-independent lowering
606 /// implementation that is parameterized by a TargetLowering object.
607 /// Also, targets can overload any lowering method.
610 class SelectionDAGLowering {
611 MachineBasicBlock *CurMBB;
613 DenseMap<const Value*, SDValue> NodeMap;
615 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
616 /// them up and then emit token factor nodes when possible. This allows us to
617 /// get simple disambiguation between loads without worrying about alias
619 SmallVector<SDValue, 8> PendingLoads;
621 /// PendingExports - CopyToReg nodes that copy values to virtual registers
622 /// for export to other blocks need to be emitted before any terminator
623 /// instruction, but they have no other ordering requirements. We bunch them
624 /// up and the emit a single tokenfactor for them just before terminator
626 SmallVector<SDValue, 8> PendingExports;
628 /// Case - A struct to record the Value for a switch case, and the
629 /// case's target basic block.
633 MachineBasicBlock* BB;
635 Case() : Low(0), High(0), BB(0) { }
636 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
637 Low(low), High(high), BB(bb) { }
638 uint64_t size() const {
639 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
640 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
641 return (rHigh - rLow + 1ULL);
647 MachineBasicBlock* BB;
650 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
651 Mask(mask), BB(bb), Bits(bits) { }
654 typedef std::vector<Case> CaseVector;
655 typedef std::vector<CaseBits> CaseBitsVector;
656 typedef CaseVector::iterator CaseItr;
657 typedef std::pair<CaseItr, CaseItr> CaseRange;
659 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
660 /// of conditional branches.
662 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
663 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
665 /// CaseBB - The MBB in which to emit the compare and branch
666 MachineBasicBlock *CaseBB;
667 /// LT, GE - If nonzero, we know the current case value must be less-than or
668 /// greater-than-or-equal-to these Constants.
671 /// Range - A pair of iterators representing the range of case values to be
672 /// processed at this point in the binary search tree.
676 typedef std::vector<CaseRec> CaseRecVector;
678 /// The comparison function for sorting the switch case values in the vector.
679 /// WARNING: Case ranges should be disjoint!
681 bool operator () (const Case& C1, const Case& C2) {
682 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
683 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
684 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
685 return CI1->getValue().slt(CI2->getValue());
690 bool operator () (const CaseBits& C1, const CaseBits& C2) {
691 return C1.Bits > C2.Bits;
695 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
698 // TLI - This is information that describes the available target features we
699 // need for lowering. This indicates when operations are unavailable,
700 // implemented with a libcall, etc.
703 const TargetData *TD;
706 /// SwitchCases - Vector of CaseBlock structures used to communicate
707 /// SwitchInst code generation information.
708 std::vector<CaseBlock> SwitchCases;
709 /// JTCases - Vector of JumpTable structures used to communicate
710 /// SwitchInst code generation information.
711 std::vector<JumpTableBlock> JTCases;
712 /// BitTestCases - Vector of BitTestBlock structures used to communicate
713 /// SwitchInst code generation information.
714 std::vector<BitTestBlock> BitTestCases;
716 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
718 // Emit PHI-node-operand constants only once even if used by multiple
720 DenseMap<Constant*, unsigned> ConstantsOut;
722 /// FuncInfo - Information about the function as a whole.
724 FunctionLoweringInfo &FuncInfo;
726 /// GFI - Garbage collection metadata for the function.
729 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
730 FunctionLoweringInfo &funcinfo)
731 : TLI(tli), DAG(dag), FuncInfo(funcinfo) {
734 void init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
737 TD = DAG.getTarget().getTargetData();
740 /// clear - Clear out the curret SelectionDAG and the associated
741 /// state and prepare this SelectionDAGLowering object to be used
742 /// for a new block. This doesn't clear out information about
743 /// additional blocks that are needed to complete switch lowering
744 /// or PHI node updating; that information is cleared out as it is
748 PendingLoads.clear();
749 PendingExports.clear();
753 /// getRoot - Return the current virtual root of the Selection DAG,
754 /// flushing any PendingLoad items. This must be done before emitting
755 /// a store or any other node that may need to be ordered after any
756 /// prior load instructions.
759 if (PendingLoads.empty())
760 return DAG.getRoot();
762 if (PendingLoads.size() == 1) {
763 SDValue Root = PendingLoads[0];
765 PendingLoads.clear();
769 // Otherwise, we have to make a token factor node.
770 SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
771 &PendingLoads[0], PendingLoads.size());
772 PendingLoads.clear();
777 /// getControlRoot - Similar to getRoot, but instead of flushing all the
778 /// PendingLoad items, flush all the PendingExports items. It is necessary
779 /// to do this before emitting a terminator instruction.
781 SDValue getControlRoot() {
782 SDValue Root = DAG.getRoot();
784 if (PendingExports.empty())
787 // Turn all of the CopyToReg chains into one factored node.
788 if (Root.getOpcode() != ISD::EntryToken) {
789 unsigned i = 0, e = PendingExports.size();
790 for (; i != e; ++i) {
791 assert(PendingExports[i].Val->getNumOperands() > 1);
792 if (PendingExports[i].Val->getOperand(0) == Root)
793 break; // Don't add the root if we already indirectly depend on it.
797 PendingExports.push_back(Root);
800 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
802 PendingExports.size());
803 PendingExports.clear();
808 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
810 void visit(Instruction &I) { visit(I.getOpcode(), I); }
812 void visit(unsigned Opcode, User &I) {
813 // Note: this doesn't use InstVisitor, because it has to work with
814 // ConstantExpr's in addition to instructions.
816 default: assert(0 && "Unknown instruction type encountered!");
818 // Build the switch statement using the Instruction.def file.
819 #define HANDLE_INST(NUM, OPCODE, CLASS) \
820 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
821 #include "llvm/Instruction.def"
825 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
827 SDValue getValue(const Value *V);
829 void setValue(const Value *V, SDValue NewN) {
830 SDValue &N = NodeMap[V];
831 assert(N.Val == 0 && "Already set a value for this node!");
835 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
836 std::set<unsigned> &OutputRegs,
837 std::set<unsigned> &InputRegs);
839 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
840 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
842 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
843 void ExportFromCurrentBlock(Value *V);
844 void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
845 MachineBasicBlock *LandingPad = NULL);
847 // Terminator instructions.
848 void visitRet(ReturnInst &I);
849 void visitBr(BranchInst &I);
850 void visitSwitch(SwitchInst &I);
851 void visitUnreachable(UnreachableInst &I) { /* noop */ }
853 // Helpers for visitSwitch
854 bool handleSmallSwitchRange(CaseRec& CR,
855 CaseRecVector& WorkList,
857 MachineBasicBlock* Default);
858 bool handleJTSwitchCase(CaseRec& CR,
859 CaseRecVector& WorkList,
861 MachineBasicBlock* Default);
862 bool handleBTSplitSwitchCase(CaseRec& CR,
863 CaseRecVector& WorkList,
865 MachineBasicBlock* Default);
866 bool handleBitTestsSwitchCase(CaseRec& CR,
867 CaseRecVector& WorkList,
869 MachineBasicBlock* Default);
870 void visitSwitchCase(CaseBlock &CB);
871 void visitBitTestHeader(BitTestBlock &B);
872 void visitBitTestCase(MachineBasicBlock* NextMBB,
875 void visitJumpTable(JumpTable &JT);
876 void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH);
878 // These all get lowered before this pass.
879 void visitInvoke(InvokeInst &I);
880 void visitUnwind(UnwindInst &I);
882 void visitBinary(User &I, unsigned OpCode);
883 void visitShift(User &I, unsigned Opcode);
884 void visitAdd(User &I) {
885 if (I.getType()->isFPOrFPVector())
886 visitBinary(I, ISD::FADD);
888 visitBinary(I, ISD::ADD);
890 void visitSub(User &I);
891 void visitMul(User &I) {
892 if (I.getType()->isFPOrFPVector())
893 visitBinary(I, ISD::FMUL);
895 visitBinary(I, ISD::MUL);
897 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
898 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
899 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
900 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
901 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
902 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
903 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
904 void visitOr (User &I) { visitBinary(I, ISD::OR); }
905 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
906 void visitShl (User &I) { visitShift(I, ISD::SHL); }
907 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
908 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
909 void visitICmp(User &I);
910 void visitFCmp(User &I);
911 void visitVICmp(User &I);
912 void visitVFCmp(User &I);
913 // Visit the conversion instructions
914 void visitTrunc(User &I);
915 void visitZExt(User &I);
916 void visitSExt(User &I);
917 void visitFPTrunc(User &I);
918 void visitFPExt(User &I);
919 void visitFPToUI(User &I);
920 void visitFPToSI(User &I);
921 void visitUIToFP(User &I);
922 void visitSIToFP(User &I);
923 void visitPtrToInt(User &I);
924 void visitIntToPtr(User &I);
925 void visitBitCast(User &I);
927 void visitExtractElement(User &I);
928 void visitInsertElement(User &I);
929 void visitShuffleVector(User &I);
931 void visitExtractValue(ExtractValueInst &I);
932 void visitInsertValue(InsertValueInst &I);
934 void visitGetElementPtr(User &I);
935 void visitSelect(User &I);
937 void visitMalloc(MallocInst &I);
938 void visitFree(FreeInst &I);
939 void visitAlloca(AllocaInst &I);
940 void visitLoad(LoadInst &I);
941 void visitStore(StoreInst &I);
942 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
943 void visitCall(CallInst &I);
944 void visitInlineAsm(CallSite CS);
945 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
946 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
948 void visitVAStart(CallInst &I);
949 void visitVAArg(VAArgInst &I);
950 void visitVAEnd(CallInst &I);
951 void visitVACopy(CallInst &I);
953 void visitUserOp1(Instruction &I) {
954 assert(0 && "UserOp1 should not exist at instruction selection time!");
957 void visitUserOp2(Instruction &I) {
958 assert(0 && "UserOp2 should not exist at instruction selection time!");
963 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
966 } // end namespace llvm
969 /// getCopyFromParts - Create a value that contains the specified legal parts
970 /// combined into the value they represent. If the parts combine to a type
971 /// larger then ValueVT then AssertOp can be used to specify whether the extra
972 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
973 /// (ISD::AssertSext).
974 static SDValue getCopyFromParts(SelectionDAG &DAG,
975 const SDValue *Parts,
979 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
980 assert(NumParts > 0 && "No parts to assemble!");
981 TargetLowering &TLI = DAG.getTargetLoweringInfo();
982 SDValue Val = Parts[0];
985 // Assemble the value from multiple parts.
986 if (!ValueVT.isVector()) {
987 unsigned PartBits = PartVT.getSizeInBits();
988 unsigned ValueBits = ValueVT.getSizeInBits();
990 // Assemble the power of 2 part.
991 unsigned RoundParts = NumParts & (NumParts - 1) ?
992 1 << Log2_32(NumParts) : NumParts;
993 unsigned RoundBits = PartBits * RoundParts;
994 MVT RoundVT = RoundBits == ValueBits ?
995 ValueVT : MVT::getIntegerVT(RoundBits);
998 if (RoundParts > 2) {
999 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
1000 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
1001 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
1007 if (TLI.isBigEndian())
1009 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
1011 if (RoundParts < NumParts) {
1012 // Assemble the trailing non-power-of-2 part.
1013 unsigned OddParts = NumParts - RoundParts;
1014 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
1015 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
1017 // Combine the round and odd parts.
1019 if (TLI.isBigEndian())
1021 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
1022 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
1023 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
1024 DAG.getConstant(Lo.getValueType().getSizeInBits(),
1025 TLI.getShiftAmountTy()));
1026 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
1027 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
1030 // Handle a multi-element vector.
1031 MVT IntermediateVT, RegisterVT;
1032 unsigned NumIntermediates;
1034 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1036 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
1037 NumParts = NumRegs; // Silence a compiler warning.
1038 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1039 assert(RegisterVT == Parts[0].getValueType() &&
1040 "Part type doesn't match part!");
1042 // Assemble the parts into intermediate operands.
1043 SmallVector<SDValue, 8> Ops(NumIntermediates);
1044 if (NumIntermediates == NumParts) {
1045 // If the register was not expanded, truncate or copy the value,
1047 for (unsigned i = 0; i != NumParts; ++i)
1048 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
1049 PartVT, IntermediateVT);
1050 } else if (NumParts > 0) {
1051 // If the intermediate type was expanded, build the intermediate operands
1053 assert(NumParts % NumIntermediates == 0 &&
1054 "Must expand into a divisible number of parts!");
1055 unsigned Factor = NumParts / NumIntermediates;
1056 for (unsigned i = 0; i != NumIntermediates; ++i)
1057 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
1058 PartVT, IntermediateVT);
1061 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
1063 Val = DAG.getNode(IntermediateVT.isVector() ?
1064 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
1065 ValueVT, &Ops[0], NumIntermediates);
1069 // There is now one part, held in Val. Correct it to match ValueVT.
1070 PartVT = Val.getValueType();
1072 if (PartVT == ValueVT)
1075 if (PartVT.isVector()) {
1076 assert(ValueVT.isVector() && "Unknown vector conversion!");
1077 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
1080 if (ValueVT.isVector()) {
1081 assert(ValueVT.getVectorElementType() == PartVT &&
1082 ValueVT.getVectorNumElements() == 1 &&
1083 "Only trivial scalar-to-vector conversions should get here!");
1084 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
1087 if (PartVT.isInteger() &&
1088 ValueVT.isInteger()) {
1089 if (ValueVT.bitsLT(PartVT)) {
1090 // For a truncate, see if we have any information to
1091 // indicate whether the truncated bits will always be
1092 // zero or sign-extension.
1093 if (AssertOp != ISD::DELETED_NODE)
1094 Val = DAG.getNode(AssertOp, PartVT, Val,
1095 DAG.getValueType(ValueVT));
1096 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1098 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
1102 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
1103 if (ValueVT.bitsLT(Val.getValueType()))
1104 // FP_ROUND's are always exact here.
1105 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
1106 DAG.getIntPtrConstant(1));
1107 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
1110 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
1111 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
1113 assert(0 && "Unknown mismatch!");
1117 /// getCopyToParts - Create a series of nodes that contain the specified value
1118 /// split into legal parts. If the parts contain more bits than Val, then, for
1119 /// integers, ExtendKind can be used to specify how to generate the extra bits.
1120 static void getCopyToParts(SelectionDAG &DAG,
1125 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
1126 TargetLowering &TLI = DAG.getTargetLoweringInfo();
1127 MVT PtrVT = TLI.getPointerTy();
1128 MVT ValueVT = Val.getValueType();
1129 unsigned PartBits = PartVT.getSizeInBits();
1130 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
1135 if (!ValueVT.isVector()) {
1136 if (PartVT == ValueVT) {
1137 assert(NumParts == 1 && "No-op copy with multiple parts!");
1142 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
1143 // If the parts cover more bits than the value has, promote the value.
1144 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
1145 assert(NumParts == 1 && "Do not know what to promote to!");
1146 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
1147 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
1148 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1149 Val = DAG.getNode(ExtendKind, ValueVT, Val);
1151 assert(0 && "Unknown mismatch!");
1153 } else if (PartBits == ValueVT.getSizeInBits()) {
1154 // Different types of the same size.
1155 assert(NumParts == 1 && PartVT != ValueVT);
1156 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1157 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
1158 // If the parts cover less bits than value has, truncate the value.
1159 if (PartVT.isInteger() && ValueVT.isInteger()) {
1160 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1161 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1163 assert(0 && "Unknown mismatch!");
1167 // The value may have changed - recompute ValueVT.
1168 ValueVT = Val.getValueType();
1169 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
1170 "Failed to tile the value with PartVT!");
1172 if (NumParts == 1) {
1173 assert(PartVT == ValueVT && "Type conversion failed!");
1178 // Expand the value into multiple parts.
1179 if (NumParts & (NumParts - 1)) {
1180 // The number of parts is not a power of 2. Split off and copy the tail.
1181 assert(PartVT.isInteger() && ValueVT.isInteger() &&
1182 "Do not know what to expand to!");
1183 unsigned RoundParts = 1 << Log2_32(NumParts);
1184 unsigned RoundBits = RoundParts * PartBits;
1185 unsigned OddParts = NumParts - RoundParts;
1186 SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
1187 DAG.getConstant(RoundBits,
1188 TLI.getShiftAmountTy()));
1189 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
1190 if (TLI.isBigEndian())
1191 // The odd parts were reversed by getCopyToParts - unreverse them.
1192 std::reverse(Parts + RoundParts, Parts + NumParts);
1193 NumParts = RoundParts;
1194 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1195 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1198 // The number of parts is a power of 2. Repeatedly bisect the value using
1200 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
1201 MVT::getIntegerVT(ValueVT.getSizeInBits()),
1203 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
1204 for (unsigned i = 0; i < NumParts; i += StepSize) {
1205 unsigned ThisBits = StepSize * PartBits / 2;
1206 MVT ThisVT = MVT::getIntegerVT (ThisBits);
1207 SDValue &Part0 = Parts[i];
1208 SDValue &Part1 = Parts[i+StepSize/2];
1210 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1211 DAG.getConstant(1, PtrVT));
1212 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1213 DAG.getConstant(0, PtrVT));
1215 if (ThisBits == PartBits && ThisVT != PartVT) {
1216 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
1217 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
1222 if (TLI.isBigEndian())
1223 std::reverse(Parts, Parts + NumParts);
1229 if (NumParts == 1) {
1230 if (PartVT != ValueVT) {
1231 if (PartVT.isVector()) {
1232 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1234 assert(ValueVT.getVectorElementType() == PartVT &&
1235 ValueVT.getVectorNumElements() == 1 &&
1236 "Only trivial vector-to-scalar conversions should get here!");
1237 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
1238 DAG.getConstant(0, PtrVT));
1246 // Handle a multi-element vector.
1247 MVT IntermediateVT, RegisterVT;
1248 unsigned NumIntermediates;
1250 DAG.getTargetLoweringInfo()
1251 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1253 unsigned NumElements = ValueVT.getVectorNumElements();
1255 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
1256 NumParts = NumRegs; // Silence a compiler warning.
1257 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1259 // Split the vector into intermediate operands.
1260 SmallVector<SDValue, 8> Ops(NumIntermediates);
1261 for (unsigned i = 0; i != NumIntermediates; ++i)
1262 if (IntermediateVT.isVector())
1263 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
1264 IntermediateVT, Val,
1265 DAG.getConstant(i * (NumElements / NumIntermediates),
1268 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
1269 IntermediateVT, Val,
1270 DAG.getConstant(i, PtrVT));
1272 // Split the intermediate operands into legal parts.
1273 if (NumParts == NumIntermediates) {
1274 // If the register was not expanded, promote or copy the value,
1276 for (unsigned i = 0; i != NumParts; ++i)
1277 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
1278 } else if (NumParts > 0) {
1279 // If the intermediate type was expanded, split each the value into
1281 assert(NumParts % NumIntermediates == 0 &&
1282 "Must expand into a divisible number of parts!");
1283 unsigned Factor = NumParts / NumIntermediates;
1284 for (unsigned i = 0; i != NumIntermediates; ++i)
1285 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
1290 SDValue SelectionDAGLowering::getValue(const Value *V) {
1291 SDValue &N = NodeMap[V];
1292 if (N.Val) return N;
1294 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
1295 MVT VT = TLI.getValueType(V->getType(), true);
1297 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
1298 return N = DAG.getConstant(CI->getValue(), VT);
1300 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
1301 return N = DAG.getGlobalAddress(GV, VT);
1303 if (isa<ConstantPointerNull>(C))
1304 return N = DAG.getConstant(0, TLI.getPointerTy());
1306 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1307 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1309 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
1310 !V->getType()->isAggregateType())
1311 return N = DAG.getNode(ISD::UNDEF, VT);
1313 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1314 visit(CE->getOpcode(), *CE);
1315 SDValue N1 = NodeMap[V];
1316 assert(N1.Val && "visit didn't populate the ValueMap!");
1320 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1321 SmallVector<SDValue, 4> Constants;
1322 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1324 SDNode *Val = getValue(*OI).Val;
1325 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1326 Constants.push_back(SDValue(Val, i));
1328 return DAG.getMergeValues(&Constants[0], Constants.size());
1331 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
1332 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1333 "Unknown struct or array constant!");
1335 SmallVector<MVT, 4> ValueVTs;
1336 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1337 unsigned NumElts = ValueVTs.size();
1339 return SDValue(); // empty struct
1340 SmallVector<SDValue, 4> Constants(NumElts);
1341 for (unsigned i = 0; i != NumElts; ++i) {
1342 MVT EltVT = ValueVTs[i];
1343 if (isa<UndefValue>(C))
1344 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1345 else if (EltVT.isFloatingPoint())
1346 Constants[i] = DAG.getConstantFP(0, EltVT);
1348 Constants[i] = DAG.getConstant(0, EltVT);
1350 return DAG.getMergeValues(&Constants[0], NumElts);
1353 const VectorType *VecTy = cast<VectorType>(V->getType());
1354 unsigned NumElements = VecTy->getNumElements();
1356 // Now that we know the number and type of the elements, get that number of
1357 // elements into the Ops array based on what kind of constant it is.
1358 SmallVector<SDValue, 16> Ops;
1359 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1360 for (unsigned i = 0; i != NumElements; ++i)
1361 Ops.push_back(getValue(CP->getOperand(i)));
1363 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1364 "Unknown vector constant!");
1365 MVT EltVT = TLI.getValueType(VecTy->getElementType());
1368 if (isa<UndefValue>(C))
1369 Op = DAG.getNode(ISD::UNDEF, EltVT);
1370 else if (EltVT.isFloatingPoint())
1371 Op = DAG.getConstantFP(0, EltVT);
1373 Op = DAG.getConstant(0, EltVT);
1374 Ops.assign(NumElements, Op);
1377 // Create a BUILD_VECTOR node.
1378 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1381 // If this is a static alloca, generate it as the frameindex instead of
1383 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1384 DenseMap<const AllocaInst*, int>::iterator SI =
1385 FuncInfo.StaticAllocaMap.find(AI);
1386 if (SI != FuncInfo.StaticAllocaMap.end())
1387 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1390 unsigned InReg = FuncInfo.ValueMap[V];
1391 assert(InReg && "Value not in map!");
1393 RegsForValue RFV(TLI, InReg, V->getType());
1394 SDValue Chain = DAG.getEntryNode();
1395 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1399 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1400 if (I.getNumOperands() == 0) {
1401 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1405 SmallVector<SDValue, 8> NewValues;
1406 NewValues.push_back(getControlRoot());
1407 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1408 SDValue RetOp = getValue(I.getOperand(i));
1410 SmallVector<MVT, 4> ValueVTs;
1411 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
1412 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) {
1413 MVT VT = ValueVTs[j];
1415 // FIXME: C calling convention requires the return type to be promoted to
1416 // at least 32-bit. But this is not necessary for non-C calling conventions.
1417 if (VT.isInteger()) {
1418 MVT MinVT = TLI.getRegisterType(MVT::i32);
1419 if (VT.bitsLT(MinVT))
1423 unsigned NumParts = TLI.getNumRegisters(VT);
1424 MVT PartVT = TLI.getRegisterType(VT);
1425 SmallVector<SDValue, 4> Parts(NumParts);
1426 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1428 const Function *F = I.getParent()->getParent();
1429 if (F->paramHasAttr(0, ParamAttr::SExt))
1430 ExtendKind = ISD::SIGN_EXTEND;
1431 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1432 ExtendKind = ISD::ZERO_EXTEND;
1434 getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.getResNo() + j),
1435 &Parts[0], NumParts, PartVT, ExtendKind);
1437 for (unsigned i = 0; i < NumParts; ++i) {
1438 NewValues.push_back(Parts[i]);
1439 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1443 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1444 &NewValues[0], NewValues.size()));
1447 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1448 /// the current basic block, add it to ValueMap now so that we'll get a
1450 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1451 // No need to export constants.
1452 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1454 // Already exported?
1455 if (FuncInfo.isExportedInst(V)) return;
1457 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1458 CopyValueToVirtualRegister(V, Reg);
1461 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1462 const BasicBlock *FromBB) {
1463 // The operands of the setcc have to be in this block. We don't know
1464 // how to export them from some other block.
1465 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1466 // Can export from current BB.
1467 if (VI->getParent() == FromBB)
1470 // Is already exported, noop.
1471 return FuncInfo.isExportedInst(V);
1474 // If this is an argument, we can export it if the BB is the entry block or
1475 // if it is already exported.
1476 if (isa<Argument>(V)) {
1477 if (FromBB == &FromBB->getParent()->getEntryBlock())
1480 // Otherwise, can only export this if it is already exported.
1481 return FuncInfo.isExportedInst(V);
1484 // Otherwise, constants can always be exported.
1488 static bool InBlock(const Value *V, const BasicBlock *BB) {
1489 if (const Instruction *I = dyn_cast<Instruction>(V))
1490 return I->getParent() == BB;
1494 /// FindMergedConditions - If Cond is an expression like
1495 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1496 MachineBasicBlock *TBB,
1497 MachineBasicBlock *FBB,
1498 MachineBasicBlock *CurBB,
1500 // If this node is not part of the or/and tree, emit it as a branch.
1501 Instruction *BOp = dyn_cast<Instruction>(Cond);
1503 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1504 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1505 BOp->getParent() != CurBB->getBasicBlock() ||
1506 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1507 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1508 const BasicBlock *BB = CurBB->getBasicBlock();
1510 // If the leaf of the tree is a comparison, merge the condition into
1512 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1513 // The operands of the cmp have to be in this block. We don't know
1514 // how to export them from some other block. If this is the first block
1515 // of the sequence, no exporting is needed.
1517 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1518 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1519 BOp = cast<Instruction>(Cond);
1520 ISD::CondCode Condition;
1521 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1522 switch (IC->getPredicate()) {
1523 default: assert(0 && "Unknown icmp predicate opcode!");
1524 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1525 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1526 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1527 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1528 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1529 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1530 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1531 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1532 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1533 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1535 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1536 ISD::CondCode FPC, FOC;
1537 switch (FC->getPredicate()) {
1538 default: assert(0 && "Unknown fcmp predicate opcode!");
1539 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1540 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1541 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1542 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1543 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1544 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1545 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1546 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1547 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1548 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1549 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1550 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1551 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1552 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1553 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1554 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1556 if (FiniteOnlyFPMath())
1561 Condition = ISD::SETEQ; // silence warning.
1562 assert(0 && "Unknown compare instruction");
1565 CaseBlock CB(Condition, BOp->getOperand(0),
1566 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1567 SwitchCases.push_back(CB);
1571 // Create a CaseBlock record representing this branch.
1572 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1573 NULL, TBB, FBB, CurBB);
1574 SwitchCases.push_back(CB);
1579 // Create TmpBB after CurBB.
1580 MachineFunction::iterator BBI = CurBB;
1581 MachineFunction &MF = DAG.getMachineFunction();
1582 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1583 CurBB->getParent()->insert(++BBI, TmpBB);
1585 if (Opc == Instruction::Or) {
1586 // Codegen X | Y as:
1594 // Emit the LHS condition.
1595 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1597 // Emit the RHS condition into TmpBB.
1598 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1600 assert(Opc == Instruction::And && "Unknown merge op!");
1601 // Codegen X & Y as:
1608 // This requires creation of TmpBB after CurBB.
1610 // Emit the LHS condition.
1611 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1613 // Emit the RHS condition into TmpBB.
1614 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1618 /// If the set of cases should be emitted as a series of branches, return true.
1619 /// If we should emit this as a bunch of and/or'd together conditions, return
1622 ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1623 if (Cases.size() != 2) return true;
1625 // If this is two comparisons of the same values or'd or and'd together, they
1626 // will get folded into a single comparison, so don't emit two blocks.
1627 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1628 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1629 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1630 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1637 void SelectionDAGLowering::visitBr(BranchInst &I) {
1638 // Update machine-CFG edges.
1639 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1641 // Figure out which block is immediately after the current one.
1642 MachineBasicBlock *NextBlock = 0;
1643 MachineFunction::iterator BBI = CurMBB;
1644 if (++BBI != CurMBB->getParent()->end())
1647 if (I.isUnconditional()) {
1648 // Update machine-CFG edges.
1649 CurMBB->addSuccessor(Succ0MBB);
1651 // If this is not a fall-through branch, emit the branch.
1652 if (Succ0MBB != NextBlock)
1653 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1654 DAG.getBasicBlock(Succ0MBB)));
1658 // If this condition is one of the special cases we handle, do special stuff
1660 Value *CondVal = I.getCondition();
1661 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1663 // If this is a series of conditions that are or'd or and'd together, emit
1664 // this as a sequence of branches instead of setcc's with and/or operations.
1665 // For example, instead of something like:
1678 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1679 if (BOp->hasOneUse() &&
1680 (BOp->getOpcode() == Instruction::And ||
1681 BOp->getOpcode() == Instruction::Or)) {
1682 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1683 // If the compares in later blocks need to use values not currently
1684 // exported from this block, export them now. This block should always
1685 // be the first entry.
1686 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1688 // Allow some cases to be rejected.
1689 if (ShouldEmitAsBranches(SwitchCases)) {
1690 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1691 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1692 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1695 // Emit the branch for this block.
1696 visitSwitchCase(SwitchCases[0]);
1697 SwitchCases.erase(SwitchCases.begin());
1701 // Okay, we decided not to do this, remove any inserted MBB's and clear
1703 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1704 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1706 SwitchCases.clear();
1710 // Create a CaseBlock record representing this branch.
1711 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1712 NULL, Succ0MBB, Succ1MBB, CurMBB);
1713 // Use visitSwitchCase to actually insert the fast branch sequence for this
1715 visitSwitchCase(CB);
1718 /// visitSwitchCase - Emits the necessary code to represent a single node in
1719 /// the binary search tree resulting from lowering a switch instruction.
1720 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1722 SDValue CondLHS = getValue(CB.CmpLHS);
1724 // Build the setcc now.
1725 if (CB.CmpMHS == NULL) {
1726 // Fold "(X == true)" to X and "(X == false)" to !X to
1727 // handle common cases produced by branch lowering.
1728 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1730 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1731 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1732 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1734 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1736 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1738 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1739 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1741 SDValue CmpOp = getValue(CB.CmpMHS);
1742 MVT VT = CmpOp.getValueType();
1744 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1745 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1747 SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1748 Cond = DAG.getSetCC(MVT::i1, SUB,
1749 DAG.getConstant(High-Low, VT), ISD::SETULE);
1753 // Update successor info
1754 CurMBB->addSuccessor(CB.TrueBB);
1755 CurMBB->addSuccessor(CB.FalseBB);
1757 // Set NextBlock to be the MBB immediately after the current one, if any.
1758 // This is used to avoid emitting unnecessary branches to the next block.
1759 MachineBasicBlock *NextBlock = 0;
1760 MachineFunction::iterator BBI = CurMBB;
1761 if (++BBI != CurMBB->getParent()->end())
1764 // If the lhs block is the next block, invert the condition so that we can
1765 // fall through to the lhs instead of the rhs block.
1766 if (CB.TrueBB == NextBlock) {
1767 std::swap(CB.TrueBB, CB.FalseBB);
1768 SDValue True = DAG.getConstant(1, Cond.getValueType());
1769 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1771 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1772 DAG.getBasicBlock(CB.TrueBB));
1774 // If the branch was constant folded, fix up the CFG.
1775 if (BrCond.getOpcode() == ISD::BR) {
1776 CurMBB->removeSuccessor(CB.FalseBB);
1777 DAG.setRoot(BrCond);
1779 // Otherwise, go ahead and insert the false branch.
1780 if (BrCond == getControlRoot())
1781 CurMBB->removeSuccessor(CB.TrueBB);
1783 if (CB.FalseBB == NextBlock)
1784 DAG.setRoot(BrCond);
1786 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1787 DAG.getBasicBlock(CB.FalseBB)));
1791 /// visitJumpTable - Emit JumpTable node in the current MBB
1792 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1793 // Emit the code for the jump table
1794 assert(JT.Reg != -1U && "Should lower JT Header first!");
1795 MVT PTy = TLI.getPointerTy();
1796 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1797 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1798 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1803 /// visitJumpTableHeader - This function emits necessary code to produce index
1804 /// in the JumpTable from switch case.
1805 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1806 JumpTableHeader &JTH) {
1807 // Subtract the lowest switch case value from the value being switched on
1808 // and conditional branch to default mbb if the result is greater than the
1809 // difference between smallest and largest cases.
1810 SDValue SwitchOp = getValue(JTH.SValue);
1811 MVT VT = SwitchOp.getValueType();
1812 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1813 DAG.getConstant(JTH.First, VT));
1815 // The SDNode we just created, which holds the value being switched on
1816 // minus the the smallest case value, needs to be copied to a virtual
1817 // register so it can be used as an index into the jump table in a
1818 // subsequent basic block. This value may be smaller or larger than the
1819 // target's pointer type, and therefore require extension or truncating.
1820 if (VT.bitsGT(TLI.getPointerTy()))
1821 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1823 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1825 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1826 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1827 JT.Reg = JumpTableReg;
1829 // Emit the range check for the jump table, and branch to the default
1830 // block for the switch statement if the value being switched on exceeds
1831 // the largest case in the switch.
1832 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1833 DAG.getConstant(JTH.Last-JTH.First,VT),
1836 // Set NextBlock to be the MBB immediately after the current one, if any.
1837 // This is used to avoid emitting unnecessary branches to the next block.
1838 MachineBasicBlock *NextBlock = 0;
1839 MachineFunction::iterator BBI = CurMBB;
1840 if (++BBI != CurMBB->getParent()->end())
1843 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1844 DAG.getBasicBlock(JT.Default));
1846 if (JT.MBB == NextBlock)
1847 DAG.setRoot(BrCond);
1849 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1850 DAG.getBasicBlock(JT.MBB)));
1855 /// visitBitTestHeader - This function emits necessary code to produce value
1856 /// suitable for "bit tests"
1857 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1858 // Subtract the minimum value
1859 SDValue SwitchOp = getValue(B.SValue);
1860 MVT VT = SwitchOp.getValueType();
1861 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1862 DAG.getConstant(B.First, VT));
1865 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1866 DAG.getConstant(B.Range, VT),
1870 if (VT.bitsGT(TLI.getShiftAmountTy()))
1871 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1873 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1875 // Make desired shift
1876 SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1877 DAG.getConstant(1, TLI.getPointerTy()),
1880 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1881 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1884 // Set NextBlock to be the MBB immediately after the current one, if any.
1885 // This is used to avoid emitting unnecessary branches to the next block.
1886 MachineBasicBlock *NextBlock = 0;
1887 MachineFunction::iterator BBI = CurMBB;
1888 if (++BBI != CurMBB->getParent()->end())
1891 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1893 CurMBB->addSuccessor(B.Default);
1894 CurMBB->addSuccessor(MBB);
1896 SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1897 DAG.getBasicBlock(B.Default));
1899 if (MBB == NextBlock)
1900 DAG.setRoot(BrRange);
1902 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1903 DAG.getBasicBlock(MBB)));
1908 /// visitBitTestCase - this function produces one "bit test"
1909 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1912 // Emit bit tests and jumps
1913 SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
1914 TLI.getPointerTy());
1916 SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
1917 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1918 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1919 DAG.getConstant(0, TLI.getPointerTy()),
1922 CurMBB->addSuccessor(B.TargetBB);
1923 CurMBB->addSuccessor(NextMBB);
1925 SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1926 AndCmp, DAG.getBasicBlock(B.TargetBB));
1928 // Set NextBlock to be the MBB immediately after the current one, if any.
1929 // This is used to avoid emitting unnecessary branches to the next block.
1930 MachineBasicBlock *NextBlock = 0;
1931 MachineFunction::iterator BBI = CurMBB;
1932 if (++BBI != CurMBB->getParent()->end())
1935 if (NextMBB == NextBlock)
1938 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1939 DAG.getBasicBlock(NextMBB)));
1944 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1945 // Retrieve successors.
1946 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1947 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1949 if (isa<InlineAsm>(I.getCalledValue()))
1952 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1954 // If the value of the invoke is used outside of its defining block, make it
1955 // available as a virtual register.
1956 if (!I.use_empty()) {
1957 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1958 if (VMI != FuncInfo.ValueMap.end())
1959 CopyValueToVirtualRegister(&I, VMI->second);
1962 // Update successor info
1963 CurMBB->addSuccessor(Return);
1964 CurMBB->addSuccessor(LandingPad);
1966 // Drop into normal successor.
1967 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1968 DAG.getBasicBlock(Return)));
1971 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1974 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1975 /// small case ranges).
1976 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1977 CaseRecVector& WorkList,
1979 MachineBasicBlock* Default) {
1980 Case& BackCase = *(CR.Range.second-1);
1982 // Size is the number of Cases represented by this range.
1983 unsigned Size = CR.Range.second - CR.Range.first;
1987 // Get the MachineFunction which holds the current MBB. This is used when
1988 // inserting any additional MBBs necessary to represent the switch.
1989 MachineFunction *CurMF = CurMBB->getParent();
1991 // Figure out which block is immediately after the current one.
1992 MachineBasicBlock *NextBlock = 0;
1993 MachineFunction::iterator BBI = CR.CaseBB;
1995 if (++BBI != CurMBB->getParent()->end())
1998 // TODO: If any two of the cases has the same destination, and if one value
1999 // is the same as the other, but has one bit unset that the other has set,
2000 // use bit manipulation to do two compares at once. For example:
2001 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2003 // Rearrange the case blocks so that the last one falls through if possible.
2004 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2005 // The last case block won't fall through into 'NextBlock' if we emit the
2006 // branches in this order. See if rearranging a case value would help.
2007 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
2008 if (I->BB == NextBlock) {
2009 std::swap(*I, BackCase);
2015 // Create a CaseBlock record representing a conditional branch to
2016 // the Case's target mbb if the value being switched on SV is equal
2018 MachineBasicBlock *CurBlock = CR.CaseBB;
2019 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2020 MachineBasicBlock *FallThrough;
2022 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2023 CurMF->insert(BBI, FallThrough);
2025 // If the last case doesn't match, go to the default block.
2026 FallThrough = Default;
2029 Value *RHS, *LHS, *MHS;
2031 if (I->High == I->Low) {
2032 // This is just small small case range :) containing exactly 1 case
2034 LHS = SV; RHS = I->High; MHS = NULL;
2037 LHS = I->Low; MHS = SV; RHS = I->High;
2039 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
2041 // If emitting the first comparison, just call visitSwitchCase to emit the
2042 // code into the current block. Otherwise, push the CaseBlock onto the
2043 // vector to be later processed by SDISel, and insert the node's MBB
2044 // before the next MBB.
2045 if (CurBlock == CurMBB)
2046 visitSwitchCase(CB);
2048 SwitchCases.push_back(CB);
2050 CurBlock = FallThrough;
2056 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2057 return !DisableJumpTables &&
2058 (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
2059 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
2062 /// handleJTSwitchCase - Emit jumptable for current switch case range
2063 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
2064 CaseRecVector& WorkList,
2066 MachineBasicBlock* Default) {
2067 Case& FrontCase = *CR.Range.first;
2068 Case& BackCase = *(CR.Range.second-1);
2070 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
2071 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
2074 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2078 if (!areJTsAllowed(TLI) || TSize <= 3)
2081 double Density = (double)TSize / (double)((Last - First) + 1ULL);
2085 DOUT << "Lowering jump table\n"
2086 << "First entry: " << First << ". Last entry: " << Last << "\n"
2087 << "Size: " << TSize << ". Density: " << Density << "\n\n";
2089 // Get the MachineFunction which holds the current MBB. This is used when
2090 // inserting any additional MBBs necessary to represent the switch.
2091 MachineFunction *CurMF = CurMBB->getParent();
2093 // Figure out which block is immediately after the current one.
2094 MachineBasicBlock *NextBlock = 0;
2095 MachineFunction::iterator BBI = CR.CaseBB;
2097 if (++BBI != CurMBB->getParent()->end())
2100 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2102 // Create a new basic block to hold the code for loading the address
2103 // of the jump table, and jumping to it. Update successor information;
2104 // we will either branch to the default case for the switch, or the jump
2106 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2107 CurMF->insert(BBI, JumpTableBB);
2108 CR.CaseBB->addSuccessor(Default);
2109 CR.CaseBB->addSuccessor(JumpTableBB);
2111 // Build a vector of destination BBs, corresponding to each target
2112 // of the jump table. If the value of the jump table slot corresponds to
2113 // a case statement, push the case's BB onto the vector, otherwise, push
2115 std::vector<MachineBasicBlock*> DestBBs;
2116 int64_t TEI = First;
2117 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2118 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
2119 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
2121 if ((Low <= TEI) && (TEI <= High)) {
2122 DestBBs.push_back(I->BB);
2126 DestBBs.push_back(Default);
2130 // Update successor info. Add one edge to each unique successor.
2131 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2132 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2133 E = DestBBs.end(); I != E; ++I) {
2134 if (!SuccsHandled[(*I)->getNumber()]) {
2135 SuccsHandled[(*I)->getNumber()] = true;
2136 JumpTableBB->addSuccessor(*I);
2140 // Create a jump table index for this jump table, or return an existing
2142 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
2144 // Set the jump table information so that we can codegen it as a second
2145 // MachineBasicBlock
2146 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2147 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
2148 if (CR.CaseBB == CurMBB)
2149 visitJumpTableHeader(JT, JTH);
2151 JTCases.push_back(JumpTableBlock(JTH, JT));
2156 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2158 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
2159 CaseRecVector& WorkList,
2161 MachineBasicBlock* Default) {
2162 // Get the MachineFunction which holds the current MBB. This is used when
2163 // inserting any additional MBBs necessary to represent the switch.
2164 MachineFunction *CurMF = CurMBB->getParent();
2166 // Figure out which block is immediately after the current one.
2167 MachineBasicBlock *NextBlock = 0;
2168 MachineFunction::iterator BBI = CR.CaseBB;
2170 if (++BBI != CurMBB->getParent()->end())
2173 Case& FrontCase = *CR.Range.first;
2174 Case& BackCase = *(CR.Range.second-1);
2175 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2177 // Size is the number of Cases represented by this range.
2178 unsigned Size = CR.Range.second - CR.Range.first;
2180 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
2181 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
2183 CaseItr Pivot = CR.Range.first + Size/2;
2185 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2186 // (heuristically) allow us to emit JumpTable's later.
2188 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2192 uint64_t LSize = FrontCase.size();
2193 uint64_t RSize = TSize-LSize;
2194 DOUT << "Selecting best pivot: \n"
2195 << "First: " << First << ", Last: " << Last <<"\n"
2196 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
2197 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2199 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
2200 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
2201 assert((RBegin-LEnd>=1) && "Invalid case distance");
2202 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
2203 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
2204 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
2205 // Should always split in some non-trivial place
2207 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
2208 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
2209 << "Metric: " << Metric << "\n";
2210 if (FMetric < Metric) {
2213 DOUT << "Current metric set to: " << FMetric << "\n";
2219 if (areJTsAllowed(TLI)) {
2220 // If our case is dense we *really* should handle it earlier!
2221 assert((FMetric > 0) && "Should handle dense range earlier!");
2223 Pivot = CR.Range.first + Size/2;
2226 CaseRange LHSR(CR.Range.first, Pivot);
2227 CaseRange RHSR(Pivot, CR.Range.second);
2228 Constant *C = Pivot->Low;
2229 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2231 // We know that we branch to the LHS if the Value being switched on is
2232 // less than the Pivot value, C. We use this to optimize our binary
2233 // tree a bit, by recognizing that if SV is greater than or equal to the
2234 // LHS's Case Value, and that Case Value is exactly one less than the
2235 // Pivot's Value, then we can branch directly to the LHS's Target,
2236 // rather than creating a leaf node for it.
2237 if ((LHSR.second - LHSR.first) == 1 &&
2238 LHSR.first->High == CR.GE &&
2239 cast<ConstantInt>(C)->getSExtValue() ==
2240 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
2241 TrueBB = LHSR.first->BB;
2243 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2244 CurMF->insert(BBI, TrueBB);
2245 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2248 // Similar to the optimization above, if the Value being switched on is
2249 // known to be less than the Constant CR.LT, and the current Case Value
2250 // is CR.LT - 1, then we can branch directly to the target block for
2251 // the current Case Value, rather than emitting a RHS leaf node for it.
2252 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2253 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
2254 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
2255 FalseBB = RHSR.first->BB;
2257 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2258 CurMF->insert(BBI, FalseBB);
2259 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2262 // Create a CaseBlock record representing a conditional branch to
2263 // the LHS node if the value being switched on SV is less than C.
2264 // Otherwise, branch to LHS.
2265 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2267 if (CR.CaseBB == CurMBB)
2268 visitSwitchCase(CB);
2270 SwitchCases.push_back(CB);
2275 /// handleBitTestsSwitchCase - if current case range has few destination and
2276 /// range span less, than machine word bitwidth, encode case range into series
2277 /// of masks and emit bit tests with these masks.
2278 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
2279 CaseRecVector& WorkList,
2281 MachineBasicBlock* Default){
2282 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
2284 Case& FrontCase = *CR.Range.first;
2285 Case& BackCase = *(CR.Range.second-1);
2287 // Get the MachineFunction which holds the current MBB. This is used when
2288 // inserting any additional MBBs necessary to represent the switch.
2289 MachineFunction *CurMF = CurMBB->getParent();
2291 unsigned numCmps = 0;
2292 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2294 // Single case counts one, case range - two.
2295 if (I->Low == I->High)
2301 // Count unique destinations
2302 SmallSet<MachineBasicBlock*, 4> Dests;
2303 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2304 Dests.insert(I->BB);
2305 if (Dests.size() > 3)
2306 // Don't bother the code below, if there are too much unique destinations
2309 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
2310 << "Total number of comparisons: " << numCmps << "\n";
2312 // Compute span of values.
2313 Constant* minValue = FrontCase.Low;
2314 Constant* maxValue = BackCase.High;
2315 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
2316 cast<ConstantInt>(minValue)->getSExtValue();
2317 DOUT << "Compare range: " << range << "\n"
2318 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
2319 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
2321 if (range>=IntPtrBits ||
2322 (!(Dests.size() == 1 && numCmps >= 3) &&
2323 !(Dests.size() == 2 && numCmps >= 5) &&
2324 !(Dests.size() >= 3 && numCmps >= 6)))
2327 DOUT << "Emitting bit tests\n";
2328 int64_t lowBound = 0;
2330 // Optimize the case where all the case values fit in a
2331 // word without having to subtract minValue. In this case,
2332 // we can optimize away the subtraction.
2333 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
2334 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
2335 range = cast<ConstantInt>(maxValue)->getSExtValue();
2337 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
2340 CaseBitsVector CasesBits;
2341 unsigned i, count = 0;
2343 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2344 MachineBasicBlock* Dest = I->BB;
2345 for (i = 0; i < count; ++i)
2346 if (Dest == CasesBits[i].BB)
2350 assert((count < 3) && "Too much destinations to test!");
2351 CasesBits.push_back(CaseBits(0, Dest, 0));
2355 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2356 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2358 for (uint64_t j = lo; j <= hi; j++) {
2359 CasesBits[i].Mask |= 1ULL << j;
2360 CasesBits[i].Bits++;
2364 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2368 // Figure out which block is immediately after the current one.
2369 MachineFunction::iterator BBI = CR.CaseBB;
2372 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2375 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2376 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2377 << ", BB: " << CasesBits[i].BB << "\n";
2379 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2380 CurMF->insert(BBI, CaseBB);
2381 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2386 BitTestBlock BTB(lowBound, range, SV,
2387 -1U, (CR.CaseBB == CurMBB),
2388 CR.CaseBB, Default, BTC);
2390 if (CR.CaseBB == CurMBB)
2391 visitBitTestHeader(BTB);
2393 BitTestCases.push_back(BTB);
2399 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2400 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2401 const SwitchInst& SI) {
2402 unsigned numCmps = 0;
2404 // Start with "simple" cases
2405 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2406 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2407 Cases.push_back(Case(SI.getSuccessorValue(i),
2408 SI.getSuccessorValue(i),
2411 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2413 // Merge case into clusters
2414 if (Cases.size()>=2)
2415 // Must recompute end() each iteration because it may be
2416 // invalidated by erase if we hold on to it
2417 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2418 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2419 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2420 MachineBasicBlock* nextBB = J->BB;
2421 MachineBasicBlock* currentBB = I->BB;
2423 // If the two neighboring cases go to the same destination, merge them
2424 // into a single case.
2425 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2433 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2434 if (I->Low != I->High)
2435 // A range counts double, since it requires two compares.
2442 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2443 // Figure out which block is immediately after the current one.
2444 MachineBasicBlock *NextBlock = 0;
2445 MachineFunction::iterator BBI = CurMBB;
2447 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2449 // If there is only the default destination, branch to it if it is not the
2450 // next basic block. Otherwise, just fall through.
2451 if (SI.getNumOperands() == 2) {
2452 // Update machine-CFG edges.
2454 // If this is not a fall-through branch, emit the branch.
2455 CurMBB->addSuccessor(Default);
2456 if (Default != NextBlock)
2457 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2458 DAG.getBasicBlock(Default)));
2463 // If there are any non-default case statements, create a vector of Cases
2464 // representing each one, and sort the vector so that we can efficiently
2465 // create a binary search tree from them.
2467 unsigned numCmps = Clusterify(Cases, SI);
2468 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2469 << ". Total compares: " << numCmps << "\n";
2471 // Get the Value to be switched on and default basic blocks, which will be
2472 // inserted into CaseBlock records, representing basic blocks in the binary
2474 Value *SV = SI.getOperand(0);
2476 // Push the initial CaseRec onto the worklist
2477 CaseRecVector WorkList;
2478 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2480 while (!WorkList.empty()) {
2481 // Grab a record representing a case range to process off the worklist
2482 CaseRec CR = WorkList.back();
2483 WorkList.pop_back();
2485 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2488 // If the range has few cases (two or less) emit a series of specific
2490 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2493 // If the switch has more than 5 blocks, and at least 40% dense, and the
2494 // target supports indirect branches, then emit a jump table rather than
2495 // lowering the switch to a binary tree of conditional branches.
2496 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2499 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2500 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2501 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2506 void SelectionDAGLowering::visitSub(User &I) {
2507 // -0.0 - X --> fneg
2508 const Type *Ty = I.getType();
2509 if (isa<VectorType>(Ty)) {
2510 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2511 const VectorType *DestTy = cast<VectorType>(I.getType());
2512 const Type *ElTy = DestTy->getElementType();
2513 if (ElTy->isFloatingPoint()) {
2514 unsigned VL = DestTy->getNumElements();
2515 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2516 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2518 SDValue Op2 = getValue(I.getOperand(1));
2519 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2525 if (Ty->isFloatingPoint()) {
2526 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2527 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2528 SDValue Op2 = getValue(I.getOperand(1));
2529 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2534 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2537 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2538 SDValue Op1 = getValue(I.getOperand(0));
2539 SDValue Op2 = getValue(I.getOperand(1));
2541 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2544 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2545 SDValue Op1 = getValue(I.getOperand(0));
2546 SDValue Op2 = getValue(I.getOperand(1));
2547 if (!isa<VectorType>(I.getType())) {
2548 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2549 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2550 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2551 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2554 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2557 void SelectionDAGLowering::visitICmp(User &I) {
2558 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2559 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2560 predicate = IC->getPredicate();
2561 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2562 predicate = ICmpInst::Predicate(IC->getPredicate());
2563 SDValue Op1 = getValue(I.getOperand(0));
2564 SDValue Op2 = getValue(I.getOperand(1));
2565 ISD::CondCode Opcode;
2566 switch (predicate) {
2567 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2568 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2569 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2570 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2571 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2572 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2573 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2574 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2575 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2576 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2578 assert(!"Invalid ICmp predicate value");
2579 Opcode = ISD::SETEQ;
2582 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2585 void SelectionDAGLowering::visitFCmp(User &I) {
2586 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2587 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2588 predicate = FC->getPredicate();
2589 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2590 predicate = FCmpInst::Predicate(FC->getPredicate());
2591 SDValue Op1 = getValue(I.getOperand(0));
2592 SDValue Op2 = getValue(I.getOperand(1));
2593 ISD::CondCode Condition, FOC, FPC;
2594 switch (predicate) {
2595 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2596 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2597 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2598 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2599 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2600 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2601 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2602 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2603 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2604 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2605 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2606 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2607 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2608 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2609 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2610 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2612 assert(!"Invalid FCmp predicate value");
2613 FOC = FPC = ISD::SETFALSE;
2616 if (FiniteOnlyFPMath())
2620 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2623 void SelectionDAGLowering::visitVICmp(User &I) {
2624 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2625 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2626 predicate = IC->getPredicate();
2627 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2628 predicate = ICmpInst::Predicate(IC->getPredicate());
2629 SDValue Op1 = getValue(I.getOperand(0));
2630 SDValue Op2 = getValue(I.getOperand(1));
2631 ISD::CondCode Opcode;
2632 switch (predicate) {
2633 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2634 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2635 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2636 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2637 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2638 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2639 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2640 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2641 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2642 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2644 assert(!"Invalid ICmp predicate value");
2645 Opcode = ISD::SETEQ;
2648 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2651 void SelectionDAGLowering::visitVFCmp(User &I) {
2652 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2653 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2654 predicate = FC->getPredicate();
2655 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2656 predicate = FCmpInst::Predicate(FC->getPredicate());
2657 SDValue Op1 = getValue(I.getOperand(0));
2658 SDValue Op2 = getValue(I.getOperand(1));
2659 ISD::CondCode Condition, FOC, FPC;
2660 switch (predicate) {
2661 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2662 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2663 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2664 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2665 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2666 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2667 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2668 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2669 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2670 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2671 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2672 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2673 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2674 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2675 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2676 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2678 assert(!"Invalid VFCmp predicate value");
2679 FOC = FPC = ISD::SETFALSE;
2682 if (FiniteOnlyFPMath())
2687 MVT DestVT = TLI.getValueType(I.getType());
2689 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2692 void SelectionDAGLowering::visitSelect(User &I) {
2693 SDValue Cond = getValue(I.getOperand(0));
2694 SDValue TrueVal = getValue(I.getOperand(1));
2695 SDValue FalseVal = getValue(I.getOperand(2));
2696 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2697 TrueVal, FalseVal));
2701 void SelectionDAGLowering::visitTrunc(User &I) {
2702 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2703 SDValue N = getValue(I.getOperand(0));
2704 MVT DestVT = TLI.getValueType(I.getType());
2705 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2708 void SelectionDAGLowering::visitZExt(User &I) {
2709 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2710 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2711 SDValue N = getValue(I.getOperand(0));
2712 MVT DestVT = TLI.getValueType(I.getType());
2713 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2716 void SelectionDAGLowering::visitSExt(User &I) {
2717 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2718 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2719 SDValue N = getValue(I.getOperand(0));
2720 MVT DestVT = TLI.getValueType(I.getType());
2721 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2724 void SelectionDAGLowering::visitFPTrunc(User &I) {
2725 // FPTrunc is never a no-op cast, no need to check
2726 SDValue N = getValue(I.getOperand(0));
2727 MVT DestVT = TLI.getValueType(I.getType());
2728 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2731 void SelectionDAGLowering::visitFPExt(User &I){
2732 // FPTrunc is never a no-op cast, no need to check
2733 SDValue N = getValue(I.getOperand(0));
2734 MVT DestVT = TLI.getValueType(I.getType());
2735 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2738 void SelectionDAGLowering::visitFPToUI(User &I) {
2739 // FPToUI is never a no-op cast, no need to check
2740 SDValue N = getValue(I.getOperand(0));
2741 MVT DestVT = TLI.getValueType(I.getType());
2742 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2745 void SelectionDAGLowering::visitFPToSI(User &I) {
2746 // FPToSI is never a no-op cast, no need to check
2747 SDValue N = getValue(I.getOperand(0));
2748 MVT DestVT = TLI.getValueType(I.getType());
2749 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2752 void SelectionDAGLowering::visitUIToFP(User &I) {
2753 // UIToFP is never a no-op cast, no need to check
2754 SDValue N = getValue(I.getOperand(0));
2755 MVT DestVT = TLI.getValueType(I.getType());
2756 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2759 void SelectionDAGLowering::visitSIToFP(User &I){
2760 // UIToFP is never a no-op cast, no need to check
2761 SDValue N = getValue(I.getOperand(0));
2762 MVT DestVT = TLI.getValueType(I.getType());
2763 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2766 void SelectionDAGLowering::visitPtrToInt(User &I) {
2767 // What to do depends on the size of the integer and the size of the pointer.
2768 // We can either truncate, zero extend, or no-op, accordingly.
2769 SDValue N = getValue(I.getOperand(0));
2770 MVT SrcVT = N.getValueType();
2771 MVT DestVT = TLI.getValueType(I.getType());
2773 if (DestVT.bitsLT(SrcVT))
2774 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2776 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2777 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2778 setValue(&I, Result);
2781 void SelectionDAGLowering::visitIntToPtr(User &I) {
2782 // What to do depends on the size of the integer and the size of the pointer.
2783 // We can either truncate, zero extend, or no-op, accordingly.
2784 SDValue N = getValue(I.getOperand(0));
2785 MVT SrcVT = N.getValueType();
2786 MVT DestVT = TLI.getValueType(I.getType());
2787 if (DestVT.bitsLT(SrcVT))
2788 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2790 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2791 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2794 void SelectionDAGLowering::visitBitCast(User &I) {
2795 SDValue N = getValue(I.getOperand(0));
2796 MVT DestVT = TLI.getValueType(I.getType());
2798 // BitCast assures us that source and destination are the same size so this
2799 // is either a BIT_CONVERT or a no-op.
2800 if (DestVT != N.getValueType())
2801 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2803 setValue(&I, N); // noop cast.
2806 void SelectionDAGLowering::visitInsertElement(User &I) {
2807 SDValue InVec = getValue(I.getOperand(0));
2808 SDValue InVal = getValue(I.getOperand(1));
2809 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2810 getValue(I.getOperand(2)));
2812 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2813 TLI.getValueType(I.getType()),
2814 InVec, InVal, InIdx));
2817 void SelectionDAGLowering::visitExtractElement(User &I) {
2818 SDValue InVec = getValue(I.getOperand(0));
2819 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2820 getValue(I.getOperand(1)));
2821 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2822 TLI.getValueType(I.getType()), InVec, InIdx));
2825 void SelectionDAGLowering::visitShuffleVector(User &I) {
2826 SDValue V1 = getValue(I.getOperand(0));
2827 SDValue V2 = getValue(I.getOperand(1));
2828 SDValue Mask = getValue(I.getOperand(2));
2830 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2831 TLI.getValueType(I.getType()),
2835 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2836 const Value *Op0 = I.getOperand(0);
2837 const Value *Op1 = I.getOperand(1);
2838 const Type *AggTy = I.getType();
2839 const Type *ValTy = Op1->getType();
2840 bool IntoUndef = isa<UndefValue>(Op0);
2841 bool FromUndef = isa<UndefValue>(Op1);
2843 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2844 I.idx_begin(), I.idx_end());
2846 SmallVector<MVT, 4> AggValueVTs;
2847 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2848 SmallVector<MVT, 4> ValValueVTs;
2849 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2851 unsigned NumAggValues = AggValueVTs.size();
2852 unsigned NumValValues = ValValueVTs.size();
2853 SmallVector<SDValue, 4> Values(NumAggValues);
2855 SDValue Agg = getValue(Op0);
2856 SDValue Val = getValue(Op1);
2858 // Copy the beginning value(s) from the original aggregate.
2859 for (; i != LinearIndex; ++i)
2860 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2861 SDValue(Agg.Val, Agg.getResNo() + i);
2862 // Copy values from the inserted value(s).
2863 for (; i != LinearIndex + NumValValues; ++i)
2864 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2865 SDValue(Val.Val, Val.getResNo() + i - LinearIndex);
2866 // Copy remaining value(s) from the original aggregate.
2867 for (; i != NumAggValues; ++i)
2868 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2869 SDValue(Agg.Val, Agg.getResNo() + i);
2871 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
2872 &Values[0], NumAggValues));
2875 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2876 const Value *Op0 = I.getOperand(0);
2877 const Type *AggTy = Op0->getType();
2878 const Type *ValTy = I.getType();
2879 bool OutOfUndef = isa<UndefValue>(Op0);
2881 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2882 I.idx_begin(), I.idx_end());
2884 SmallVector<MVT, 4> ValValueVTs;
2885 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2887 unsigned NumValValues = ValValueVTs.size();
2888 SmallVector<SDValue, 4> Values(NumValValues);
2890 SDValue Agg = getValue(Op0);
2891 // Copy out the selected value(s).
2892 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2893 Values[i - LinearIndex] =
2894 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.getResNo() + i)) :
2895 SDValue(Agg.Val, Agg.getResNo() + i);
2897 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
2898 &Values[0], NumValValues));
2902 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2903 SDValue N = getValue(I.getOperand(0));
2904 const Type *Ty = I.getOperand(0)->getType();
2906 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2909 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2910 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2913 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2914 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2915 DAG.getIntPtrConstant(Offset));
2917 Ty = StTy->getElementType(Field);
2919 Ty = cast<SequentialType>(Ty)->getElementType();
2921 // If this is a constant subscript, handle it quickly.
2922 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2923 if (CI->getZExtValue() == 0) continue;
2925 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2926 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2927 DAG.getIntPtrConstant(Offs));
2931 // N = N + Idx * ElementSize;
2932 uint64_t ElementSize = TD->getABITypeSize(Ty);
2933 SDValue IdxN = getValue(Idx);
2935 // If the index is smaller or larger than intptr_t, truncate or extend
2937 if (IdxN.getValueType().bitsLT(N.getValueType()))
2938 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2939 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2940 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2942 // If this is a multiply by a power of two, turn it into a shl
2943 // immediately. This is a very common case.
2944 if (ElementSize != 1) {
2945 if (isPowerOf2_64(ElementSize)) {
2946 unsigned Amt = Log2_64(ElementSize);
2947 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2948 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2950 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2951 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2955 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2961 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2962 // If this is a fixed sized alloca in the entry block of the function,
2963 // allocate it statically on the stack.
2964 if (FuncInfo.StaticAllocaMap.count(&I))
2965 return; // getValue will auto-populate this.
2967 const Type *Ty = I.getAllocatedType();
2968 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2970 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2973 SDValue AllocSize = getValue(I.getArraySize());
2974 MVT IntPtr = TLI.getPointerTy();
2975 if (IntPtr.bitsLT(AllocSize.getValueType()))
2976 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2977 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2978 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2980 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2981 DAG.getIntPtrConstant(TySize));
2983 // Handle alignment. If the requested alignment is less than or equal to
2984 // the stack alignment, ignore it. If the size is greater than or equal to
2985 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2986 unsigned StackAlign =
2987 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2988 if (Align <= StackAlign)
2991 // Round the size of the allocation up to the stack alignment size
2992 // by add SA-1 to the size.
2993 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2994 DAG.getIntPtrConstant(StackAlign-1));
2995 // Mask out the low bits for alignment purposes.
2996 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2997 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2999 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3000 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
3002 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
3004 DAG.setRoot(DSA.getValue(1));
3006 // Inform the Frame Information that we have just allocated a variable-sized
3008 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
3011 void SelectionDAGLowering::visitLoad(LoadInst &I) {
3012 const Value *SV = I.getOperand(0);
3013 SDValue Ptr = getValue(SV);
3015 const Type *Ty = I.getType();
3016 bool isVolatile = I.isVolatile();
3017 unsigned Alignment = I.getAlignment();
3019 SmallVector<MVT, 4> ValueVTs;
3020 SmallVector<uint64_t, 4> Offsets;
3021 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3022 unsigned NumValues = ValueVTs.size();
3027 bool ConstantMemory = false;
3029 // Serialize volatile loads with other side effects.
3031 else if (AA->pointsToConstantMemory(SV)) {
3032 // Do not serialize (non-volatile) loads of constant memory with anything.
3033 Root = DAG.getEntryNode();
3034 ConstantMemory = true;
3036 // Do not serialize non-volatile loads against each other.
3037 Root = DAG.getRoot();
3040 SmallVector<SDValue, 4> Values(NumValues);
3041 SmallVector<SDValue, 4> Chains(NumValues);
3042 MVT PtrVT = Ptr.getValueType();
3043 for (unsigned i = 0; i != NumValues; ++i) {
3044 SDValue L = DAG.getLoad(ValueVTs[i], Root,
3045 DAG.getNode(ISD::ADD, PtrVT, Ptr,
3046 DAG.getConstant(Offsets[i], PtrVT)),
3048 isVolatile, Alignment);
3050 Chains[i] = L.getValue(1);
3053 if (!ConstantMemory) {
3054 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3055 &Chains[0], NumValues);
3059 PendingLoads.push_back(Chain);
3062 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
3063 &Values[0], NumValues));
3067 void SelectionDAGLowering::visitStore(StoreInst &I) {
3068 Value *SrcV = I.getOperand(0);
3069 Value *PtrV = I.getOperand(1);
3071 SmallVector<MVT, 4> ValueVTs;
3072 SmallVector<uint64_t, 4> Offsets;
3073 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3074 unsigned NumValues = ValueVTs.size();
3078 // Get the lowered operands. Note that we do this after
3079 // checking if NumResults is zero, because with zero results
3080 // the operands won't have values in the map.
3081 SDValue Src = getValue(SrcV);
3082 SDValue Ptr = getValue(PtrV);
3084 SDValue Root = getRoot();
3085 SmallVector<SDValue, 4> Chains(NumValues);
3086 MVT PtrVT = Ptr.getValueType();
3087 bool isVolatile = I.isVolatile();
3088 unsigned Alignment = I.getAlignment();
3089 for (unsigned i = 0; i != NumValues; ++i)
3090 Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.getResNo() + i),
3091 DAG.getNode(ISD::ADD, PtrVT, Ptr,
3092 DAG.getConstant(Offsets[i], PtrVT)),
3094 isVolatile, Alignment);
3096 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
3099 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3101 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
3102 unsigned Intrinsic) {
3103 bool HasChain = !I.doesNotAccessMemory();
3104 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3106 // Build the operand list.
3107 SmallVector<SDValue, 8> Ops;
3108 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3110 // We don't need to serialize loads against other loads.
3111 Ops.push_back(DAG.getRoot());
3113 Ops.push_back(getRoot());
3117 // Add the intrinsic ID as an integer operand.
3118 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3120 // Add all operands of the call to the operand list.
3121 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
3122 SDValue Op = getValue(I.getOperand(i));
3123 assert(TLI.isTypeLegal(Op.getValueType()) &&
3124 "Intrinsic uses a non-legal type?");
3128 std::vector<MVT> VTs;
3129 if (I.getType() != Type::VoidTy) {
3130 MVT VT = TLI.getValueType(I.getType());
3131 if (VT.isVector()) {
3132 const VectorType *DestTy = cast<VectorType>(I.getType());
3133 MVT EltVT = TLI.getValueType(DestTy->getElementType());
3135 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
3136 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
3139 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
3143 VTs.push_back(MVT::Other);
3145 const MVT *VTList = DAG.getNodeValueTypes(VTs);
3150 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
3151 &Ops[0], Ops.size());
3152 else if (I.getType() != Type::VoidTy)
3153 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
3154 &Ops[0], Ops.size());
3156 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
3157 &Ops[0], Ops.size());
3160 SDValue Chain = Result.getValue(Result.Val->getNumValues()-1);
3162 PendingLoads.push_back(Chain);
3166 if (I.getType() != Type::VoidTy) {
3167 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3168 MVT VT = TLI.getValueType(PTy);
3169 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
3171 setValue(&I, Result);
3175 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3176 static GlobalVariable *ExtractTypeInfo (Value *V) {
3177 V = V->stripPointerCasts();
3178 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3179 assert ((GV || isa<ConstantPointerNull>(V)) &&
3180 "TypeInfo must be a global variable or NULL");
3184 /// addCatchInfo - Extract the personality and type infos from an eh.selector
3185 /// call, and add them to the specified machine basic block.
3186 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3187 MachineBasicBlock *MBB) {
3188 // Inform the MachineModuleInfo of the personality for this landing pad.
3189 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3190 assert(CE->getOpcode() == Instruction::BitCast &&
3191 isa<Function>(CE->getOperand(0)) &&
3192 "Personality should be a function");
3193 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3195 // Gather all the type infos for this landing pad and pass them along to
3196 // MachineModuleInfo.
3197 std::vector<GlobalVariable *> TyInfo;
3198 unsigned N = I.getNumOperands();
3200 for (unsigned i = N - 1; i > 2; --i) {
3201 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3202 unsigned FilterLength = CI->getZExtValue();
3203 unsigned FirstCatch = i + FilterLength + !FilterLength;
3204 assert (FirstCatch <= N && "Invalid filter length");
3206 if (FirstCatch < N) {
3207 TyInfo.reserve(N - FirstCatch);
3208 for (unsigned j = FirstCatch; j < N; ++j)
3209 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3210 MMI->addCatchTypeInfo(MBB, TyInfo);
3214 if (!FilterLength) {
3216 MMI->addCleanup(MBB);
3219 TyInfo.reserve(FilterLength - 1);
3220 for (unsigned j = i + 1; j < FirstCatch; ++j)
3221 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3222 MMI->addFilterTypeInfo(MBB, TyInfo);
3231 TyInfo.reserve(N - 3);
3232 for (unsigned j = 3; j < N; ++j)
3233 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3234 MMI->addCatchTypeInfo(MBB, TyInfo);
3239 /// Inlined utility function to implement binary input atomic intrinsics for
3240 // visitIntrinsicCall: I is a call instruction
3241 // Op is the associated NodeType for I
3243 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3244 SDValue Root = getRoot();
3245 SDValue L = DAG.getAtomic(Op, Root,
3246 getValue(I.getOperand(1)),
3247 getValue(I.getOperand(2)),
3250 DAG.setRoot(L.getValue(1));
3254 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3255 /// we want to emit this as a call to a named external function, return the name
3256 /// otherwise lower it and return null.
3258 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3259 switch (Intrinsic) {
3261 // By default, turn this into a target intrinsic node.
3262 visitTargetIntrinsic(I, Intrinsic);
3264 case Intrinsic::vastart: visitVAStart(I); return 0;
3265 case Intrinsic::vaend: visitVAEnd(I); return 0;
3266 case Intrinsic::vacopy: visitVACopy(I); return 0;
3267 case Intrinsic::returnaddress:
3268 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3269 getValue(I.getOperand(1))));
3271 case Intrinsic::frameaddress:
3272 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3273 getValue(I.getOperand(1))));
3275 case Intrinsic::setjmp:
3276 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3278 case Intrinsic::longjmp:
3279 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3281 case Intrinsic::memcpy_i32:
3282 case Intrinsic::memcpy_i64: {
3283 SDValue Op1 = getValue(I.getOperand(1));
3284 SDValue Op2 = getValue(I.getOperand(2));
3285 SDValue Op3 = getValue(I.getOperand(3));
3286 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3287 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3288 I.getOperand(1), 0, I.getOperand(2), 0));
3291 case Intrinsic::memset_i32:
3292 case Intrinsic::memset_i64: {
3293 SDValue Op1 = getValue(I.getOperand(1));
3294 SDValue Op2 = getValue(I.getOperand(2));
3295 SDValue Op3 = getValue(I.getOperand(3));
3296 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3297 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3298 I.getOperand(1), 0));
3301 case Intrinsic::memmove_i32:
3302 case Intrinsic::memmove_i64: {
3303 SDValue Op1 = getValue(I.getOperand(1));
3304 SDValue Op2 = getValue(I.getOperand(2));
3305 SDValue Op3 = getValue(I.getOperand(3));
3306 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3308 // If the source and destination are known to not be aliases, we can
3309 // lower memmove as memcpy.
3310 uint64_t Size = -1ULL;
3311 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3312 Size = C->getValue();
3313 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3314 AliasAnalysis::NoAlias) {
3315 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3316 I.getOperand(1), 0, I.getOperand(2), 0));
3320 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3321 I.getOperand(1), 0, I.getOperand(2), 0));
3324 case Intrinsic::dbg_stoppoint: {
3325 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3326 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3327 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
3328 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
3329 assert(DD && "Not a debug information descriptor");
3330 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3333 cast<CompileUnitDesc>(DD)));
3338 case Intrinsic::dbg_region_start: {
3339 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3340 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3341 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3342 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
3343 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3348 case Intrinsic::dbg_region_end: {
3349 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3350 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3351 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3352 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
3353 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3358 case Intrinsic::dbg_func_start: {
3359 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3361 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3362 Value *SP = FSI.getSubprogram();
3363 if (SP && MMI->Verify(SP)) {
3364 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3365 // what (most?) gdb expects.
3366 DebugInfoDesc *DD = MMI->getDescFor(SP);
3367 assert(DD && "Not a debug information descriptor");
3368 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3369 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
3370 unsigned SrcFile = MMI->RecordSource(CompileUnit);
3371 // Record the source line but does create a label. It will be emitted
3372 // at asm emission time.
3373 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3378 case Intrinsic::dbg_declare: {
3379 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3380 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3381 Value *Variable = DI.getVariable();
3382 if (MMI && Variable && MMI->Verify(Variable))
3383 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3384 getValue(DI.getAddress()), getValue(Variable)));
3388 case Intrinsic::eh_exception: {
3389 if (!CurMBB->isLandingPad()) {
3390 // FIXME: Mark exception register as live in. Hack for PR1508.
3391 unsigned Reg = TLI.getExceptionAddressRegister();
3392 if (Reg) CurMBB->addLiveIn(Reg);
3394 // Insert the EXCEPTIONADDR instruction.
3395 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3397 Ops[0] = DAG.getRoot();
3398 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3400 DAG.setRoot(Op.getValue(1));
3404 case Intrinsic::eh_selector_i32:
3405 case Intrinsic::eh_selector_i64: {
3406 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3407 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3408 MVT::i32 : MVT::i64);
3411 if (CurMBB->isLandingPad())
3412 addCatchInfo(I, MMI, CurMBB);
3415 FuncInfo.CatchInfoLost.insert(&I);
3417 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3418 unsigned Reg = TLI.getExceptionSelectorRegister();
3419 if (Reg) CurMBB->addLiveIn(Reg);
3422 // Insert the EHSELECTION instruction.
3423 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3425 Ops[0] = getValue(I.getOperand(1));
3427 SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3429 DAG.setRoot(Op.getValue(1));
3431 setValue(&I, DAG.getConstant(0, VT));
3437 case Intrinsic::eh_typeid_for_i32:
3438 case Intrinsic::eh_typeid_for_i64: {
3439 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3440 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3441 MVT::i32 : MVT::i64);
3444 // Find the type id for the given typeinfo.
3445 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3447 unsigned TypeID = MMI->getTypeIDFor(GV);
3448 setValue(&I, DAG.getConstant(TypeID, VT));
3450 // Return something different to eh_selector.
3451 setValue(&I, DAG.getConstant(1, VT));
3457 case Intrinsic::eh_return: {
3458 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3461 MMI->setCallsEHReturn(true);
3462 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3465 getValue(I.getOperand(1)),
3466 getValue(I.getOperand(2))));
3468 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3474 case Intrinsic::eh_unwind_init: {
3475 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3476 MMI->setCallsUnwindInit(true);
3482 case Intrinsic::eh_dwarf_cfa: {
3483 MVT VT = getValue(I.getOperand(1)).getValueType();
3485 if (VT.bitsGT(TLI.getPointerTy()))
3486 CfaArg = DAG.getNode(ISD::TRUNCATE,
3487 TLI.getPointerTy(), getValue(I.getOperand(1)));
3489 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3490 TLI.getPointerTy(), getValue(I.getOperand(1)));
3492 SDValue Offset = DAG.getNode(ISD::ADD,
3494 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3495 TLI.getPointerTy()),
3497 setValue(&I, DAG.getNode(ISD::ADD,
3499 DAG.getNode(ISD::FRAMEADDR,
3502 TLI.getPointerTy())),
3507 case Intrinsic::sqrt:
3508 setValue(&I, DAG.getNode(ISD::FSQRT,
3509 getValue(I.getOperand(1)).getValueType(),
3510 getValue(I.getOperand(1))));
3512 case Intrinsic::powi:
3513 setValue(&I, DAG.getNode(ISD::FPOWI,
3514 getValue(I.getOperand(1)).getValueType(),
3515 getValue(I.getOperand(1)),
3516 getValue(I.getOperand(2))));
3518 case Intrinsic::sin:
3519 setValue(&I, DAG.getNode(ISD::FSIN,
3520 getValue(I.getOperand(1)).getValueType(),
3521 getValue(I.getOperand(1))));
3523 case Intrinsic::cos:
3524 setValue(&I, DAG.getNode(ISD::FCOS,
3525 getValue(I.getOperand(1)).getValueType(),
3526 getValue(I.getOperand(1))));
3528 case Intrinsic::pow:
3529 setValue(&I, DAG.getNode(ISD::FPOW,
3530 getValue(I.getOperand(1)).getValueType(),
3531 getValue(I.getOperand(1)),
3532 getValue(I.getOperand(2))));
3534 case Intrinsic::pcmarker: {
3535 SDValue Tmp = getValue(I.getOperand(1));
3536 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3539 case Intrinsic::readcyclecounter: {
3540 SDValue Op = getRoot();
3541 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3542 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3545 DAG.setRoot(Tmp.getValue(1));
3548 case Intrinsic::part_select: {
3549 // Currently not implemented: just abort
3550 assert(0 && "part_select intrinsic not implemented");
3553 case Intrinsic::part_set: {
3554 // Currently not implemented: just abort
3555 assert(0 && "part_set intrinsic not implemented");
3558 case Intrinsic::bswap:
3559 setValue(&I, DAG.getNode(ISD::BSWAP,
3560 getValue(I.getOperand(1)).getValueType(),
3561 getValue(I.getOperand(1))));
3563 case Intrinsic::cttz: {
3564 SDValue Arg = getValue(I.getOperand(1));
3565 MVT Ty = Arg.getValueType();
3566 SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3567 setValue(&I, result);
3570 case Intrinsic::ctlz: {
3571 SDValue Arg = getValue(I.getOperand(1));
3572 MVT Ty = Arg.getValueType();
3573 SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3574 setValue(&I, result);
3577 case Intrinsic::ctpop: {
3578 SDValue Arg = getValue(I.getOperand(1));
3579 MVT Ty = Arg.getValueType();
3580 SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3581 setValue(&I, result);
3584 case Intrinsic::stacksave: {
3585 SDValue Op = getRoot();
3586 SDValue Tmp = DAG.getNode(ISD::STACKSAVE,
3587 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3589 DAG.setRoot(Tmp.getValue(1));
3592 case Intrinsic::stackrestore: {
3593 SDValue Tmp = getValue(I.getOperand(1));
3594 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3597 case Intrinsic::var_annotation:
3598 // Discard annotate attributes
3601 case Intrinsic::init_trampoline: {
3602 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3606 Ops[1] = getValue(I.getOperand(1));
3607 Ops[2] = getValue(I.getOperand(2));
3608 Ops[3] = getValue(I.getOperand(3));
3609 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3610 Ops[5] = DAG.getSrcValue(F);
3612 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE,
3613 DAG.getNodeValueTypes(TLI.getPointerTy(),
3618 DAG.setRoot(Tmp.getValue(1));
3622 case Intrinsic::gcroot:
3624 Value *Alloca = I.getOperand(1);
3625 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3627 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3628 GFI->addStackRoot(FI->getIndex(), TypeMap);
3632 case Intrinsic::gcread:
3633 case Intrinsic::gcwrite:
3634 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
3637 case Intrinsic::flt_rounds: {
3638 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3642 case Intrinsic::trap: {
3643 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3646 case Intrinsic::prefetch: {
3649 Ops[1] = getValue(I.getOperand(1));
3650 Ops[2] = getValue(I.getOperand(2));
3651 Ops[3] = getValue(I.getOperand(3));
3652 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3656 case Intrinsic::memory_barrier: {
3659 for (int x = 1; x < 6; ++x)
3660 Ops[x] = getValue(I.getOperand(x));
3662 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3665 case Intrinsic::atomic_cmp_swap: {
3666 SDValue Root = getRoot();
3668 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3670 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_8, Root,
3671 getValue(I.getOperand(1)),
3672 getValue(I.getOperand(2)),
3673 getValue(I.getOperand(3)),
3677 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_16, Root,
3678 getValue(I.getOperand(1)),
3679 getValue(I.getOperand(2)),
3680 getValue(I.getOperand(3)),
3684 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_32, Root,
3685 getValue(I.getOperand(1)),
3686 getValue(I.getOperand(2)),
3687 getValue(I.getOperand(3)),
3691 L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_64, Root,
3692 getValue(I.getOperand(1)),
3693 getValue(I.getOperand(2)),
3694 getValue(I.getOperand(3)),
3698 assert(0 && "Invalid atomic type");
3702 DAG.setRoot(L.getValue(1));
3705 case Intrinsic::atomic_load_add:
3706 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3708 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_8);
3710 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_16);
3712 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_32);
3714 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_64);
3716 assert(0 && "Invalid atomic type");
3719 case Intrinsic::atomic_load_sub:
3720 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3722 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_8);
3724 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_16);
3726 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_32);
3728 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_64);
3730 assert(0 && "Invalid atomic type");
3733 case Intrinsic::atomic_load_or:
3734 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3736 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_8);
3738 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_16);
3740 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_32);
3742 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_64);
3744 assert(0 && "Invalid atomic type");
3747 case Intrinsic::atomic_load_xor:
3748 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3750 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_8);
3752 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_16);
3754 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_32);
3756 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_64);
3758 assert(0 && "Invalid atomic type");
3761 case Intrinsic::atomic_load_and:
3762 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3764 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_8);
3766 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_16);
3768 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_32);
3770 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_64);
3772 assert(0 && "Invalid atomic type");
3775 case Intrinsic::atomic_load_nand:
3776 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3778 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_8);
3780 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_16);
3782 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_32);
3784 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_64);
3786 assert(0 && "Invalid atomic type");
3789 case Intrinsic::atomic_load_max:
3790 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3792 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_8);
3794 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_16);
3796 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_32);
3798 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_64);
3800 assert(0 && "Invalid atomic type");
3803 case Intrinsic::atomic_load_min:
3804 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3806 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_8);
3808 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_16);
3810 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_32);
3812 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_64);
3814 assert(0 && "Invalid atomic type");
3817 case Intrinsic::atomic_load_umin:
3818 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3820 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_8);
3822 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_16);
3824 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_32);
3826 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_64);
3828 assert(0 && "Invalid atomic type");
3831 case Intrinsic::atomic_load_umax:
3832 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3834 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_8);
3836 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_16);
3838 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_32);
3840 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_64);
3842 assert(0 && "Invalid atomic type");
3845 case Intrinsic::atomic_swap:
3846 switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) {
3848 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_8);
3850 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_16);
3852 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_32);
3854 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_64);
3856 assert(0 && "Invalid atomic type");
3863 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
3865 MachineBasicBlock *LandingPad) {
3866 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3867 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3868 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3869 unsigned BeginLabel = 0, EndLabel = 0;
3871 TargetLowering::ArgListTy Args;
3872 TargetLowering::ArgListEntry Entry;
3873 Args.reserve(CS.arg_size());
3874 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3876 SDValue ArgNode = getValue(*i);
3877 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3879 unsigned attrInd = i - CS.arg_begin() + 1;
3880 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3881 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3882 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3883 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3884 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3885 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3886 Entry.Alignment = CS.getParamAlignment(attrInd);
3887 Args.push_back(Entry);
3890 if (LandingPad && MMI) {
3891 // Insert a label before the invoke call to mark the try range. This can be
3892 // used to detect deletion of the invoke via the MachineModuleInfo.
3893 BeginLabel = MMI->NextLabelID();
3894 // Both PendingLoads and PendingExports must be flushed here;
3895 // this call might not return.
3897 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
3900 std::pair<SDValue,SDValue> Result =
3901 TLI.LowerCallTo(getRoot(), CS.getType(),
3902 CS.paramHasAttr(0, ParamAttr::SExt),
3903 CS.paramHasAttr(0, ParamAttr::ZExt),
3904 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3906 if (CS.getType() != Type::VoidTy)
3907 setValue(CS.getInstruction(), Result.first);
3908 DAG.setRoot(Result.second);
3910 if (LandingPad && MMI) {
3911 // Insert a label at the end of the invoke call to mark the try range. This
3912 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3913 EndLabel = MMI->NextLabelID();
3914 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
3916 // Inform MachineModuleInfo of range.
3917 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3922 void SelectionDAGLowering::visitCall(CallInst &I) {
3923 const char *RenameFn = 0;
3924 if (Function *F = I.getCalledFunction()) {
3925 if (F->isDeclaration()) {
3926 if (unsigned IID = F->getIntrinsicID()) {
3927 RenameFn = visitIntrinsicCall(I, IID);
3933 // Check for well-known libc/libm calls. If the function is internal, it
3934 // can't be a library call.
3935 unsigned NameLen = F->getNameLen();
3936 if (!F->hasInternalLinkage() && NameLen) {
3937 const char *NameStr = F->getNameStart();
3938 if (NameStr[0] == 'c' &&
3939 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3940 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3941 if (I.getNumOperands() == 3 && // Basic sanity checks.
3942 I.getOperand(1)->getType()->isFloatingPoint() &&
3943 I.getType() == I.getOperand(1)->getType() &&
3944 I.getType() == I.getOperand(2)->getType()) {
3945 SDValue LHS = getValue(I.getOperand(1));
3946 SDValue RHS = getValue(I.getOperand(2));
3947 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3951 } else if (NameStr[0] == 'f' &&
3952 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3953 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3954 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3955 if (I.getNumOperands() == 2 && // Basic sanity checks.
3956 I.getOperand(1)->getType()->isFloatingPoint() &&
3957 I.getType() == I.getOperand(1)->getType()) {
3958 SDValue Tmp = getValue(I.getOperand(1));
3959 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3962 } else if (NameStr[0] == 's' &&
3963 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3964 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3965 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3966 if (I.getNumOperands() == 2 && // Basic sanity checks.
3967 I.getOperand(1)->getType()->isFloatingPoint() &&
3968 I.getType() == I.getOperand(1)->getType()) {
3969 SDValue Tmp = getValue(I.getOperand(1));
3970 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3973 } else if (NameStr[0] == 'c' &&
3974 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3975 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3976 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3977 if (I.getNumOperands() == 2 && // Basic sanity checks.
3978 I.getOperand(1)->getType()->isFloatingPoint() &&
3979 I.getType() == I.getOperand(1)->getType()) {
3980 SDValue Tmp = getValue(I.getOperand(1));
3981 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3986 } else if (isa<InlineAsm>(I.getOperand(0))) {
3993 Callee = getValue(I.getOperand(0));
3995 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3997 LowerCallTo(&I, Callee, I.isTailCall());
4001 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4002 /// this value and returns the result as a ValueVT value. This uses
4003 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4004 /// If the Flag pointer is NULL, no flag is used.
4005 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
4007 SDValue *Flag) const {
4008 // Assemble the legal parts into the final values.
4009 SmallVector<SDValue, 4> Values(ValueVTs.size());
4010 SmallVector<SDValue, 8> Parts;
4011 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4012 // Copy the legal parts from the registers.
4013 MVT ValueVT = ValueVTs[Value];
4014 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4015 MVT RegisterVT = RegVTs[Value];
4017 Parts.resize(NumRegs);
4018 for (unsigned i = 0; i != NumRegs; ++i) {
4021 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
4023 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
4024 *Flag = P.getValue(2);
4026 Chain = P.getValue(1);
4028 // If the source register was virtual and if we know something about it,
4029 // add an assert node.
4030 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4031 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4032 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4033 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4034 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4035 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4037 unsigned RegSize = RegisterVT.getSizeInBits();
4038 unsigned NumSignBits = LOI.NumSignBits;
4039 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4041 // FIXME: We capture more information than the dag can represent. For
4042 // now, just use the tightest assertzext/assertsext possible.
4044 MVT FromVT(MVT::Other);
4045 if (NumSignBits == RegSize)
4046 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4047 else if (NumZeroBits >= RegSize-1)
4048 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4049 else if (NumSignBits > RegSize-8)
4050 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4051 else if (NumZeroBits >= RegSize-9)
4052 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4053 else if (NumSignBits > RegSize-16)
4054 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4055 else if (NumZeroBits >= RegSize-17)
4056 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4057 else if (NumSignBits > RegSize-32)
4058 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4059 else if (NumZeroBits >= RegSize-33)
4060 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4062 if (FromVT != MVT::Other) {
4063 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
4064 RegisterVT, P, DAG.getValueType(FromVT));
4073 Values[Value] = getCopyFromParts(DAG, Parts.begin(), NumRegs, RegisterVT,
4079 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4080 &Values[0], ValueVTs.size());
4083 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4084 /// specified value into the registers specified by this object. This uses
4085 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4086 /// If the Flag pointer is NULL, no flag is used.
4087 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
4088 SDValue &Chain, SDValue *Flag) const {
4089 // Get the list of the values's legal parts.
4090 unsigned NumRegs = Regs.size();
4091 SmallVector<SDValue, 8> Parts(NumRegs);
4092 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4093 MVT ValueVT = ValueVTs[Value];
4094 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4095 MVT RegisterVT = RegVTs[Value];
4097 getCopyToParts(DAG, Val.getValue(Val.getResNo() + Value),
4098 &Parts[Part], NumParts, RegisterVT);
4102 // Copy the parts into the registers.
4103 SmallVector<SDValue, 8> Chains(NumRegs);
4104 for (unsigned i = 0; i != NumRegs; ++i) {
4107 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
4109 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
4110 *Flag = Part.getValue(1);
4112 Chains[i] = Part.getValue(0);
4115 if (NumRegs == 1 || Flag)
4116 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4117 // flagged to it. That is the CopyToReg nodes and the user are considered
4118 // a single scheduling unit. If we create a TokenFactor and return it as
4119 // chain, then the TokenFactor is both a predecessor (operand) of the
4120 // user as well as a successor (the TF operands are flagged to the user).
4121 // c1, f1 = CopyToReg
4122 // c2, f2 = CopyToReg
4123 // c3 = TokenFactor c1, c2
4126 Chain = Chains[NumRegs-1];
4128 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4131 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4132 /// operand list. This adds the code marker and includes the number of
4133 /// values added into it.
4134 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
4135 std::vector<SDValue> &Ops) const {
4136 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4137 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
4138 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4139 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4140 MVT RegisterVT = RegVTs[Value];
4141 for (unsigned i = 0; i != NumRegs; ++i)
4142 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4146 /// isAllocatableRegister - If the specified register is safe to allocate,
4147 /// i.e. it isn't a stack pointer or some other special register, return the
4148 /// register class for the register. Otherwise, return null.
4149 static const TargetRegisterClass *
4150 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4151 const TargetLowering &TLI,
4152 const TargetRegisterInfo *TRI) {
4153 MVT FoundVT = MVT::Other;
4154 const TargetRegisterClass *FoundRC = 0;
4155 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4156 E = TRI->regclass_end(); RCI != E; ++RCI) {
4157 MVT ThisVT = MVT::Other;
4159 const TargetRegisterClass *RC = *RCI;
4160 // If none of the the value types for this register class are valid, we
4161 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4162 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4164 if (TLI.isTypeLegal(*I)) {
4165 // If we have already found this register in a different register class,
4166 // choose the one with the largest VT specified. For example, on
4167 // PowerPC, we favor f64 register classes over f32.
4168 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4175 if (ThisVT == MVT::Other) continue;
4177 // NOTE: This isn't ideal. In particular, this might allocate the
4178 // frame pointer in functions that need it (due to them not being taken
4179 // out of allocation, because a variable sized allocation hasn't been seen
4180 // yet). This is a slight code pessimization, but should still work.
4181 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4182 E = RC->allocation_order_end(MF); I != E; ++I)
4184 // We found a matching register class. Keep looking at others in case
4185 // we find one with larger registers that this physreg is also in.
4196 /// AsmOperandInfo - This contains information for each constraint that we are
4198 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
4199 /// CallOperand - If this is the result output operand or a clobber
4200 /// this is null, otherwise it is the incoming operand to the CallInst.
4201 /// This gets modified as the asm is processed.
4202 SDValue CallOperand;
4204 /// AssignedRegs - If this is a register or register class operand, this
4205 /// contains the set of register corresponding to the operand.
4206 RegsForValue AssignedRegs;
4208 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4209 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4212 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4213 /// busy in OutputRegs/InputRegs.
4214 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4215 std::set<unsigned> &OutputRegs,
4216 std::set<unsigned> &InputRegs,
4217 const TargetRegisterInfo &TRI) const {
4219 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4220 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4223 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4224 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4229 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4231 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4232 const TargetRegisterInfo &TRI) {
4233 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4235 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4236 for (; *Aliases; ++Aliases)
4237 Regs.insert(*Aliases);
4240 } // end anon namespace.
4243 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4244 /// specified operand. We prefer to assign virtual registers, to allow the
4245 /// register allocator handle the assignment process. However, if the asm uses
4246 /// features that we can't model on machineinstrs, we have SDISel do the
4247 /// allocation. This produces generally horrible, but correct, code.
4249 /// OpInfo describes the operand.
4250 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
4251 /// or any explicitly clobbered registers.
4252 /// Input and OutputRegs are the set of already allocated physical registers.
4254 void SelectionDAGLowering::
4255 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
4256 std::set<unsigned> &OutputRegs,
4257 std::set<unsigned> &InputRegs) {
4258 // Compute whether this value requires an input register, an output register,
4260 bool isOutReg = false;
4261 bool isInReg = false;
4262 switch (OpInfo.Type) {
4263 case InlineAsm::isOutput:
4266 // If this is an early-clobber output, or if there is an input
4267 // constraint that matches this, we need to reserve the input register
4268 // so no other inputs allocate to it.
4269 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
4271 case InlineAsm::isInput:
4275 case InlineAsm::isClobber:
4282 MachineFunction &MF = DAG.getMachineFunction();
4283 SmallVector<unsigned, 4> Regs;
4285 // If this is a constraint for a single physreg, or a constraint for a
4286 // register class, find it.
4287 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4288 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4289 OpInfo.ConstraintVT);
4291 unsigned NumRegs = 1;
4292 if (OpInfo.ConstraintVT != MVT::Other)
4293 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4295 MVT ValueVT = OpInfo.ConstraintVT;
4298 // If this is a constraint for a specific physical register, like {r17},
4300 if (PhysReg.first) {
4301 if (OpInfo.ConstraintVT == MVT::Other)
4302 ValueVT = *PhysReg.second->vt_begin();
4304 // Get the actual register value type. This is important, because the user
4305 // may have asked for (e.g.) the AX register in i32 type. We need to
4306 // remember that AX is actually i16 to get the right extension.
4307 RegVT = *PhysReg.second->vt_begin();
4309 // This is a explicit reference to a physical register.
4310 Regs.push_back(PhysReg.first);
4312 // If this is an expanded reference, add the rest of the regs to Regs.
4314 TargetRegisterClass::iterator I = PhysReg.second->begin();
4315 for (; *I != PhysReg.first; ++I)
4316 assert(I != PhysReg.second->end() && "Didn't find reg!");
4318 // Already added the first reg.
4320 for (; NumRegs; --NumRegs, ++I) {
4321 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4325 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4326 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4327 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4331 // Otherwise, if this was a reference to an LLVM register class, create vregs
4332 // for this reference.
4333 std::vector<unsigned> RegClassRegs;
4334 const TargetRegisterClass *RC = PhysReg.second;
4336 // If this is an early clobber or tied register, our regalloc doesn't know
4337 // how to maintain the constraint. If it isn't, go ahead and create vreg
4338 // and let the regalloc do the right thing.
4339 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
4340 // If there is some other early clobber and this is an input register,
4341 // then we are forced to pre-allocate the input reg so it doesn't
4342 // conflict with the earlyclobber.
4343 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
4344 RegVT = *PhysReg.second->vt_begin();
4346 if (OpInfo.ConstraintVT == MVT::Other)
4349 // Create the appropriate number of virtual registers.
4350 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4351 for (; NumRegs; --NumRegs)
4352 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4354 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4358 // Otherwise, we can't allocate it. Let the code below figure out how to
4359 // maintain these constraints.
4360 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4363 // This is a reference to a register class that doesn't directly correspond
4364 // to an LLVM register class. Allocate NumRegs consecutive, available,
4365 // registers from the class.
4366 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4367 OpInfo.ConstraintVT);
4370 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4371 unsigned NumAllocated = 0;
4372 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4373 unsigned Reg = RegClassRegs[i];
4374 // See if this register is available.
4375 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4376 (isInReg && InputRegs.count(Reg))) { // Already used.
4377 // Make sure we find consecutive registers.
4382 // Check to see if this register is allocatable (i.e. don't give out the
4385 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4386 if (!RC) { // Couldn't allocate this register.
4387 // Reset NumAllocated to make sure we return consecutive registers.
4393 // Okay, this register is good, we can use it.
4396 // If we allocated enough consecutive registers, succeed.
4397 if (NumAllocated == NumRegs) {
4398 unsigned RegStart = (i-NumAllocated)+1;
4399 unsigned RegEnd = i+1;
4400 // Mark all of the allocated registers used.
4401 for (unsigned i = RegStart; i != RegEnd; ++i)
4402 Regs.push_back(RegClassRegs[i]);
4404 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4405 OpInfo.ConstraintVT);
4406 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4411 // Otherwise, we couldn't allocate enough registers for this.
4415 /// visitInlineAsm - Handle a call to an InlineAsm object.
4417 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4418 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4420 /// ConstraintOperands - Information about all of the constraints.
4421 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4423 SDValue Chain = getRoot();
4426 std::set<unsigned> OutputRegs, InputRegs;
4428 // Do a prepass over the constraints, canonicalizing them, and building up the
4429 // ConstraintOperands list.
4430 std::vector<InlineAsm::ConstraintInfo>
4431 ConstraintInfos = IA->ParseConstraints();
4433 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
4434 // constraint. If so, we can't let the register allocator allocate any input
4435 // registers, because it will not know to avoid the earlyclobbered output reg.
4436 bool SawEarlyClobber = false;
4438 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4439 unsigned ResNo = 0; // ResNo - The result number of the next output.
4440 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4441 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4442 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4444 MVT OpVT = MVT::Other;
4446 // Compute the value type for each operand.
4447 switch (OpInfo.Type) {
4448 case InlineAsm::isOutput:
4449 // Indirect outputs just consume an argument.
4450 if (OpInfo.isIndirect) {
4451 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4454 // The return value of the call is this value. As such, there is no
4455 // corresponding argument.
4456 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4457 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4458 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4460 assert(ResNo == 0 && "Asm only has one result!");
4461 OpVT = TLI.getValueType(CS.getType());
4465 case InlineAsm::isInput:
4466 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4468 case InlineAsm::isClobber:
4473 // If this is an input or an indirect output, process the call argument.
4474 // BasicBlocks are labels, currently appearing only in asm's.
4475 if (OpInfo.CallOperandVal) {
4476 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
4477 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
4479 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4480 const Type *OpTy = OpInfo.CallOperandVal->getType();
4481 // If this is an indirect operand, the operand is a pointer to the
4483 if (OpInfo.isIndirect)
4484 OpTy = cast<PointerType>(OpTy)->getElementType();
4486 // If OpTy is not a single value, it may be a struct/union that we
4487 // can tile with integers.
4488 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4489 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4497 OpTy = IntegerType::get(BitSize);
4502 OpVT = TLI.getValueType(OpTy, true);
4506 OpInfo.ConstraintVT = OpVT;
4508 // Compute the constraint code and ConstraintType to use.
4509 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
4511 // Keep track of whether we see an earlyclobber.
4512 SawEarlyClobber |= OpInfo.isEarlyClobber;
4514 // If we see a clobber of a register, it is an early clobber.
4515 if (!SawEarlyClobber &&
4516 OpInfo.Type == InlineAsm::isClobber &&
4517 OpInfo.ConstraintType == TargetLowering::C_Register) {
4518 // Note that we want to ignore things that we don't track here, like
4519 // dirflag, fpsr, flags, etc.
4520 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4521 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4522 OpInfo.ConstraintVT);
4523 if (PhysReg.first || PhysReg.second) {
4524 // This is a register we know of.
4525 SawEarlyClobber = true;
4529 // If this is a memory input, and if the operand is not indirect, do what we
4530 // need to to provide an address for the memory input.
4531 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4532 !OpInfo.isIndirect) {
4533 assert(OpInfo.Type == InlineAsm::isInput &&
4534 "Can only indirectify direct input operands!");
4536 // Memory operands really want the address of the value. If we don't have
4537 // an indirect input, put it in the constpool if we can, otherwise spill
4538 // it to a stack slot.
4540 // If the operand is a float, integer, or vector constant, spill to a
4541 // constant pool entry to get its address.
4542 Value *OpVal = OpInfo.CallOperandVal;
4543 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4544 isa<ConstantVector>(OpVal)) {
4545 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4546 TLI.getPointerTy());
4548 // Otherwise, create a stack slot and emit a store to it before the
4550 const Type *Ty = OpVal->getType();
4551 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
4552 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4553 MachineFunction &MF = DAG.getMachineFunction();
4554 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
4555 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4556 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4557 OpInfo.CallOperand = StackSlot;
4560 // There is no longer a Value* corresponding to this operand.
4561 OpInfo.CallOperandVal = 0;
4562 // It is now an indirect operand.
4563 OpInfo.isIndirect = true;
4566 // If this constraint is for a specific register, allocate it before
4568 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4569 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4571 ConstraintInfos.clear();
4574 // Second pass - Loop over all of the operands, assigning virtual or physregs
4575 // to registerclass operands.
4576 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4577 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4579 // C_Register operands have already been allocated, Other/Memory don't need
4581 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4582 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4585 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4586 std::vector<SDValue> AsmNodeOperands;
4587 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
4588 AsmNodeOperands.push_back(
4589 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4592 // Loop over all of the inputs, copying the operand values into the
4593 // appropriate registers and processing the output regs.
4594 RegsForValue RetValRegs;
4596 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4597 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4599 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4600 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4602 switch (OpInfo.Type) {
4603 case InlineAsm::isOutput: {
4604 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4605 OpInfo.ConstraintType != TargetLowering::C_Register) {
4606 // Memory output, or 'other' output (e.g. 'X' constraint).
4607 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4609 // Add information to the INLINEASM node to know about this output.
4610 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4611 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4612 TLI.getPointerTy()));
4613 AsmNodeOperands.push_back(OpInfo.CallOperand);
4617 // Otherwise, this is a register or register class output.
4619 // Copy the output from the appropriate register. Find a register that
4621 if (OpInfo.AssignedRegs.Regs.empty()) {
4622 cerr << "Couldn't allocate output reg for constraint '"
4623 << OpInfo.ConstraintCode << "'!\n";
4627 // If this is an indirect operand, store through the pointer after the
4629 if (OpInfo.isIndirect) {
4630 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4631 OpInfo.CallOperandVal));
4633 // This is the result value of the call.
4634 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4635 // Concatenate this output onto the outputs list.
4636 RetValRegs.append(OpInfo.AssignedRegs);
4639 // Add information to the INLINEASM node to know that this register is
4641 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
4645 case InlineAsm::isInput: {
4646 SDValue InOperandVal = OpInfo.CallOperand;
4648 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
4649 // If this is required to match an output register we have already set,
4650 // just use its register.
4651 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
4653 // Scan until we find the definition we already emitted of this operand.
4654 // When we find it, create a RegsForValue operand.
4655 unsigned CurOp = 2; // The first operand.
4656 for (; OperandNo; --OperandNo) {
4657 // Advance to the next operand.
4659 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4660 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4661 (NumOps & 7) == 4 /*MEM*/) &&
4662 "Skipped past definitions?");
4663 CurOp += (NumOps>>3)+1;
4667 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4668 if ((NumOps & 7) == 2 /*REGDEF*/) {
4669 // Add NumOps>>3 registers to MatchedRegs.
4670 RegsForValue MatchedRegs;
4671 MatchedRegs.TLI = &TLI;
4672 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4673 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4674 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4676 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4677 MatchedRegs.Regs.push_back(Reg);
4680 // Use the produced MatchedRegs object to
4681 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4682 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4685 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
4686 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4687 // Add information to the INLINEASM node to know about this input.
4688 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4689 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4690 TLI.getPointerTy()));
4691 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4696 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4697 assert(!OpInfo.isIndirect &&
4698 "Don't know how to handle indirect other inputs yet!");
4700 std::vector<SDValue> Ops;
4701 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4704 cerr << "Invalid operand for inline asm constraint '"
4705 << OpInfo.ConstraintCode << "'!\n";
4709 // Add information to the INLINEASM node to know about this input.
4710 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4711 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4712 TLI.getPointerTy()));
4713 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4715 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4716 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4717 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4718 "Memory operands expect pointer values");
4720 // Add information to the INLINEASM node to know about this input.
4721 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4722 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4723 TLI.getPointerTy()));
4724 AsmNodeOperands.push_back(InOperandVal);
4728 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4729 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4730 "Unknown constraint type!");
4731 assert(!OpInfo.isIndirect &&
4732 "Don't know how to handle indirect register inputs yet!");
4734 // Copy the input into the appropriate registers.
4735 assert(!OpInfo.AssignedRegs.Regs.empty() &&
4736 "Couldn't allocate input reg!");
4738 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4740 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
4744 case InlineAsm::isClobber: {
4745 // Add the clobbered value to the operand list, so that the register
4746 // allocator is aware that the physreg got clobbered.
4747 if (!OpInfo.AssignedRegs.Regs.empty())
4748 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
4755 // Finish up input operands.
4756 AsmNodeOperands[0] = Chain;
4757 if (Flag.Val) AsmNodeOperands.push_back(Flag);
4759 Chain = DAG.getNode(ISD::INLINEASM,
4760 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4761 &AsmNodeOperands[0], AsmNodeOperands.size());
4762 Flag = Chain.getValue(1);
4764 // If this asm returns a register value, copy the result from that register
4765 // and set it as the value of the call.
4766 if (!RetValRegs.Regs.empty()) {
4767 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4769 // If any of the results of the inline asm is a vector, it may have the
4770 // wrong width/num elts. This can happen for register classes that can
4771 // contain multiple different value types. The preg or vreg allocated may
4772 // not have the same VT as was expected. Convert it to the right type with
4774 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4775 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
4776 if (Val.Val->getValueType(i).isVector())
4777 Val = DAG.getNode(ISD::BIT_CONVERT,
4778 TLI.getValueType(ResSTy->getElementType(i)), Val);
4781 if (Val.getValueType().isVector())
4782 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4786 setValue(CS.getInstruction(), Val);
4789 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
4791 // Process indirect outputs, first output all of the flagged copies out of
4793 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
4794 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
4795 Value *Ptr = IndirectStoresToEmit[i].second;
4796 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
4797 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
4800 // Emit the non-flagged stores from the physregs.
4801 SmallVector<SDValue, 8> OutChains;
4802 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
4803 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
4804 getValue(StoresToEmit[i].second),
4805 StoresToEmit[i].second, 0));
4806 if (!OutChains.empty())
4807 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4808 &OutChains[0], OutChains.size());
4813 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4814 SDValue Src = getValue(I.getOperand(0));
4816 MVT IntPtr = TLI.getPointerTy();
4818 if (IntPtr.bitsLT(Src.getValueType()))
4819 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4820 else if (IntPtr.bitsGT(Src.getValueType()))
4821 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4823 // Scale the source by the type size.
4824 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4825 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4826 Src, DAG.getIntPtrConstant(ElementSize));
4828 TargetLowering::ArgListTy Args;
4829 TargetLowering::ArgListEntry Entry;
4831 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4832 Args.push_back(Entry);
4834 std::pair<SDValue,SDValue> Result =
4835 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4836 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4837 setValue(&I, Result.first); // Pointers always fit in registers
4838 DAG.setRoot(Result.second);
4841 void SelectionDAGLowering::visitFree(FreeInst &I) {
4842 TargetLowering::ArgListTy Args;
4843 TargetLowering::ArgListEntry Entry;
4844 Entry.Node = getValue(I.getOperand(0));
4845 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4846 Args.push_back(Entry);
4847 MVT IntPtr = TLI.getPointerTy();
4848 std::pair<SDValue,SDValue> Result =
4849 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4850 CallingConv::C, true,
4851 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4852 DAG.setRoot(Result.second);
4855 // EmitInstrWithCustomInserter - This method should be implemented by targets
4856 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4857 // instructions are special in various ways, which require special support to
4858 // insert. The specified MachineInstr is created but not inserted into any
4859 // basic blocks, and the scheduler passes ownership of it to this method.
4860 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4861 MachineBasicBlock *MBB) {
4862 cerr << "If a target marks an instruction with "
4863 << "'usesCustomDAGSchedInserter', it must implement "
4864 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4869 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4870 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4871 getValue(I.getOperand(1)),
4872 DAG.getSrcValue(I.getOperand(1))));
4875 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4876 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4877 getValue(I.getOperand(0)),
4878 DAG.getSrcValue(I.getOperand(0)));
4880 DAG.setRoot(V.getValue(1));
4883 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4884 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4885 getValue(I.getOperand(1)),
4886 DAG.getSrcValue(I.getOperand(1))));
4889 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4890 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4891 getValue(I.getOperand(1)),
4892 getValue(I.getOperand(2)),
4893 DAG.getSrcValue(I.getOperand(1)),
4894 DAG.getSrcValue(I.getOperand(2))));
4897 /// TargetLowering::LowerArguments - This is the default LowerArguments
4898 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4899 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4900 /// integrated into SDISel.
4901 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
4902 SmallVectorImpl<SDValue> &ArgValues) {
4903 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4904 SmallVector<SDValue, 3+16> Ops;
4905 Ops.push_back(DAG.getRoot());
4906 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4907 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4909 // Add one result value for each formal argument.
4910 SmallVector<MVT, 16> RetVals;
4912 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4914 SmallVector<MVT, 4> ValueVTs;
4915 ComputeValueVTs(*this, I->getType(), ValueVTs);
4916 for (unsigned Value = 0, NumValues = ValueVTs.size();
4917 Value != NumValues; ++Value) {
4918 MVT VT = ValueVTs[Value];
4919 const Type *ArgTy = VT.getTypeForMVT();
4920 ISD::ArgFlagsTy Flags;
4921 unsigned OriginalAlignment =
4922 getTargetData()->getABITypeAlignment(ArgTy);
4924 if (F.paramHasAttr(j, ParamAttr::ZExt))
4926 if (F.paramHasAttr(j, ParamAttr::SExt))
4928 if (F.paramHasAttr(j, ParamAttr::InReg))
4930 if (F.paramHasAttr(j, ParamAttr::StructRet))
4932 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4934 const PointerType *Ty = cast<PointerType>(I->getType());
4935 const Type *ElementTy = Ty->getElementType();
4936 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4937 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4938 // For ByVal, alignment should be passed from FE. BE will guess if
4939 // this info is not there but there are cases it cannot get right.
4940 if (F.getParamAlignment(j))
4941 FrameAlign = F.getParamAlignment(j);
4942 Flags.setByValAlign(FrameAlign);
4943 Flags.setByValSize(FrameSize);
4945 if (F.paramHasAttr(j, ParamAttr::Nest))
4947 Flags.setOrigAlign(OriginalAlignment);
4949 MVT RegisterVT = getRegisterType(VT);
4950 unsigned NumRegs = getNumRegisters(VT);
4951 for (unsigned i = 0; i != NumRegs; ++i) {
4952 RetVals.push_back(RegisterVT);
4953 ISD::ArgFlagsTy MyFlags = Flags;
4954 if (NumRegs > 1 && i == 0)
4956 // if it isn't first piece, alignment must be 1
4958 MyFlags.setOrigAlign(1);
4959 Ops.push_back(DAG.getArgFlags(MyFlags));
4964 RetVals.push_back(MVT::Other);
4967 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4968 DAG.getVTList(&RetVals[0], RetVals.size()),
4969 &Ops[0], Ops.size()).Val;
4971 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4972 // allows exposing the loads that may be part of the argument access to the
4973 // first DAGCombiner pass.
4974 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
4976 // The number of results should match up, except that the lowered one may have
4977 // an extra flag result.
4978 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4979 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4980 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4981 && "Lowering produced unexpected number of results!");
4983 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
4984 if (Result != TmpRes.Val && Result->use_empty()) {
4985 HandleSDNode Dummy(DAG.getRoot());
4986 DAG.RemoveDeadNode(Result);
4989 Result = TmpRes.Val;
4991 unsigned NumArgRegs = Result->getNumValues() - 1;
4992 DAG.setRoot(SDValue(Result, NumArgRegs));
4994 // Set up the return result vector.
4997 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4999 SmallVector<MVT, 4> ValueVTs;
5000 ComputeValueVTs(*this, I->getType(), ValueVTs);
5001 for (unsigned Value = 0, NumValues = ValueVTs.size();
5002 Value != NumValues; ++Value) {
5003 MVT VT = ValueVTs[Value];
5004 MVT PartVT = getRegisterType(VT);
5006 unsigned NumParts = getNumRegisters(VT);
5007 SmallVector<SDValue, 4> Parts(NumParts);
5008 for (unsigned j = 0; j != NumParts; ++j)
5009 Parts[j] = SDValue(Result, i++);
5011 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5012 if (F.paramHasAttr(Idx, ParamAttr::SExt))
5013 AssertOp = ISD::AssertSext;
5014 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
5015 AssertOp = ISD::AssertZext;
5017 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
5021 assert(i == NumArgRegs && "Argument register count mismatch!");
5025 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5026 /// implementation, which just inserts an ISD::CALL node, which is later custom
5027 /// lowered by the target to something concrete. FIXME: When all targets are
5028 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5029 std::pair<SDValue, SDValue>
5030 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5031 bool RetSExt, bool RetZExt, bool isVarArg,
5032 unsigned CallingConv, bool isTailCall,
5034 ArgListTy &Args, SelectionDAG &DAG) {
5035 SmallVector<SDValue, 32> Ops;
5036 Ops.push_back(Chain); // Op#0 - Chain
5037 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
5038 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
5039 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
5040 Ops.push_back(Callee);
5042 // Handle all of the outgoing arguments.
5043 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5044 SmallVector<MVT, 4> ValueVTs;
5045 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5046 for (unsigned Value = 0, NumValues = ValueVTs.size();
5047 Value != NumValues; ++Value) {
5048 MVT VT = ValueVTs[Value];
5049 const Type *ArgTy = VT.getTypeForMVT();
5050 SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.getResNo() + Value);
5051 ISD::ArgFlagsTy Flags;
5052 unsigned OriginalAlignment =
5053 getTargetData()->getABITypeAlignment(ArgTy);
5059 if (Args[i].isInReg)
5063 if (Args[i].isByVal) {
5065 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5066 const Type *ElementTy = Ty->getElementType();
5067 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5068 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
5069 // For ByVal, alignment should come from FE. BE will guess if this
5070 // info is not there but there are cases it cannot get right.
5071 if (Args[i].Alignment)
5072 FrameAlign = Args[i].Alignment;
5073 Flags.setByValAlign(FrameAlign);
5074 Flags.setByValSize(FrameSize);
5078 Flags.setOrigAlign(OriginalAlignment);
5080 MVT PartVT = getRegisterType(VT);
5081 unsigned NumParts = getNumRegisters(VT);
5082 SmallVector<SDValue, 4> Parts(NumParts);
5083 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5086 ExtendKind = ISD::SIGN_EXTEND;
5087 else if (Args[i].isZExt)
5088 ExtendKind = ISD::ZERO_EXTEND;
5090 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5092 for (unsigned i = 0; i != NumParts; ++i) {
5093 // if it isn't first piece, alignment must be 1
5094 ISD::ArgFlagsTy MyFlags = Flags;
5095 if (NumParts > 1 && i == 0)
5098 MyFlags.setOrigAlign(1);
5100 Ops.push_back(Parts[i]);
5101 Ops.push_back(DAG.getArgFlags(MyFlags));
5106 // Figure out the result value types. We start by making a list of
5107 // the potentially illegal return value types.
5108 SmallVector<MVT, 4> LoweredRetTys;
5109 SmallVector<MVT, 4> RetTys;
5110 ComputeValueVTs(*this, RetTy, RetTys);
5112 // Then we translate that to a list of legal types.
5113 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5115 MVT RegisterVT = getRegisterType(VT);
5116 unsigned NumRegs = getNumRegisters(VT);
5117 for (unsigned i = 0; i != NumRegs; ++i)
5118 LoweredRetTys.push_back(RegisterVT);
5121 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5123 // Create the CALL node.
5124 SDValue Res = DAG.getNode(ISD::CALL,
5125 DAG.getVTList(&LoweredRetTys[0],
5126 LoweredRetTys.size()),
5127 &Ops[0], Ops.size());
5128 Chain = Res.getValue(LoweredRetTys.size() - 1);
5130 // Gather up the call result into a single value.
5131 if (RetTy != Type::VoidTy) {
5132 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5135 AssertOp = ISD::AssertSext;
5137 AssertOp = ISD::AssertZext;
5139 SmallVector<SDValue, 4> ReturnValues;
5141 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5143 MVT RegisterVT = getRegisterType(VT);
5144 unsigned NumRegs = getNumRegisters(VT);
5145 unsigned RegNoEnd = NumRegs + RegNo;
5146 SmallVector<SDValue, 4> Results;
5147 for (; RegNo != RegNoEnd; ++RegNo)
5148 Results.push_back(Res.getValue(RegNo));
5149 SDValue ReturnValue =
5150 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
5152 ReturnValues.push_back(ReturnValue);
5154 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()),
5155 &ReturnValues[0], ReturnValues.size());
5158 return std::make_pair(Res, Chain);
5161 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5162 assert(0 && "LowerOperation not implemented for this target!");
5168 //===----------------------------------------------------------------------===//
5169 // SelectionDAGISel code
5170 //===----------------------------------------------------------------------===//
5172 SelectionDAGISel::SelectionDAGISel(TargetLowering &tli, bool fast) :
5173 FunctionPass((intptr_t)&ID), TLI(tli),
5174 FuncInfo(new FunctionLoweringInfo(TLI)),
5175 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
5176 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo)),
5182 SelectionDAGISel::~SelectionDAGISel() {
5188 unsigned SelectionDAGISel::MakeReg(MVT VT) {
5189 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
5192 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
5193 AU.addRequired<AliasAnalysis>();
5194 AU.addRequired<GCModuleInfo>();
5195 AU.setPreservesAll();
5198 bool SelectionDAGISel::runOnFunction(Function &Fn) {
5199 // Get alias analysis for load/store combining.
5200 AA = &getAnalysis<AliasAnalysis>();
5202 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
5203 if (MF.getFunction()->hasGC())
5204 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction());
5207 RegInfo = &MF.getRegInfo();
5208 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
5210 FuncInfo->set(Fn, MF);
5211 CurDAG->init(MF, getAnalysisToUpdate<MachineModuleInfo>());
5212 SDL->init(GFI, *AA);
5214 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
5215 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
5216 // Mark landing pad.
5217 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
5219 SelectAllBasicBlocks(Fn, MF);
5221 // Add function live-ins to entry block live-in set.
5222 BasicBlock *EntryBB = &Fn.getEntryBlock();
5223 BB = FuncInfo->MBBMap[EntryBB];
5224 if (!RegInfo->livein_empty())
5225 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
5226 E = RegInfo->livein_end(); I != E; ++I)
5227 BB->addLiveIn(I->first);
5230 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
5231 "Not all catch info was assigned to a landing pad!");
5239 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5240 SDValue Op = getValue(V);
5241 assert((Op.getOpcode() != ISD::CopyFromReg ||
5242 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5243 "Copy from a reg to the same reg!");
5244 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5246 RegsForValue RFV(TLI, Reg, V->getType());
5247 SDValue Chain = DAG.getEntryNode();
5248 RFV.getCopyToRegs(Op, DAG, Chain, 0);
5249 PendingExports.push_back(Chain);
5252 void SelectionDAGISel::
5253 LowerArguments(BasicBlock *LLVMBB) {
5254 // If this is the entry block, emit arguments.
5255 Function &F = *LLVMBB->getParent();
5256 SDValue OldRoot = SDL->DAG.getRoot();
5257 SmallVector<SDValue, 16> Args;
5258 TLI.LowerArguments(F, SDL->DAG, Args);
5261 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5263 SmallVector<MVT, 4> ValueVTs;
5264 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5265 unsigned NumValues = ValueVTs.size();
5266 if (!AI->use_empty()) {
5267 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues));
5268 // If this argument is live outside of the entry block, insert a copy from
5269 // whereever we got it to the vreg that other BB's will reference it as.
5270 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
5271 if (VMI != FuncInfo->ValueMap.end()) {
5272 SDL->CopyValueToVirtualRegister(AI, VMI->second);
5278 // Finally, if the target has anything special to do, allow it to do so.
5279 // FIXME: this should insert code into the DAG!
5280 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5283 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
5284 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
5285 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
5286 if (isSelector(I)) {
5287 // Apply the catch info to DestBB.
5288 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
5290 if (!FLI.MBBMap[SrcBB]->isLandingPad())
5291 FLI.CatchInfoFound.insert(I);
5296 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
5297 /// whether object offset >= 0.
5299 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
5300 if (!isa<FrameIndexSDNode>(Op)) return false;
5302 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
5303 int FrameIdx = FrameIdxNode->getIndex();
5304 return MFI->isFixedObjectIndex(FrameIdx) &&
5305 MFI->getObjectOffset(FrameIdx) >= 0;
5308 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
5309 /// possibly be overwritten when lowering the outgoing arguments in a tail
5310 /// call. Currently the implementation of this call is very conservative and
5311 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
5312 /// virtual registers would be overwritten by direct lowering.
5313 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
5314 MachineFrameInfo * MFI) {
5315 RegisterSDNode * OpReg = NULL;
5316 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
5317 (Op.getOpcode()== ISD::CopyFromReg &&
5318 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
5319 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
5320 (Op.getOpcode() == ISD::LOAD &&
5321 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
5322 (Op.getOpcode() == ISD::MERGE_VALUES &&
5323 Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD &&
5324 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()).
5330 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
5331 /// DAG and fixes their tailcall attribute operand.
5332 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
5333 TargetLowering& TLI) {
5334 SDNode * Ret = NULL;
5335 SDValue Terminator = DAG.getRoot();
5338 if (Terminator.getOpcode() == ISD::RET) {
5339 Ret = Terminator.Val;
5342 // Fix tail call attribute of CALL nodes.
5343 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
5344 BI = DAG.allnodes_end(); BI != BE; ) {
5346 if (BI->getOpcode() == ISD::CALL) {
5347 SDValue OpRet(Ret, 0);
5348 SDValue OpCall(BI, 0);
5349 bool isMarkedTailCall =
5350 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
5351 // If CALL node has tail call attribute set to true and the call is not
5352 // eligible (no RET or the target rejects) the attribute is fixed to
5353 // false. The TargetLowering::IsEligibleForTailCallOptimization function
5354 // must correctly identify tail call optimizable calls.
5355 if (!isMarkedTailCall) continue;
5357 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
5358 // Not eligible. Mark CALL node as non tail call.
5359 SmallVector<SDValue, 32> Ops;
5361 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
5362 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5366 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
5368 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5370 // Look for tail call clobbered arguments. Emit a series of
5371 // copyto/copyfrom virtual register nodes to protect them.
5372 SmallVector<SDValue, 32> Ops;
5373 SDValue Chain = OpCall.getOperand(0), InFlag;
5375 for(SDNode::op_iterator I = OpCall.Val->op_begin(),
5376 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5378 if (idx > 4 && (idx % 2)) {
5379 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
5380 getArgFlags().isByVal();
5381 MachineFunction &MF = DAG.getMachineFunction();
5382 MachineFrameInfo *MFI = MF.getFrameInfo();
5384 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
5385 MVT VT = Arg.getValueType();
5386 unsigned VReg = MF.getRegInfo().
5387 createVirtualRegister(TLI.getRegClassFor(VT));
5388 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
5389 InFlag = Chain.getValue(1);
5390 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
5391 Chain = Arg.getValue(1);
5392 InFlag = Arg.getValue(2);
5397 // Link in chain of CopyTo/CopyFromReg.
5399 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5405 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5406 /// ensure constants are generated when needed. Remember the virtual registers
5407 /// that need to be added to the Machine PHI nodes as input. We cannot just
5408 /// directly add them, because expansion might result in multiple MBB's for one
5409 /// BB. As such, the start of the BB might correspond to a different MBB than
5413 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5414 TerminatorInst *TI = LLVMBB->getTerminator();
5416 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5418 // Check successor nodes' PHI nodes that expect a constant to be available
5420 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5421 BasicBlock *SuccBB = TI->getSuccessor(succ);
5422 if (!isa<PHINode>(SuccBB->begin())) continue;
5423 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5425 // If this terminator has multiple identical successors (common for
5426 // switches), only handle each succ once.
5427 if (!SuccsHandled.insert(SuccMBB)) continue;
5429 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5432 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5433 // nodes and Machine PHI nodes, but the incoming operands have not been
5435 for (BasicBlock::iterator I = SuccBB->begin();
5436 (PN = dyn_cast<PHINode>(I)); ++I) {
5437 // Ignore dead phi's.
5438 if (PN->use_empty()) continue;
5441 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5443 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5444 unsigned &RegOut = SDL->ConstantsOut[C];
5446 RegOut = FuncInfo->CreateRegForValue(C);
5447 SDL->CopyValueToVirtualRegister(C, RegOut);
5451 Reg = FuncInfo->ValueMap[PHIOp];
5453 assert(isa<AllocaInst>(PHIOp) &&
5454 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5455 "Didn't codegen value into a register!??");
5456 Reg = FuncInfo->CreateRegForValue(PHIOp);
5457 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5461 // Remember that this register needs to added to the machine PHI node as
5462 // the input for this MBB.
5463 SmallVector<MVT, 4> ValueVTs;
5464 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5465 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5466 MVT VT = ValueVTs[vti];
5467 unsigned NumRegisters = TLI.getNumRegisters(VT);
5468 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5469 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5470 Reg += NumRegisters;
5474 SDL->ConstantsOut.clear();
5476 // Lower the terminator after the copies are emitted.
5477 SDL->visit(*LLVMBB->getTerminator());
5480 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
5481 BasicBlock::iterator Begin,
5482 BasicBlock::iterator End,
5484 // Lower any arguments needed in this block if this is the entry block.
5486 LowerArguments(LLVMBB);
5488 SDL->setCurrentBasicBlock(BB);
5490 MachineModuleInfo *MMI = CurDAG->getMachineModuleInfo();
5492 if (MMI && BB->isLandingPad()) {
5493 // Add a label to mark the beginning of the landing pad. Deletion of the
5494 // landing pad can thus be detected via the MachineModuleInfo.
5495 unsigned LabelID = MMI->addLandingPad(BB);
5496 CurDAG->setRoot(CurDAG->getLabel(ISD::EH_LABEL,
5497 CurDAG->getEntryNode(), LabelID));
5499 // Mark exception register as live in.
5500 unsigned Reg = TLI.getExceptionAddressRegister();
5501 if (Reg) BB->addLiveIn(Reg);
5503 // Mark exception selector register as live in.
5504 Reg = TLI.getExceptionSelectorRegister();
5505 if (Reg) BB->addLiveIn(Reg);
5507 // FIXME: Hack around an exception handling flaw (PR1508): the personality
5508 // function and list of typeids logically belong to the invoke (or, if you
5509 // like, the basic block containing the invoke), and need to be associated
5510 // with it in the dwarf exception handling tables. Currently however the
5511 // information is provided by an intrinsic (eh.selector) that can be moved
5512 // to unexpected places by the optimizers: if the unwind edge is critical,
5513 // then breaking it can result in the intrinsics being in the successor of
5514 // the landing pad, not the landing pad itself. This results in exceptions
5515 // not being caught because no typeids are associated with the invoke.
5516 // This may not be the only way things can go wrong, but it is the only way
5517 // we try to work around for the moment.
5518 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
5520 if (Br && Br->isUnconditional()) { // Critical edge?
5521 BasicBlock::iterator I, E;
5522 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
5527 // No catch info found - try to extract some from the successor.
5528 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
5532 // Lower all of the non-terminator instructions.
5533 for (BasicBlock::iterator I = Begin; I != End; ++I)
5534 if (!isa<TerminatorInst>(I))
5537 // Ensure that all instructions which are used outside of their defining
5538 // blocks are available as virtual registers. Invoke is handled elsewhere.
5539 for (BasicBlock::iterator I = Begin; I != End; ++I)
5540 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
5541 DenseMap<const Value*,unsigned>::iterator VMI =FuncInfo->ValueMap.find(I);
5542 if (VMI != FuncInfo->ValueMap.end())
5543 SDL->CopyValueToVirtualRegister(I, VMI->second);
5546 // Handle PHI nodes in successor blocks.
5547 if (Begin != End && End == LLVMBB->end())
5548 HandlePHINodesInSuccessorBlocks(LLVMBB);
5550 // Make sure the root of the DAG is up-to-date.
5551 CurDAG->setRoot(SDL->getControlRoot());
5553 // Check whether calls in this block are real tail calls. Fix up CALL nodes
5554 // with correct tailcall attribute so that the target can rely on the tailcall
5555 // attribute indicating whether the call is really eligible for tail call
5557 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI);
5559 // Final step, emit the lowered DAG as machine code.
5560 CodeGenAndEmitDAG();
5564 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
5565 SmallPtrSet<SDNode*, 128> VisitedNodes;
5566 SmallVector<SDNode*, 128> Worklist;
5568 Worklist.push_back(CurDAG->getRoot().Val);
5574 while (!Worklist.empty()) {
5575 SDNode *N = Worklist.back();
5576 Worklist.pop_back();
5578 // If we've already seen this node, ignore it.
5579 if (!VisitedNodes.insert(N))
5582 // Otherwise, add all chain operands to the worklist.
5583 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5584 if (N->getOperand(i).getValueType() == MVT::Other)
5585 Worklist.push_back(N->getOperand(i).Val);
5587 // If this is a CopyToReg with a vreg dest, process it.
5588 if (N->getOpcode() != ISD::CopyToReg)
5591 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
5592 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
5595 // Ignore non-scalar or non-integer values.
5596 SDValue Src = N->getOperand(2);
5597 MVT SrcVT = Src.getValueType();
5598 if (!SrcVT.isInteger() || SrcVT.isVector())
5601 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
5602 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
5603 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
5605 // Only install this information if it tells us something.
5606 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
5607 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
5608 FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo();
5609 if (DestReg >= FLI.LiveOutRegInfo.size())
5610 FLI.LiveOutRegInfo.resize(DestReg+1);
5611 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
5612 LOI.NumSignBits = NumSignBits;
5613 LOI.KnownOne = NumSignBits;
5614 LOI.KnownZero = NumSignBits;
5619 void SelectionDAGISel::CodeGenAndEmitDAG() {
5620 std::string GroupName;
5621 if (TimePassesIsEnabled)
5622 GroupName = "Instruction Selection and Scheduling";
5623 std::string BlockName;
5624 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
5625 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
5626 BlockName = CurDAG->getMachineFunction().getFunction()->getName() + ':' +
5627 BB->getBasicBlock()->getName();
5629 DOUT << "Initial selection DAG:\n";
5630 DEBUG(CurDAG->dump());
5632 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
5634 // Run the DAG combiner in pre-legalize mode.
5635 if (TimePassesIsEnabled) {
5636 NamedRegionTimer T("DAG Combining 1", GroupName);
5637 CurDAG->Combine(false, *AA, Fast);
5639 CurDAG->Combine(false, *AA, Fast);
5642 DOUT << "Optimized lowered selection DAG:\n";
5643 DEBUG(CurDAG->dump());
5645 // Second step, hack on the DAG until it only uses operations and types that
5646 // the target supports.
5647 if (EnableLegalizeTypes) {// Enable this some day.
5648 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
5651 if (TimePassesIsEnabled) {
5652 NamedRegionTimer T("Type Legalization", GroupName);
5653 CurDAG->LegalizeTypes();
5655 CurDAG->LegalizeTypes();
5658 DOUT << "Type-legalized selection DAG:\n";
5659 DEBUG(CurDAG->dump());
5661 // TODO: enable a dag combine pass here.
5664 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
5666 if (TimePassesIsEnabled) {
5667 NamedRegionTimer T("DAG Legalization", GroupName);
5673 DOUT << "Legalized selection DAG:\n";
5674 DEBUG(CurDAG->dump());
5676 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
5678 // Run the DAG combiner in post-legalize mode.
5679 if (TimePassesIsEnabled) {
5680 NamedRegionTimer T("DAG Combining 2", GroupName);
5681 CurDAG->Combine(true, *AA, Fast);
5683 CurDAG->Combine(true, *AA, Fast);
5686 DOUT << "Optimized legalized selection DAG:\n";
5687 DEBUG(CurDAG->dump());
5689 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
5691 if (!Fast && EnableValueProp)
5692 ComputeLiveOutVRegInfo();
5694 // Third, instruction select all of the operations to machine code, adding the
5695 // code to the MachineBasicBlock.
5696 if (TimePassesIsEnabled) {
5697 NamedRegionTimer T("Instruction Selection", GroupName);
5698 InstructionSelect();
5700 InstructionSelect();
5703 DOUT << "Selected selection DAG:\n";
5704 DEBUG(CurDAG->dump());
5706 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
5708 // Schedule machine code.
5709 ScheduleDAG *Scheduler;
5710 if (TimePassesIsEnabled) {
5711 NamedRegionTimer T("Instruction Scheduling", GroupName);
5712 Scheduler = Schedule();
5714 Scheduler = Schedule();
5717 if (ViewSUnitDAGs) Scheduler->viewGraph();
5719 // Emit machine code to BB. This can change 'BB' to the last block being
5721 if (TimePassesIsEnabled) {
5722 NamedRegionTimer T("Instruction Creation", GroupName);
5723 BB = Scheduler->EmitSchedule();
5725 BB = Scheduler->EmitSchedule();
5728 // Free the scheduler state.
5729 if (TimePassesIsEnabled) {
5730 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
5736 DOUT << "Selected machine code:\n";
5740 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF) {
5741 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
5742 BasicBlock *LLVMBB = &*I;
5743 BB = FuncInfo->MBBMap[LLVMBB];
5745 BasicBlock::iterator Begin = LLVMBB->begin();
5746 BasicBlock::iterator End = LLVMBB->end();
5747 bool DoArgs = LLVMBB == &Fn.getEntryBlock();
5749 // Before doing SelectionDAG ISel, see if FastISel has been requested.
5750 // FastISel doesn't support EH landing pads, which require special handling.
5751 if (EnableFastISel && !BB->isLandingPad()) {
5752 if (FastISel *F = TLI.createFastISel(*FuncInfo->MF)) {
5753 while (Begin != End) {
5754 Begin = F->SelectInstructions(Begin, End, FuncInfo->ValueMap,
5755 FuncInfo->MBBMap, BB);
5758 // The "fast" selector selected the entire block, so we're done.
5761 // Handle certain instructions as single-LLVM-Instruction blocks.
5762 if (isa<CallInst>(Begin) || isa<LoadInst>(Begin) ||
5763 isa<StoreInst>(Begin)) {
5764 if (Begin->getType() != Type::VoidTy) {
5765 unsigned &R = FuncInfo->ValueMap[Begin];
5767 R = FuncInfo->CreateRegForValue(Begin);
5770 SelectBasicBlock(LLVMBB, Begin, next(Begin), DoArgs);
5777 if (!DisableFastISelAbort &&
5778 // For now, don't abort on non-conditional-branch terminators.
5779 (!isa<TerminatorInst>(Begin) ||
5780 (isa<BranchInst>(Begin) &&
5781 cast<BranchInst>(Begin)->isUnconditional()))) {
5782 // The "fast" selector couldn't handle something and bailed.
5783 // For the purpose of debugging, just abort.
5787 assert(0 && "FastISel didn't select the entire block");
5795 if (Begin != End || DoArgs)
5796 SelectBasicBlock(LLVMBB, Begin, End, DoArgs);
5803 SelectionDAGISel::FinishBasicBlock() {
5805 // Perform target specific isel post processing.
5806 InstructionSelectPostProcessing();
5808 DOUT << "Target-post-processed machine code:\n";
5811 DOUT << "Total amount of phi nodes to update: "
5812 << SDL->PHINodesToUpdate.size() << "\n";
5813 DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i)
5814 DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first
5815 << ", " << SDL->PHINodesToUpdate[i].second << ")\n";);
5817 // Next, now that we know what the last MBB the LLVM BB expanded is, update
5818 // PHI nodes in successors.
5819 if (SDL->SwitchCases.empty() &&
5820 SDL->JTCases.empty() &&
5821 SDL->BitTestCases.empty()) {
5822 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
5823 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
5824 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5825 "This is not a machine PHI node that we are updating!");
5826 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
5828 PHI->addOperand(MachineOperand::CreateMBB(BB));
5830 SDL->PHINodesToUpdate.clear();
5834 for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) {
5835 // Lower header first, if it wasn't already lowered
5836 if (!SDL->BitTestCases[i].Emitted) {
5837 // Set the current basic block to the mbb we wish to insert the code into
5838 BB = SDL->BitTestCases[i].Parent;
5839 SDL->setCurrentBasicBlock(BB);
5841 SDL->visitBitTestHeader(SDL->BitTestCases[i]);
5842 CurDAG->setRoot(SDL->getRoot());
5843 CodeGenAndEmitDAG();
5847 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) {
5848 // Set the current basic block to the mbb we wish to insert the code into
5849 BB = SDL->BitTestCases[i].Cases[j].ThisBB;
5850 SDL->setCurrentBasicBlock(BB);
5853 SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB,
5854 SDL->BitTestCases[i].Reg,
5855 SDL->BitTestCases[i].Cases[j]);
5857 SDL->visitBitTestCase(SDL->BitTestCases[i].Default,
5858 SDL->BitTestCases[i].Reg,
5859 SDL->BitTestCases[i].Cases[j]);
5862 CurDAG->setRoot(SDL->getRoot());
5863 CodeGenAndEmitDAG();
5868 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
5869 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
5870 MachineBasicBlock *PHIBB = PHI->getParent();
5871 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5872 "This is not a machine PHI node that we are updating!");
5873 // This is "default" BB. We have two jumps to it. From "header" BB and
5874 // from last "case" BB.
5875 if (PHIBB == SDL->BitTestCases[i].Default) {
5876 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
5878 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent));
5879 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
5881 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases.
5884 // One of "cases" BB.
5885 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size();
5887 MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB;
5888 if (cBB->succ_end() !=
5889 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5890 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
5892 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5897 SDL->BitTestCases.clear();
5899 // If the JumpTable record is filled in, then we need to emit a jump table.
5900 // Updating the PHI nodes is tricky in this case, since we need to determine
5901 // whether the PHI is a successor of the range check MBB or the jump table MBB
5902 for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) {
5903 // Lower header first, if it wasn't already lowered
5904 if (!SDL->JTCases[i].first.Emitted) {
5905 // Set the current basic block to the mbb we wish to insert the code into
5906 BB = SDL->JTCases[i].first.HeaderBB;
5907 SDL->setCurrentBasicBlock(BB);
5909 SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first);
5910 CurDAG->setRoot(SDL->getRoot());
5911 CodeGenAndEmitDAG();
5915 // Set the current basic block to the mbb we wish to insert the code into
5916 BB = SDL->JTCases[i].second.MBB;
5917 SDL->setCurrentBasicBlock(BB);
5919 SDL->visitJumpTable(SDL->JTCases[i].second);
5920 CurDAG->setRoot(SDL->getRoot());
5921 CodeGenAndEmitDAG();
5925 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
5926 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
5927 MachineBasicBlock *PHIBB = PHI->getParent();
5928 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5929 "This is not a machine PHI node that we are updating!");
5930 // "default" BB. We can go there only from header BB.
5931 if (PHIBB == SDL->JTCases[i].second.Default) {
5932 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
5934 PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB));
5936 // JT BB. Just iterate over successors here
5937 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5938 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
5940 PHI->addOperand(MachineOperand::CreateMBB(BB));
5944 SDL->JTCases.clear();
5946 // If the switch block involved a branch to one of the actual successors, we
5947 // need to update PHI nodes in that block.
5948 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
5949 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
5950 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5951 "This is not a machine PHI node that we are updating!");
5952 if (BB->isSuccessor(PHI->getParent())) {
5953 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
5955 PHI->addOperand(MachineOperand::CreateMBB(BB));
5959 // If we generated any switch lowering information, build and codegen any
5960 // additional DAGs necessary.
5961 for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) {
5962 // Set the current basic block to the mbb we wish to insert the code into
5963 BB = SDL->SwitchCases[i].ThisBB;
5964 SDL->setCurrentBasicBlock(BB);
5967 SDL->visitSwitchCase(SDL->SwitchCases[i]);
5968 CurDAG->setRoot(SDL->getRoot());
5969 CodeGenAndEmitDAG();
5972 // Handle any PHI nodes in successors of this chunk, as if we were coming
5973 // from the original BB before switch expansion. Note that PHI nodes can
5974 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5975 // handle them the right number of times.
5976 while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5977 for (MachineBasicBlock::iterator Phi = BB->begin();
5978 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5979 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5980 for (unsigned pn = 0; ; ++pn) {
5981 assert(pn != SDL->PHINodesToUpdate.size() &&
5982 "Didn't find PHI entry!");
5983 if (SDL->PHINodesToUpdate[pn].first == Phi) {
5984 Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn].
5986 Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB));
5992 // Don't process RHS if same block as LHS.
5993 if (BB == SDL->SwitchCases[i].FalseBB)
5994 SDL->SwitchCases[i].FalseBB = 0;
5996 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5997 SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB;
5998 SDL->SwitchCases[i].FalseBB = 0;
6000 assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0);
6002 SDL->SwitchCases.clear();
6004 SDL->PHINodesToUpdate.clear();
6008 /// Schedule - Pick a safe ordering for instructions for each
6009 /// target node in the graph.
6011 ScheduleDAG *SelectionDAGISel::Schedule() {
6012 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
6016 RegisterScheduler::setDefault(Ctor);
6019 ScheduleDAG *Scheduler = Ctor(this, CurDAG, BB, Fast);
6026 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
6027 return new HazardRecognizer();
6030 //===----------------------------------------------------------------------===//
6031 // Helper functions used by the generated instruction selector.
6032 //===----------------------------------------------------------------------===//
6033 // Calls to these methods are generated by tblgen.
6035 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
6036 /// the dag combiner simplified the 255, we still want to match. RHS is the
6037 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
6038 /// specified in the .td file (e.g. 255).
6039 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
6040 int64_t DesiredMaskS) const {
6041 const APInt &ActualMask = RHS->getAPIntValue();
6042 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
6044 // If the actual mask exactly matches, success!
6045 if (ActualMask == DesiredMask)
6048 // If the actual AND mask is allowing unallowed bits, this doesn't match.
6049 if (ActualMask.intersects(~DesiredMask))
6052 // Otherwise, the DAG Combiner may have proven that the value coming in is
6053 // either already zero or is not demanded. Check for known zero input bits.
6054 APInt NeededMask = DesiredMask & ~ActualMask;
6055 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
6058 // TODO: check to see if missing bits are just not demanded.
6060 // Otherwise, this pattern doesn't match.
6064 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
6065 /// the dag combiner simplified the 255, we still want to match. RHS is the
6066 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
6067 /// specified in the .td file (e.g. 255).
6068 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
6069 int64_t DesiredMaskS) const {
6070 const APInt &ActualMask = RHS->getAPIntValue();
6071 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
6073 // If the actual mask exactly matches, success!
6074 if (ActualMask == DesiredMask)
6077 // If the actual AND mask is allowing unallowed bits, this doesn't match.
6078 if (ActualMask.intersects(~DesiredMask))
6081 // Otherwise, the DAG Combiner may have proven that the value coming in is
6082 // either already zero or is not demanded. Check for known zero input bits.
6083 APInt NeededMask = DesiredMask & ~ActualMask;
6085 APInt KnownZero, KnownOne;
6086 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
6088 // If all the missing bits in the or are already known to be set, match!
6089 if ((NeededMask & KnownOne) == NeededMask)
6092 // TODO: check to see if missing bits are just not demanded.
6094 // Otherwise, this pattern doesn't match.
6099 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
6100 /// by tblgen. Others should not call it.
6101 void SelectionDAGISel::
6102 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
6103 std::vector<SDValue> InOps;
6104 std::swap(InOps, Ops);
6106 Ops.push_back(InOps[0]); // input chain.
6107 Ops.push_back(InOps[1]); // input asm string.
6109 unsigned i = 2, e = InOps.size();
6110 if (InOps[e-1].getValueType() == MVT::Flag)
6111 --e; // Don't process a flag operand if it is here.
6114 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
6115 if ((Flags & 7) != 4 /*MEM*/) {
6116 // Just skip over this operand, copying the operands verbatim.
6117 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
6118 i += (Flags >> 3) + 1;
6120 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
6121 // Otherwise, this is a memory operand. Ask the target to select it.
6122 std::vector<SDValue> SelOps;
6123 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
6124 cerr << "Could not match memory address. Inline asm failure!\n";
6128 // Add this to the output node.
6129 MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy();
6130 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
6132 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
6137 // Add the flag input back if present.
6138 if (e != InOps.size())
6139 Ops.push_back(InOps.back());
6142 char SelectionDAGISel::ID = 0;