1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DebugInfo.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/Function.h"
27 #include "llvm/GlobalVariable.h"
28 #include "llvm/InlineAsm.h"
29 #include "llvm/Instructions.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/IntrinsicInst.h"
32 #include "llvm/LLVMContext.h"
33 #include "llvm/Module.h"
34 #include "llvm/CodeGen/Analysis.h"
35 #include "llvm/CodeGen/FastISel.h"
36 #include "llvm/CodeGen/FunctionLoweringInfo.h"
37 #include "llvm/CodeGen/GCStrategy.h"
38 #include "llvm/CodeGen/GCMetadata.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineFrameInfo.h"
41 #include "llvm/CodeGen/MachineInstrBuilder.h"
42 #include "llvm/CodeGen/MachineJumpTableInfo.h"
43 #include "llvm/CodeGen/MachineModuleInfo.h"
44 #include "llvm/CodeGen/MachineRegisterInfo.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameLowering.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetIntrinsicInfo.h"
50 #include "llvm/Target/TargetLibraryInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/IntegersSubsetMapping.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
62 /// LimitFloatPrecision - Generate low-precision inline sequences for
63 /// some float libcalls (6, 8 or 12 bits).
64 static unsigned LimitFloatPrecision;
66 static cl::opt<unsigned, true>
67 LimitFPPrecision("limit-float-precision",
68 cl::desc("Generate low-precision inline sequences "
69 "for some float libcalls"),
70 cl::location(LimitFloatPrecision),
73 // Limit the width of DAG chains. This is important in general to prevent
74 // prevent DAG-based analysis from blowing up. For example, alias analysis and
75 // load clustering may not complete in reasonable time. It is difficult to
76 // recognize and avoid this situation within each individual analysis, and
77 // future analyses are likely to have the same behavior. Limiting DAG width is
78 // the safe approach, and will be especially important with global DAGs.
80 // MaxParallelChains default is arbitrarily high to avoid affecting
81 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
82 // sequence over this should have been converted to llvm.memcpy by the
83 // frontend. It easy to induce this behavior with .ll code such as:
84 // %buffer = alloca [4096 x i8]
85 // %data = load [4096 x i8]* %argPtr
86 // store [4096 x i8] %data, [4096 x i8]* %buffer
87 static const unsigned MaxParallelChains = 64;
89 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
90 const SDValue *Parts, unsigned NumParts,
91 EVT PartVT, EVT ValueVT);
93 /// getCopyFromParts - Create a value that contains the specified legal parts
94 /// combined into the value they represent. If the parts combine to a type
95 /// larger then ValueVT then AssertOp can be used to specify whether the extra
96 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
97 /// (ISD::AssertSext).
98 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
100 unsigned NumParts, EVT PartVT, EVT ValueVT,
101 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
102 if (ValueVT.isVector())
103 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
105 assert(NumParts > 0 && "No parts to assemble!");
106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
107 SDValue Val = Parts[0];
110 // Assemble the value from multiple parts.
111 if (ValueVT.isInteger()) {
112 unsigned PartBits = PartVT.getSizeInBits();
113 unsigned ValueBits = ValueVT.getSizeInBits();
115 // Assemble the power of 2 part.
116 unsigned RoundParts = NumParts & (NumParts - 1) ?
117 1 << Log2_32(NumParts) : NumParts;
118 unsigned RoundBits = PartBits * RoundParts;
119 EVT RoundVT = RoundBits == ValueBits ?
120 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
123 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
125 if (RoundParts > 2) {
126 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
128 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
129 RoundParts / 2, PartVT, HalfVT);
131 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
132 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
135 if (TLI.isBigEndian())
138 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
140 if (RoundParts < NumParts) {
141 // Assemble the trailing non-power-of-2 part.
142 unsigned OddParts = NumParts - RoundParts;
143 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
144 Hi = getCopyFromParts(DAG, DL,
145 Parts + RoundParts, OddParts, PartVT, OddVT);
147 // Combine the round and odd parts.
149 if (TLI.isBigEndian())
151 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
152 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
153 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
154 DAG.getConstant(Lo.getValueType().getSizeInBits(),
155 TLI.getPointerTy()));
156 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
157 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
159 } else if (PartVT.isFloatingPoint()) {
160 // FP split into multiple FP parts (for ppcf128)
161 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
164 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
165 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
166 if (TLI.isBigEndian())
168 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
170 // FP split into integer parts (soft fp)
171 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
172 !PartVT.isVector() && "Unexpected split");
173 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
174 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
178 // There is now one part, held in Val. Correct it to match ValueVT.
179 PartVT = Val.getValueType();
181 if (PartVT == ValueVT)
184 if (PartVT.isInteger() && ValueVT.isInteger()) {
185 if (ValueVT.bitsLT(PartVT)) {
186 // For a truncate, see if we have any information to
187 // indicate whether the truncated bits will always be
188 // zero or sign-extension.
189 if (AssertOp != ISD::DELETED_NODE)
190 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
191 DAG.getValueType(ValueVT));
192 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
194 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
197 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
198 // FP_ROUND's are always exact here.
199 if (ValueVT.bitsLT(Val.getValueType()))
200 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
201 DAG.getTargetConstant(1, TLI.getPointerTy()));
203 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
206 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
207 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
209 llvm_unreachable("Unknown mismatch!");
212 /// getCopyFromParts - Create a value that contains the specified legal parts
213 /// combined into the value they represent. If the parts combine to a type
214 /// larger then ValueVT then AssertOp can be used to specify whether the extra
215 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
216 /// (ISD::AssertSext).
217 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
218 const SDValue *Parts, unsigned NumParts,
219 EVT PartVT, EVT ValueVT) {
220 assert(ValueVT.isVector() && "Not a vector value");
221 assert(NumParts > 0 && "No parts to assemble!");
222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
223 SDValue Val = Parts[0];
225 // Handle a multi-element vector.
227 EVT IntermediateVT, RegisterVT;
228 unsigned NumIntermediates;
230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
231 NumIntermediates, RegisterVT);
232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
233 NumParts = NumRegs; // Silence a compiler warning.
234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
235 assert(RegisterVT == Parts[0].getValueType() &&
236 "Part type doesn't match part!");
238 // Assemble the parts into intermediate operands.
239 SmallVector<SDValue, 8> Ops(NumIntermediates);
240 if (NumIntermediates == NumParts) {
241 // If the register was not expanded, truncate or copy the value,
243 for (unsigned i = 0; i != NumParts; ++i)
244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
245 PartVT, IntermediateVT);
246 } else if (NumParts > 0) {
247 // If the intermediate type was expanded, build the intermediate
248 // operands from the parts.
249 assert(NumParts % NumIntermediates == 0 &&
250 "Must expand into a divisible number of parts!");
251 unsigned Factor = NumParts / NumIntermediates;
252 for (unsigned i = 0; i != NumIntermediates; ++i)
253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
254 PartVT, IntermediateVT);
257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
258 // intermediate operands.
259 Val = DAG.getNode(IntermediateVT.isVector() ?
260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
261 ValueVT, &Ops[0], NumIntermediates);
264 // There is now one part, held in Val. Correct it to match ValueVT.
265 PartVT = Val.getValueType();
267 if (PartVT == ValueVT)
270 if (PartVT.isVector()) {
271 // If the element type of the source/dest vectors are the same, but the
272 // parts vector has more elements than the value vector, then we have a
273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
277 "Cannot narrow, it would be a lossy transformation");
278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
279 DAG.getIntPtrConstant(0));
282 // Vector/Vector bitcast.
283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits())
284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
287 "Cannot handle this kind of promotion");
288 // Promoted vector extract
289 bool Smaller = ValueVT.bitsLE(PartVT);
290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
295 // Trivial bitcast if the types are the same size and the destination
296 // vector type is legal.
297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() &&
298 TLI.isTypeLegal(ValueVT))
299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
301 // Handle cases such as i8 -> <1 x i1>
302 assert(ValueVT.getVectorNumElements() == 1 &&
303 "Only trivial scalar-to-vector conversions should get here!");
305 if (ValueVT.getVectorNumElements() == 1 &&
306 ValueVT.getVectorElementType() != PartVT) {
307 bool Smaller = ValueVT.bitsLE(PartVT);
308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
309 DL, ValueVT.getScalarType(), Val);
312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
318 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
319 SDValue Val, SDValue *Parts, unsigned NumParts,
322 /// getCopyToParts - Create a series of nodes that contain the specified value
323 /// split into legal parts. If the parts contain more bits than Val, then, for
324 /// integers, ExtendKind can be used to specify how to generate the extra bits.
325 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
326 SDValue Val, SDValue *Parts, unsigned NumParts,
328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
329 EVT ValueVT = Val.getValueType();
331 // Handle the vector case separately.
332 if (ValueVT.isVector())
333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
336 unsigned PartBits = PartVT.getSizeInBits();
337 unsigned OrigNumParts = NumParts;
338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
343 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
344 if (PartVT == ValueVT) {
345 assert(NumParts == 1 && "No-op copy with multiple parts!");
350 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
351 // If the parts cover more bits than the value has, promote the value.
352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
353 assert(NumParts == 1 && "Do not know what to promote to!");
354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
356 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
357 ValueVT.isInteger() &&
358 "Unknown mismatch!");
359 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
360 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
361 if (PartVT == MVT::x86mmx)
362 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
364 } else if (PartBits == ValueVT.getSizeInBits()) {
365 // Different types of the same size.
366 assert(NumParts == 1 && PartVT != ValueVT);
367 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
368 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
369 // If the parts cover less bits than value has, truncate the value.
370 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
371 ValueVT.isInteger() &&
372 "Unknown mismatch!");
373 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
374 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
375 if (PartVT == MVT::x86mmx)
376 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
379 // The value may have changed - recompute ValueVT.
380 ValueVT = Val.getValueType();
381 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
382 "Failed to tile the value with PartVT!");
385 assert(PartVT == ValueVT && "Type conversion failed!");
390 // Expand the value into multiple parts.
391 if (NumParts & (NumParts - 1)) {
392 // The number of parts is not a power of 2. Split off and copy the tail.
393 assert(PartVT.isInteger() && ValueVT.isInteger() &&
394 "Do not know what to expand to!");
395 unsigned RoundParts = 1 << Log2_32(NumParts);
396 unsigned RoundBits = RoundParts * PartBits;
397 unsigned OddParts = NumParts - RoundParts;
398 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
399 DAG.getIntPtrConstant(RoundBits));
400 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
402 if (TLI.isBigEndian())
403 // The odd parts were reversed by getCopyToParts - unreverse them.
404 std::reverse(Parts + RoundParts, Parts + NumParts);
406 NumParts = RoundParts;
407 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
408 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
411 // The number of parts is a power of 2. Repeatedly bisect the value using
413 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
414 EVT::getIntegerVT(*DAG.getContext(),
415 ValueVT.getSizeInBits()),
418 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
419 for (unsigned i = 0; i < NumParts; i += StepSize) {
420 unsigned ThisBits = StepSize * PartBits / 2;
421 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
422 SDValue &Part0 = Parts[i];
423 SDValue &Part1 = Parts[i+StepSize/2];
425 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
426 ThisVT, Part0, DAG.getIntPtrConstant(1));
427 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
428 ThisVT, Part0, DAG.getIntPtrConstant(0));
430 if (ThisBits == PartBits && ThisVT != PartVT) {
431 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
432 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
437 if (TLI.isBigEndian())
438 std::reverse(Parts, Parts + OrigNumParts);
442 /// getCopyToPartsVector - Create a series of nodes that contain the specified
443 /// value split into legal parts.
444 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
445 SDValue Val, SDValue *Parts, unsigned NumParts,
447 EVT ValueVT = Val.getValueType();
448 assert(ValueVT.isVector() && "Not a vector");
449 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
452 if (PartVT == ValueVT) {
454 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
455 // Bitconvert vector->vector case.
456 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
457 } else if (PartVT.isVector() &&
458 PartVT.getVectorElementType() == ValueVT.getVectorElementType() &&
459 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
460 EVT ElementVT = PartVT.getVectorElementType();
461 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
463 SmallVector<SDValue, 16> Ops;
464 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
465 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
466 ElementVT, Val, DAG.getIntPtrConstant(i)));
468 for (unsigned i = ValueVT.getVectorNumElements(),
469 e = PartVT.getVectorNumElements(); i != e; ++i)
470 Ops.push_back(DAG.getUNDEF(ElementVT));
472 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
474 // FIXME: Use CONCAT for 2x -> 4x.
476 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
477 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
478 } else if (PartVT.isVector() &&
479 PartVT.getVectorElementType().bitsGE(
480 ValueVT.getVectorElementType()) &&
481 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
483 // Promoted vector extract
484 bool Smaller = PartVT.bitsLE(ValueVT);
485 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
488 // Vector -> scalar conversion.
489 assert(ValueVT.getVectorNumElements() == 1 &&
490 "Only trivial vector-to-scalar conversions should get here!");
491 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
492 PartVT, Val, DAG.getIntPtrConstant(0));
494 bool Smaller = ValueVT.bitsLE(PartVT);
495 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
503 // Handle a multi-element vector.
504 EVT IntermediateVT, RegisterVT;
505 unsigned NumIntermediates;
506 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
508 NumIntermediates, RegisterVT);
509 unsigned NumElements = ValueVT.getVectorNumElements();
511 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
512 NumParts = NumRegs; // Silence a compiler warning.
513 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
515 // Split the vector into intermediate operands.
516 SmallVector<SDValue, 8> Ops(NumIntermediates);
517 for (unsigned i = 0; i != NumIntermediates; ++i) {
518 if (IntermediateVT.isVector())
519 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
521 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
523 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
524 IntermediateVT, Val, DAG.getIntPtrConstant(i));
527 // Split the intermediate operands into legal parts.
528 if (NumParts == NumIntermediates) {
529 // If the register was not expanded, promote or copy the value,
531 for (unsigned i = 0; i != NumParts; ++i)
532 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
533 } else if (NumParts > 0) {
534 // If the intermediate type was expanded, split each the value into
536 assert(NumParts % NumIntermediates == 0 &&
537 "Must expand into a divisible number of parts!");
538 unsigned Factor = NumParts / NumIntermediates;
539 for (unsigned i = 0; i != NumIntermediates; ++i)
540 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
548 /// RegsForValue - This struct represents the registers (physical or virtual)
549 /// that a particular set of values is assigned, and the type information
550 /// about the value. The most common situation is to represent one value at a
551 /// time, but struct or array values are handled element-wise as multiple
552 /// values. The splitting of aggregates is performed recursively, so that we
553 /// never have aggregate-typed registers. The values at this point do not
554 /// necessarily have legal types, so each value may require one or more
555 /// registers of some legal type.
557 struct RegsForValue {
558 /// ValueVTs - The value types of the values, which may not be legal, and
559 /// may need be promoted or synthesized from one or more registers.
561 SmallVector<EVT, 4> ValueVTs;
563 /// RegVTs - The value types of the registers. This is the same size as
564 /// ValueVTs and it records, for each value, what the type of the assigned
565 /// register or registers are. (Individual values are never synthesized
566 /// from more than one type of register.)
568 /// With virtual registers, the contents of RegVTs is redundant with TLI's
569 /// getRegisterType member function, however when with physical registers
570 /// it is necessary to have a separate record of the types.
572 SmallVector<EVT, 4> RegVTs;
574 /// Regs - This list holds the registers assigned to the values.
575 /// Each legal or promoted value requires one register, and each
576 /// expanded value requires multiple registers.
578 SmallVector<unsigned, 4> Regs;
582 RegsForValue(const SmallVector<unsigned, 4> ®s,
583 EVT regvt, EVT valuevt)
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
587 unsigned Reg, Type *Ty) {
588 ComputeValueVTs(tli, Ty, ValueVTs);
590 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
591 EVT ValueVT = ValueVTs[Value];
592 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
593 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
594 for (unsigned i = 0; i != NumRegs; ++i)
595 Regs.push_back(Reg + i);
596 RegVTs.push_back(RegisterVT);
601 /// areValueTypesLegal - Return true if types of all the values are legal.
602 bool areValueTypesLegal(const TargetLowering &TLI) {
603 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
604 EVT RegisterVT = RegVTs[Value];
605 if (!TLI.isTypeLegal(RegisterVT))
611 /// append - Add the specified values to this one.
612 void append(const RegsForValue &RHS) {
613 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
614 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
615 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
618 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
619 /// this value and returns the result as a ValueVTs value. This uses
620 /// Chain/Flag as the input and updates them for the output Chain/Flag.
621 /// If the Flag pointer is NULL, no flag is used.
622 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
624 SDValue &Chain, SDValue *Flag) const;
626 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
627 /// specified value into the registers specified by this object. This uses
628 /// Chain/Flag as the input and updates them for the output Chain/Flag.
629 /// If the Flag pointer is NULL, no flag is used.
630 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
631 SDValue &Chain, SDValue *Flag) const;
633 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
634 /// operand list. This adds the code marker, matching input operand index
635 /// (if applicable), and includes the number of values added into it.
636 void AddInlineAsmOperands(unsigned Kind,
637 bool HasMatching, unsigned MatchingIdx,
639 std::vector<SDValue> &Ops) const;
643 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
644 /// this value and returns the result as a ValueVT value. This uses
645 /// Chain/Flag as the input and updates them for the output Chain/Flag.
646 /// If the Flag pointer is NULL, no flag is used.
647 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
648 FunctionLoweringInfo &FuncInfo,
650 SDValue &Chain, SDValue *Flag) const {
651 // A Value with type {} or [0 x %t] needs no registers.
652 if (ValueVTs.empty())
655 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
657 // Assemble the legal parts into the final values.
658 SmallVector<SDValue, 4> Values(ValueVTs.size());
659 SmallVector<SDValue, 8> Parts;
660 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
661 // Copy the legal parts from the registers.
662 EVT ValueVT = ValueVTs[Value];
663 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
664 EVT RegisterVT = RegVTs[Value];
666 Parts.resize(NumRegs);
667 for (unsigned i = 0; i != NumRegs; ++i) {
670 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
672 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
673 *Flag = P.getValue(2);
676 Chain = P.getValue(1);
679 // If the source register was virtual and if we know something about it,
680 // add an assert node.
681 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
682 !RegisterVT.isInteger() || RegisterVT.isVector())
685 const FunctionLoweringInfo::LiveOutInfo *LOI =
686 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
690 unsigned RegSize = RegisterVT.getSizeInBits();
691 unsigned NumSignBits = LOI->NumSignBits;
692 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
694 // FIXME: We capture more information than the dag can represent. For
695 // now, just use the tightest assertzext/assertsext possible.
697 EVT FromVT(MVT::Other);
698 if (NumSignBits == RegSize)
699 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
700 else if (NumZeroBits >= RegSize-1)
701 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
702 else if (NumSignBits > RegSize-8)
703 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
704 else if (NumZeroBits >= RegSize-8)
705 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
706 else if (NumSignBits > RegSize-16)
707 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
708 else if (NumZeroBits >= RegSize-16)
709 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
710 else if (NumSignBits > RegSize-32)
711 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
712 else if (NumZeroBits >= RegSize-32)
713 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
717 // Add an assertion node.
718 assert(FromVT != MVT::Other);
719 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
720 RegisterVT, P, DAG.getValueType(FromVT));
723 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
724 NumRegs, RegisterVT, ValueVT);
729 return DAG.getNode(ISD::MERGE_VALUES, dl,
730 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
731 &Values[0], ValueVTs.size());
734 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
735 /// specified value into the registers specified by this object. This uses
736 /// Chain/Flag as the input and updates them for the output Chain/Flag.
737 /// If the Flag pointer is NULL, no flag is used.
738 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
739 SDValue &Chain, SDValue *Flag) const {
740 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
742 // Get the list of the values's legal parts.
743 unsigned NumRegs = Regs.size();
744 SmallVector<SDValue, 8> Parts(NumRegs);
745 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
746 EVT ValueVT = ValueVTs[Value];
747 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
748 EVT RegisterVT = RegVTs[Value];
750 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
751 &Parts[Part], NumParts, RegisterVT);
755 // Copy the parts into the registers.
756 SmallVector<SDValue, 8> Chains(NumRegs);
757 for (unsigned i = 0; i != NumRegs; ++i) {
760 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
762 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
763 *Flag = Part.getValue(1);
766 Chains[i] = Part.getValue(0);
769 if (NumRegs == 1 || Flag)
770 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
771 // flagged to it. That is the CopyToReg nodes and the user are considered
772 // a single scheduling unit. If we create a TokenFactor and return it as
773 // chain, then the TokenFactor is both a predecessor (operand) of the
774 // user as well as a successor (the TF operands are flagged to the user).
775 // c1, f1 = CopyToReg
776 // c2, f2 = CopyToReg
777 // c3 = TokenFactor c1, c2
780 Chain = Chains[NumRegs-1];
782 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
785 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
786 /// operand list. This adds the code marker and includes the number of
787 /// values added into it.
788 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
789 unsigned MatchingIdx,
791 std::vector<SDValue> &Ops) const {
792 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
794 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
796 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
797 else if (!Regs.empty() &&
798 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
799 // Put the register class of the virtual registers in the flag word. That
800 // way, later passes can recompute register class constraints for inline
801 // assembly as well as normal instructions.
802 // Don't do this for tied operands that can use the regclass information
804 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
805 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
806 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
809 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
812 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
813 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
814 EVT RegisterVT = RegVTs[Value];
815 for (unsigned i = 0; i != NumRegs; ++i) {
816 assert(Reg < Regs.size() && "Mismatch in # registers expected");
817 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
822 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
823 const TargetLibraryInfo *li) {
827 TD = DAG.getTarget().getTargetData();
828 LPadToCallSiteMap.clear();
831 /// clear - Clear out the current SelectionDAG and the associated
832 /// state and prepare this SelectionDAGBuilder object to be used
833 /// for a new block. This doesn't clear out information about
834 /// additional blocks that are needed to complete switch lowering
835 /// or PHI node updating; that information is cleared out as it is
837 void SelectionDAGBuilder::clear() {
839 UnusedArgNodeMap.clear();
840 PendingLoads.clear();
841 PendingExports.clear();
842 CurDebugLoc = DebugLoc();
846 /// clearDanglingDebugInfo - Clear the dangling debug information
847 /// map. This function is separated from the clear so that debug
848 /// information that is dangling in a basic block can be properly
849 /// resolved in a different basic block. This allows the
850 /// SelectionDAG to resolve dangling debug information attached
852 void SelectionDAGBuilder::clearDanglingDebugInfo() {
853 DanglingDebugInfoMap.clear();
856 /// getRoot - Return the current virtual root of the Selection DAG,
857 /// flushing any PendingLoad items. This must be done before emitting
858 /// a store or any other node that may need to be ordered after any
859 /// prior load instructions.
861 SDValue SelectionDAGBuilder::getRoot() {
862 if (PendingLoads.empty())
863 return DAG.getRoot();
865 if (PendingLoads.size() == 1) {
866 SDValue Root = PendingLoads[0];
868 PendingLoads.clear();
872 // Otherwise, we have to make a token factor node.
873 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
874 &PendingLoads[0], PendingLoads.size());
875 PendingLoads.clear();
880 /// getControlRoot - Similar to getRoot, but instead of flushing all the
881 /// PendingLoad items, flush all the PendingExports items. It is necessary
882 /// to do this before emitting a terminator instruction.
884 SDValue SelectionDAGBuilder::getControlRoot() {
885 SDValue Root = DAG.getRoot();
887 if (PendingExports.empty())
890 // Turn all of the CopyToReg chains into one factored node.
891 if (Root.getOpcode() != ISD::EntryToken) {
892 unsigned i = 0, e = PendingExports.size();
893 for (; i != e; ++i) {
894 assert(PendingExports[i].getNode()->getNumOperands() > 1);
895 if (PendingExports[i].getNode()->getOperand(0) == Root)
896 break; // Don't add the root if we already indirectly depend on it.
900 PendingExports.push_back(Root);
903 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
905 PendingExports.size());
906 PendingExports.clear();
911 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
912 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
913 DAG.AssignOrdering(Node, SDNodeOrder);
915 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
916 AssignOrderingToNode(Node->getOperand(I).getNode());
919 void SelectionDAGBuilder::visit(const Instruction &I) {
920 // Set up outgoing PHI node register values before emitting the terminator.
921 if (isa<TerminatorInst>(&I))
922 HandlePHINodesInSuccessorBlocks(I.getParent());
924 CurDebugLoc = I.getDebugLoc();
926 visit(I.getOpcode(), I);
928 if (!isa<TerminatorInst>(&I) && !HasTailCall)
929 CopyToExportRegsIfNeeded(&I);
931 CurDebugLoc = DebugLoc();
934 void SelectionDAGBuilder::visitPHI(const PHINode &) {
935 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
938 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
939 // Note: this doesn't use InstVisitor, because it has to work with
940 // ConstantExpr's in addition to instructions.
942 default: llvm_unreachable("Unknown instruction type encountered!");
943 // Build the switch statement using the Instruction.def file.
944 #define HANDLE_INST(NUM, OPCODE, CLASS) \
945 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
946 #include "llvm/Instruction.def"
949 // Assign the ordering to the freshly created DAG nodes.
950 if (NodeMap.count(&I)) {
952 AssignOrderingToNode(getValue(&I).getNode());
956 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
957 // generate the debug data structures now that we've seen its definition.
958 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
960 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
962 const DbgValueInst *DI = DDI.getDI();
963 DebugLoc dl = DDI.getdl();
964 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
965 MDNode *Variable = DI->getVariable();
966 uint64_t Offset = DI->getOffset();
969 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
970 SDV = DAG.getDbgValue(Variable, Val.getNode(),
971 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
972 DAG.AddDbgValue(SDV, Val.getNode(), false);
975 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
976 DanglingDebugInfoMap[V] = DanglingDebugInfo();
980 /// getValue - Return an SDValue for the given Value.
981 SDValue SelectionDAGBuilder::getValue(const Value *V) {
982 // If we already have an SDValue for this value, use it. It's important
983 // to do this first, so that we don't create a CopyFromReg if we already
984 // have a regular SDValue.
985 SDValue &N = NodeMap[V];
986 if (N.getNode()) return N;
988 // If there's a virtual register allocated and initialized for this
990 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
991 if (It != FuncInfo.ValueMap.end()) {
992 unsigned InReg = It->second;
993 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
994 SDValue Chain = DAG.getEntryNode();
995 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
996 resolveDanglingDebugInfo(V, N);
1000 // Otherwise create a new SDValue and remember it.
1001 SDValue Val = getValueImpl(V);
1003 resolveDanglingDebugInfo(V, Val);
1007 /// getNonRegisterValue - Return an SDValue for the given Value, but
1008 /// don't look in FuncInfo.ValueMap for a virtual register.
1009 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1010 // If we already have an SDValue for this value, use it.
1011 SDValue &N = NodeMap[V];
1012 if (N.getNode()) return N;
1014 // Otherwise create a new SDValue and remember it.
1015 SDValue Val = getValueImpl(V);
1017 resolveDanglingDebugInfo(V, Val);
1021 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1022 /// Create an SDValue for the given value.
1023 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1024 if (const Constant *C = dyn_cast<Constant>(V)) {
1025 EVT VT = TLI.getValueType(V->getType(), true);
1027 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1028 return DAG.getConstant(*CI, VT);
1030 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1031 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
1033 if (isa<ConstantPointerNull>(C))
1034 return DAG.getConstant(0, TLI.getPointerTy());
1036 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1037 return DAG.getConstantFP(*CFP, VT);
1039 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1040 return DAG.getUNDEF(VT);
1042 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1043 visit(CE->getOpcode(), *CE);
1044 SDValue N1 = NodeMap[V];
1045 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1049 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1050 SmallVector<SDValue, 4> Constants;
1051 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1053 SDNode *Val = getValue(*OI).getNode();
1054 // If the operand is an empty aggregate, there are no values.
1056 // Add each leaf value from the operand to the Constants list
1057 // to form a flattened list of all the values.
1058 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1059 Constants.push_back(SDValue(Val, i));
1062 return DAG.getMergeValues(&Constants[0], Constants.size(),
1066 if (const ConstantDataSequential *CDS =
1067 dyn_cast<ConstantDataSequential>(C)) {
1068 SmallVector<SDValue, 4> Ops;
1069 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1070 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1071 // Add each leaf value from the operand to the Constants list
1072 // to form a flattened list of all the values.
1073 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1074 Ops.push_back(SDValue(Val, i));
1077 if (isa<ArrayType>(CDS->getType()))
1078 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc());
1079 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1080 VT, &Ops[0], Ops.size());
1083 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1084 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1085 "Unknown struct or array constant!");
1087 SmallVector<EVT, 4> ValueVTs;
1088 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1089 unsigned NumElts = ValueVTs.size();
1091 return SDValue(); // empty struct
1092 SmallVector<SDValue, 4> Constants(NumElts);
1093 for (unsigned i = 0; i != NumElts; ++i) {
1094 EVT EltVT = ValueVTs[i];
1095 if (isa<UndefValue>(C))
1096 Constants[i] = DAG.getUNDEF(EltVT);
1097 else if (EltVT.isFloatingPoint())
1098 Constants[i] = DAG.getConstantFP(0, EltVT);
1100 Constants[i] = DAG.getConstant(0, EltVT);
1103 return DAG.getMergeValues(&Constants[0], NumElts,
1107 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1108 return DAG.getBlockAddress(BA, VT);
1110 VectorType *VecTy = cast<VectorType>(V->getType());
1111 unsigned NumElements = VecTy->getNumElements();
1113 // Now that we know the number and type of the elements, get that number of
1114 // elements into the Ops array based on what kind of constant it is.
1115 SmallVector<SDValue, 16> Ops;
1116 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1117 for (unsigned i = 0; i != NumElements; ++i)
1118 Ops.push_back(getValue(CV->getOperand(i)));
1120 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1121 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1124 if (EltVT.isFloatingPoint())
1125 Op = DAG.getConstantFP(0, EltVT);
1127 Op = DAG.getConstant(0, EltVT);
1128 Ops.assign(NumElements, Op);
1131 // Create a BUILD_VECTOR node.
1132 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1133 VT, &Ops[0], Ops.size());
1136 // If this is a static alloca, generate it as the frameindex instead of
1138 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1139 DenseMap<const AllocaInst*, int>::iterator SI =
1140 FuncInfo.StaticAllocaMap.find(AI);
1141 if (SI != FuncInfo.StaticAllocaMap.end())
1142 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1145 // If this is an instruction which fast-isel has deferred, select it now.
1146 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1147 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1148 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1149 SDValue Chain = DAG.getEntryNode();
1150 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1153 llvm_unreachable("Can't get register for value!");
1156 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1157 SDValue Chain = getControlRoot();
1158 SmallVector<ISD::OutputArg, 8> Outs;
1159 SmallVector<SDValue, 8> OutVals;
1161 if (!FuncInfo.CanLowerReturn) {
1162 unsigned DemoteReg = FuncInfo.DemoteRegister;
1163 const Function *F = I.getParent()->getParent();
1165 // Emit a store of the return value through the virtual register.
1166 // Leave Outs empty so that LowerReturn won't try to load return
1167 // registers the usual way.
1168 SmallVector<EVT, 1> PtrValueVTs;
1169 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1172 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1173 SDValue RetOp = getValue(I.getOperand(0));
1175 SmallVector<EVT, 4> ValueVTs;
1176 SmallVector<uint64_t, 4> Offsets;
1177 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1178 unsigned NumValues = ValueVTs.size();
1180 SmallVector<SDValue, 4> Chains(NumValues);
1181 for (unsigned i = 0; i != NumValues; ++i) {
1182 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1183 RetPtr.getValueType(), RetPtr,
1184 DAG.getIntPtrConstant(Offsets[i]));
1186 DAG.getStore(Chain, getCurDebugLoc(),
1187 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1188 // FIXME: better loc info would be nice.
1189 Add, MachinePointerInfo(), false, false, 0);
1192 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1193 MVT::Other, &Chains[0], NumValues);
1194 } else if (I.getNumOperands() != 0) {
1195 SmallVector<EVT, 4> ValueVTs;
1196 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1197 unsigned NumValues = ValueVTs.size();
1199 SDValue RetOp = getValue(I.getOperand(0));
1200 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1201 EVT VT = ValueVTs[j];
1203 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1205 const Function *F = I.getParent()->getParent();
1206 if (F->paramHasAttr(0, Attribute::SExt))
1207 ExtendKind = ISD::SIGN_EXTEND;
1208 else if (F->paramHasAttr(0, Attribute::ZExt))
1209 ExtendKind = ISD::ZERO_EXTEND;
1211 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1212 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1214 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1215 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1216 SmallVector<SDValue, 4> Parts(NumParts);
1217 getCopyToParts(DAG, getCurDebugLoc(),
1218 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1219 &Parts[0], NumParts, PartVT, ExtendKind);
1221 // 'inreg' on function refers to return value
1222 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1223 if (F->paramHasAttr(0, Attribute::InReg))
1226 // Propagate extension type if any
1227 if (ExtendKind == ISD::SIGN_EXTEND)
1229 else if (ExtendKind == ISD::ZERO_EXTEND)
1232 for (unsigned i = 0; i < NumParts; ++i) {
1233 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1235 OutVals.push_back(Parts[i]);
1241 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1242 CallingConv::ID CallConv =
1243 DAG.getMachineFunction().getFunction()->getCallingConv();
1244 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1245 Outs, OutVals, getCurDebugLoc(), DAG);
1247 // Verify that the target's LowerReturn behaved as expected.
1248 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1249 "LowerReturn didn't return a valid chain!");
1251 // Update the DAG with the new chain value resulting from return lowering.
1255 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1256 /// created for it, emit nodes to copy the value into the virtual
1258 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1260 if (V->getType()->isEmptyTy())
1263 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1264 if (VMI != FuncInfo.ValueMap.end()) {
1265 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1266 CopyValueToVirtualRegister(V, VMI->second);
1270 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1271 /// the current basic block, add it to ValueMap now so that we'll get a
1273 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1274 // No need to export constants.
1275 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1277 // Already exported?
1278 if (FuncInfo.isExportedInst(V)) return;
1280 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1281 CopyValueToVirtualRegister(V, Reg);
1284 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1285 const BasicBlock *FromBB) {
1286 // The operands of the setcc have to be in this block. We don't know
1287 // how to export them from some other block.
1288 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1289 // Can export from current BB.
1290 if (VI->getParent() == FromBB)
1293 // Is already exported, noop.
1294 return FuncInfo.isExportedInst(V);
1297 // If this is an argument, we can export it if the BB is the entry block or
1298 // if it is already exported.
1299 if (isa<Argument>(V)) {
1300 if (FromBB == &FromBB->getParent()->getEntryBlock())
1303 // Otherwise, can only export this if it is already exported.
1304 return FuncInfo.isExportedInst(V);
1307 // Otherwise, constants can always be exported.
1311 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1312 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1313 const MachineBasicBlock *Dst) const {
1314 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1317 const BasicBlock *SrcBB = Src->getBasicBlock();
1318 const BasicBlock *DstBB = Dst->getBasicBlock();
1319 return BPI->getEdgeWeight(SrcBB, DstBB);
1322 void SelectionDAGBuilder::
1323 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1324 uint32_t Weight /* = 0 */) {
1326 Weight = getEdgeWeight(Src, Dst);
1327 Src->addSuccessor(Dst, Weight);
1331 static bool InBlock(const Value *V, const BasicBlock *BB) {
1332 if (const Instruction *I = dyn_cast<Instruction>(V))
1333 return I->getParent() == BB;
1337 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1338 /// This function emits a branch and is used at the leaves of an OR or an
1339 /// AND operator tree.
1342 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1343 MachineBasicBlock *TBB,
1344 MachineBasicBlock *FBB,
1345 MachineBasicBlock *CurBB,
1346 MachineBasicBlock *SwitchBB) {
1347 const BasicBlock *BB = CurBB->getBasicBlock();
1349 // If the leaf of the tree is a comparison, merge the condition into
1351 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1352 // The operands of the cmp have to be in this block. We don't know
1353 // how to export them from some other block. If this is the first block
1354 // of the sequence, no exporting is needed.
1355 if (CurBB == SwitchBB ||
1356 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1357 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1358 ISD::CondCode Condition;
1359 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1360 Condition = getICmpCondCode(IC->getPredicate());
1361 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1362 Condition = getFCmpCondCode(FC->getPredicate());
1363 if (TM.Options.NoNaNsFPMath)
1364 Condition = getFCmpCodeWithoutNaN(Condition);
1366 Condition = ISD::SETEQ; // silence warning.
1367 llvm_unreachable("Unknown compare instruction");
1370 CaseBlock CB(Condition, BOp->getOperand(0),
1371 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1372 SwitchCases.push_back(CB);
1377 // Create a CaseBlock record representing this branch.
1378 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1379 NULL, TBB, FBB, CurBB);
1380 SwitchCases.push_back(CB);
1383 /// FindMergedConditions - If Cond is an expression like
1384 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1385 MachineBasicBlock *TBB,
1386 MachineBasicBlock *FBB,
1387 MachineBasicBlock *CurBB,
1388 MachineBasicBlock *SwitchBB,
1390 // If this node is not part of the or/and tree, emit it as a branch.
1391 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1392 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1393 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1394 BOp->getParent() != CurBB->getBasicBlock() ||
1395 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1396 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1397 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1401 // Create TmpBB after CurBB.
1402 MachineFunction::iterator BBI = CurBB;
1403 MachineFunction &MF = DAG.getMachineFunction();
1404 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1405 CurBB->getParent()->insert(++BBI, TmpBB);
1407 if (Opc == Instruction::Or) {
1408 // Codegen X | Y as:
1416 // Emit the LHS condition.
1417 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1419 // Emit the RHS condition into TmpBB.
1420 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1422 assert(Opc == Instruction::And && "Unknown merge op!");
1423 // Codegen X & Y as:
1430 // This requires creation of TmpBB after CurBB.
1432 // Emit the LHS condition.
1433 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1435 // Emit the RHS condition into TmpBB.
1436 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1440 /// If the set of cases should be emitted as a series of branches, return true.
1441 /// If we should emit this as a bunch of and/or'd together conditions, return
1444 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1445 if (Cases.size() != 2) return true;
1447 // If this is two comparisons of the same values or'd or and'd together, they
1448 // will get folded into a single comparison, so don't emit two blocks.
1449 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1450 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1451 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1452 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1456 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1457 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1458 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1459 Cases[0].CC == Cases[1].CC &&
1460 isa<Constant>(Cases[0].CmpRHS) &&
1461 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1462 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1464 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1471 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1472 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1474 // Update machine-CFG edges.
1475 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1477 // Figure out which block is immediately after the current one.
1478 MachineBasicBlock *NextBlock = 0;
1479 MachineFunction::iterator BBI = BrMBB;
1480 if (++BBI != FuncInfo.MF->end())
1483 if (I.isUnconditional()) {
1484 // Update machine-CFG edges.
1485 BrMBB->addSuccessor(Succ0MBB);
1487 // If this is not a fall-through branch, emit the branch.
1488 if (Succ0MBB != NextBlock)
1489 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1490 MVT::Other, getControlRoot(),
1491 DAG.getBasicBlock(Succ0MBB)));
1496 // If this condition is one of the special cases we handle, do special stuff
1498 const Value *CondVal = I.getCondition();
1499 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1501 // If this is a series of conditions that are or'd or and'd together, emit
1502 // this as a sequence of branches instead of setcc's with and/or operations.
1503 // As long as jumps are not expensive, this should improve performance.
1504 // For example, instead of something like:
1517 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1518 if (!TLI.isJumpExpensive() &&
1520 (BOp->getOpcode() == Instruction::And ||
1521 BOp->getOpcode() == Instruction::Or)) {
1522 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1524 // If the compares in later blocks need to use values not currently
1525 // exported from this block, export them now. This block should always
1526 // be the first entry.
1527 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1529 // Allow some cases to be rejected.
1530 if (ShouldEmitAsBranches(SwitchCases)) {
1531 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1532 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1533 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1536 // Emit the branch for this block.
1537 visitSwitchCase(SwitchCases[0], BrMBB);
1538 SwitchCases.erase(SwitchCases.begin());
1542 // Okay, we decided not to do this, remove any inserted MBB's and clear
1544 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1545 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1547 SwitchCases.clear();
1551 // Create a CaseBlock record representing this branch.
1552 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1553 NULL, Succ0MBB, Succ1MBB, BrMBB);
1555 // Use visitSwitchCase to actually insert the fast branch sequence for this
1557 visitSwitchCase(CB, BrMBB);
1560 /// visitSwitchCase - Emits the necessary code to represent a single node in
1561 /// the binary search tree resulting from lowering a switch instruction.
1562 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1563 MachineBasicBlock *SwitchBB) {
1565 SDValue CondLHS = getValue(CB.CmpLHS);
1566 DebugLoc dl = getCurDebugLoc();
1568 // Build the setcc now.
1569 if (CB.CmpMHS == NULL) {
1570 // Fold "(X == true)" to X and "(X == false)" to !X to
1571 // handle common cases produced by branch lowering.
1572 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1573 CB.CC == ISD::SETEQ)
1575 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1576 CB.CC == ISD::SETEQ) {
1577 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1578 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1580 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1582 assert(CB.CC == ISD::SETCC_INVALID &&
1583 "Condition is undefined for to-the-range belonging check.");
1585 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1586 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1588 SDValue CmpOp = getValue(CB.CmpMHS);
1589 EVT VT = CmpOp.getValueType();
1591 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) {
1592 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1595 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1596 VT, CmpOp, DAG.getConstant(Low, VT));
1597 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1598 DAG.getConstant(High-Low, VT), ISD::SETULE);
1602 // Update successor info
1603 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1604 // TrueBB and FalseBB are always different unless the incoming IR is
1605 // degenerate. This only happens when running llc on weird IR.
1606 if (CB.TrueBB != CB.FalseBB)
1607 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1609 // Set NextBlock to be the MBB immediately after the current one, if any.
1610 // This is used to avoid emitting unnecessary branches to the next block.
1611 MachineBasicBlock *NextBlock = 0;
1612 MachineFunction::iterator BBI = SwitchBB;
1613 if (++BBI != FuncInfo.MF->end())
1616 // If the lhs block is the next block, invert the condition so that we can
1617 // fall through to the lhs instead of the rhs block.
1618 if (CB.TrueBB == NextBlock) {
1619 std::swap(CB.TrueBB, CB.FalseBB);
1620 SDValue True = DAG.getConstant(1, Cond.getValueType());
1621 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1624 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1625 MVT::Other, getControlRoot(), Cond,
1626 DAG.getBasicBlock(CB.TrueBB));
1628 // Insert the false branch. Do this even if it's a fall through branch,
1629 // this makes it easier to do DAG optimizations which require inverting
1630 // the branch condition.
1631 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1632 DAG.getBasicBlock(CB.FalseBB));
1634 DAG.setRoot(BrCond);
1637 /// visitJumpTable - Emit JumpTable node in the current MBB
1638 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1639 // Emit the code for the jump table
1640 assert(JT.Reg != -1U && "Should lower JT Header first!");
1641 EVT PTy = TLI.getPointerTy();
1642 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1644 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1645 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1646 MVT::Other, Index.getValue(1),
1648 DAG.setRoot(BrJumpTable);
1651 /// visitJumpTableHeader - This function emits necessary code to produce index
1652 /// in the JumpTable from switch case.
1653 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1654 JumpTableHeader &JTH,
1655 MachineBasicBlock *SwitchBB) {
1656 // Subtract the lowest switch case value from the value being switched on and
1657 // conditional branch to default mbb if the result is greater than the
1658 // difference between smallest and largest cases.
1659 SDValue SwitchOp = getValue(JTH.SValue);
1660 EVT VT = SwitchOp.getValueType();
1661 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1662 DAG.getConstant(JTH.First, VT));
1664 // The SDNode we just created, which holds the value being switched on minus
1665 // the smallest case value, needs to be copied to a virtual register so it
1666 // can be used as an index into the jump table in a subsequent basic block.
1667 // This value may be smaller or larger than the target's pointer type, and
1668 // therefore require extension or truncating.
1669 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1671 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1672 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1673 JumpTableReg, SwitchOp);
1674 JT.Reg = JumpTableReg;
1676 // Emit the range check for the jump table, and branch to the default block
1677 // for the switch statement if the value being switched on exceeds the largest
1678 // case in the switch.
1679 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1680 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1681 DAG.getConstant(JTH.Last-JTH.First,VT),
1684 // Set NextBlock to be the MBB immediately after the current one, if any.
1685 // This is used to avoid emitting unnecessary branches to the next block.
1686 MachineBasicBlock *NextBlock = 0;
1687 MachineFunction::iterator BBI = SwitchBB;
1689 if (++BBI != FuncInfo.MF->end())
1692 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1693 MVT::Other, CopyTo, CMP,
1694 DAG.getBasicBlock(JT.Default));
1696 if (JT.MBB != NextBlock)
1697 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1698 DAG.getBasicBlock(JT.MBB));
1700 DAG.setRoot(BrCond);
1703 /// visitBitTestHeader - This function emits necessary code to produce value
1704 /// suitable for "bit tests"
1705 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1706 MachineBasicBlock *SwitchBB) {
1707 // Subtract the minimum value
1708 SDValue SwitchOp = getValue(B.SValue);
1709 EVT VT = SwitchOp.getValueType();
1710 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1711 DAG.getConstant(B.First, VT));
1714 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1715 TLI.getSetCCResultType(Sub.getValueType()),
1716 Sub, DAG.getConstant(B.Range, VT),
1719 // Determine the type of the test operands.
1720 bool UsePtrType = false;
1721 if (!TLI.isTypeLegal(VT))
1724 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1725 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1726 // Switch table case range are encoded into series of masks.
1727 // Just use pointer type, it's guaranteed to fit.
1733 VT = TLI.getPointerTy();
1734 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1738 B.Reg = FuncInfo.CreateReg(VT);
1739 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1742 // Set NextBlock to be the MBB immediately after the current one, if any.
1743 // This is used to avoid emitting unnecessary branches to the next block.
1744 MachineBasicBlock *NextBlock = 0;
1745 MachineFunction::iterator BBI = SwitchBB;
1746 if (++BBI != FuncInfo.MF->end())
1749 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1751 addSuccessorWithWeight(SwitchBB, B.Default);
1752 addSuccessorWithWeight(SwitchBB, MBB);
1754 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1755 MVT::Other, CopyTo, RangeCmp,
1756 DAG.getBasicBlock(B.Default));
1758 if (MBB != NextBlock)
1759 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1760 DAG.getBasicBlock(MBB));
1762 DAG.setRoot(BrRange);
1765 /// visitBitTestCase - this function produces one "bit test"
1766 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1767 MachineBasicBlock* NextMBB,
1770 MachineBasicBlock *SwitchBB) {
1772 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1775 unsigned PopCount = CountPopulation_64(B.Mask);
1776 if (PopCount == 1) {
1777 // Testing for a single bit; just compare the shift count with what it
1778 // would need to be to shift a 1 bit in that position.
1779 Cmp = DAG.getSetCC(getCurDebugLoc(),
1780 TLI.getSetCCResultType(VT),
1782 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1784 } else if (PopCount == BB.Range) {
1785 // There is only one zero bit in the range, test for it directly.
1786 Cmp = DAG.getSetCC(getCurDebugLoc(),
1787 TLI.getSetCCResultType(VT),
1789 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1792 // Make desired shift
1793 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1794 DAG.getConstant(1, VT), ShiftOp);
1796 // Emit bit tests and jumps
1797 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1798 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1799 Cmp = DAG.getSetCC(getCurDebugLoc(),
1800 TLI.getSetCCResultType(VT),
1801 AndOp, DAG.getConstant(0, VT),
1805 addSuccessorWithWeight(SwitchBB, B.TargetBB);
1806 addSuccessorWithWeight(SwitchBB, NextMBB);
1808 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1809 MVT::Other, getControlRoot(),
1810 Cmp, DAG.getBasicBlock(B.TargetBB));
1812 // Set NextBlock to be the MBB immediately after the current one, if any.
1813 // This is used to avoid emitting unnecessary branches to the next block.
1814 MachineBasicBlock *NextBlock = 0;
1815 MachineFunction::iterator BBI = SwitchBB;
1816 if (++BBI != FuncInfo.MF->end())
1819 if (NextMBB != NextBlock)
1820 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1821 DAG.getBasicBlock(NextMBB));
1826 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1827 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1829 // Retrieve successors.
1830 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1831 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1833 const Value *Callee(I.getCalledValue());
1834 const Function *Fn = dyn_cast<Function>(Callee);
1835 if (isa<InlineAsm>(Callee))
1837 else if (Fn && Fn->isIntrinsic()) {
1838 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
1839 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1841 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1843 // If the value of the invoke is used outside of its defining block, make it
1844 // available as a virtual register.
1845 CopyToExportRegsIfNeeded(&I);
1847 // Update successor info
1848 addSuccessorWithWeight(InvokeMBB, Return);
1849 addSuccessorWithWeight(InvokeMBB, LandingPad);
1851 // Drop into normal successor.
1852 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1853 MVT::Other, getControlRoot(),
1854 DAG.getBasicBlock(Return)));
1857 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1858 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1861 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1862 assert(FuncInfo.MBB->isLandingPad() &&
1863 "Call to landingpad not in landing pad!");
1865 MachineBasicBlock *MBB = FuncInfo.MBB;
1866 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1867 AddLandingPadInfo(LP, MMI, MBB);
1869 // If there aren't registers to copy the values into (e.g., during SjLj
1870 // exceptions), then don't bother to create these DAG nodes.
1871 if (TLI.getExceptionPointerRegister() == 0 &&
1872 TLI.getExceptionSelectorRegister() == 0)
1875 SmallVector<EVT, 2> ValueVTs;
1876 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
1878 // Insert the EXCEPTIONADDR instruction.
1879 assert(FuncInfo.MBB->isLandingPad() &&
1880 "Call to eh.exception not in landing pad!");
1881 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1883 Ops[0] = DAG.getRoot();
1884 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1);
1885 SDValue Chain = Op1.getValue(1);
1887 // Insert the EHSELECTION instruction.
1888 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1891 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2);
1892 Chain = Op2.getValue(1);
1893 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32);
1897 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
1898 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1901 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
1902 setValue(&LP, RetPair.first);
1903 DAG.setRoot(RetPair.second);
1906 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1907 /// small case ranges).
1908 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1909 CaseRecVector& WorkList,
1911 MachineBasicBlock *Default,
1912 MachineBasicBlock *SwitchBB) {
1913 // Size is the number of Cases represented by this range.
1914 size_t Size = CR.Range.second - CR.Range.first;
1918 // Get the MachineFunction which holds the current MBB. This is used when
1919 // inserting any additional MBBs necessary to represent the switch.
1920 MachineFunction *CurMF = FuncInfo.MF;
1922 // Figure out which block is immediately after the current one.
1923 MachineBasicBlock *NextBlock = 0;
1924 MachineFunction::iterator BBI = CR.CaseBB;
1926 if (++BBI != FuncInfo.MF->end())
1929 // If any two of the cases has the same destination, and if one value
1930 // is the same as the other, but has one bit unset that the other has set,
1931 // use bit manipulation to do two compares at once. For example:
1932 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1933 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1934 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1935 if (Size == 2 && CR.CaseBB == SwitchBB) {
1936 Case &Small = *CR.Range.first;
1937 Case &Big = *(CR.Range.second-1);
1939 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1940 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1941 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1943 // Check that there is only one bit different.
1944 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1945 (SmallValue | BigValue) == BigValue) {
1946 // Isolate the common bit.
1947 APInt CommonBit = BigValue & ~SmallValue;
1948 assert((SmallValue | CommonBit) == BigValue &&
1949 CommonBit.countPopulation() == 1 && "Not a common bit?");
1951 SDValue CondLHS = getValue(SV);
1952 EVT VT = CondLHS.getValueType();
1953 DebugLoc DL = getCurDebugLoc();
1955 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1956 DAG.getConstant(CommonBit, VT));
1957 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1958 Or, DAG.getConstant(BigValue, VT),
1961 // Update successor info.
1962 addSuccessorWithWeight(SwitchBB, Small.BB);
1963 addSuccessorWithWeight(SwitchBB, Default);
1965 // Insert the true branch.
1966 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1967 getControlRoot(), Cond,
1968 DAG.getBasicBlock(Small.BB));
1970 // Insert the false branch.
1971 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1972 DAG.getBasicBlock(Default));
1974 DAG.setRoot(BrCond);
1980 // Order cases by weight so the most likely case will be checked first.
1981 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1983 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
1984 uint32_t IWeight = BPI->getEdgeWeight(SwitchBB->getBasicBlock(),
1985 I->BB->getBasicBlock());
1986 for (CaseItr J = CR.Range.first; J < I; ++J) {
1987 uint32_t JWeight = BPI->getEdgeWeight(SwitchBB->getBasicBlock(),
1988 J->BB->getBasicBlock());
1989 if (IWeight > JWeight)
1994 // Rearrange the case blocks so that the last one falls through if possible.
1995 Case &BackCase = *(CR.Range.second-1);
1997 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1998 // The last case block won't fall through into 'NextBlock' if we emit the
1999 // branches in this order. See if rearranging a case value would help.
2000 // We start at the bottom as it's the case with the least weight.
2001 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){
2002 if (I->BB == NextBlock) {
2003 std::swap(*I, BackCase);
2009 // Create a CaseBlock record representing a conditional branch to
2010 // the Case's target mbb if the value being switched on SV is equal
2012 MachineBasicBlock *CurBlock = CR.CaseBB;
2013 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2014 MachineBasicBlock *FallThrough;
2016 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2017 CurMF->insert(BBI, FallThrough);
2019 // Put SV in a virtual register to make it available from the new blocks.
2020 ExportFromCurrentBlock(SV);
2022 // If the last case doesn't match, go to the default block.
2023 FallThrough = Default;
2026 const Value *RHS, *LHS, *MHS;
2028 if (I->High == I->Low) {
2029 // This is just small small case range :) containing exactly 1 case
2031 LHS = SV; RHS = I->High; MHS = NULL;
2033 CC = ISD::SETCC_INVALID;
2034 LHS = I->Low; MHS = SV; RHS = I->High;
2037 uint32_t ExtraWeight = I->ExtraWeight;
2038 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2040 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2);
2042 // If emitting the first comparison, just call visitSwitchCase to emit the
2043 // code into the current block. Otherwise, push the CaseBlock onto the
2044 // vector to be later processed by SDISel, and insert the node's MBB
2045 // before the next MBB.
2046 if (CurBlock == SwitchBB)
2047 visitSwitchCase(CB, SwitchBB);
2049 SwitchCases.push_back(CB);
2051 CurBlock = FallThrough;
2057 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2058 return TLI.supportJumpTables() &&
2059 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2060 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2063 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2064 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2065 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth);
2066 return (LastExt - FirstExt + 1ULL);
2069 /// handleJTSwitchCase - Emit jumptable for current switch case range
2070 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2071 CaseRecVector &WorkList,
2073 MachineBasicBlock *Default,
2074 MachineBasicBlock *SwitchBB) {
2075 Case& FrontCase = *CR.Range.first;
2076 Case& BackCase = *(CR.Range.second-1);
2078 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2079 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2081 APInt TSize(First.getBitWidth(), 0);
2082 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2085 if (!areJTsAllowed(TLI) || TSize.ult(4))
2088 APInt Range = ComputeRange(First, Last);
2089 // The density is TSize / Range. Require at least 40%.
2090 // It should not be possible for IntTSize to saturate for sane code, but make
2091 // sure we handle Range saturation correctly.
2092 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2093 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2094 if (IntTSize * 10 < IntRange * 4)
2097 DEBUG(dbgs() << "Lowering jump table\n"
2098 << "First entry: " << First << ". Last entry: " << Last << '\n'
2099 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2101 // Get the MachineFunction which holds the current MBB. This is used when
2102 // inserting any additional MBBs necessary to represent the switch.
2103 MachineFunction *CurMF = FuncInfo.MF;
2105 // Figure out which block is immediately after the current one.
2106 MachineFunction::iterator BBI = CR.CaseBB;
2109 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2111 // Create a new basic block to hold the code for loading the address
2112 // of the jump table, and jumping to it. Update successor information;
2113 // we will either branch to the default case for the switch, or the jump
2115 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2116 CurMF->insert(BBI, JumpTableBB);
2118 addSuccessorWithWeight(CR.CaseBB, Default);
2119 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2121 // Build a vector of destination BBs, corresponding to each target
2122 // of the jump table. If the value of the jump table slot corresponds to
2123 // a case statement, push the case's BB onto the vector, otherwise, push
2125 std::vector<MachineBasicBlock*> DestBBs;
2127 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2128 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2129 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2131 if (Low.ule(TEI) && TEI.ule(High)) {
2132 DestBBs.push_back(I->BB);
2136 DestBBs.push_back(Default);
2140 // Update successor info. Add one edge to each unique successor.
2141 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2142 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2143 E = DestBBs.end(); I != E; ++I) {
2144 if (!SuccsHandled[(*I)->getNumber()]) {
2145 SuccsHandled[(*I)->getNumber()] = true;
2146 addSuccessorWithWeight(JumpTableBB, *I);
2150 // Create a jump table index for this jump table.
2151 unsigned JTEncoding = TLI.getJumpTableEncoding();
2152 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2153 ->createJumpTableIndex(DestBBs);
2155 // Set the jump table information so that we can codegen it as a second
2156 // MachineBasicBlock
2157 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2158 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2159 if (CR.CaseBB == SwitchBB)
2160 visitJumpTableHeader(JT, JTH, SwitchBB);
2162 JTCases.push_back(JumpTableBlock(JTH, JT));
2166 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2168 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2169 CaseRecVector& WorkList,
2171 MachineBasicBlock *Default,
2172 MachineBasicBlock *SwitchBB) {
2173 // Get the MachineFunction which holds the current MBB. This is used when
2174 // inserting any additional MBBs necessary to represent the switch.
2175 MachineFunction *CurMF = FuncInfo.MF;
2177 // Figure out which block is immediately after the current one.
2178 MachineFunction::iterator BBI = CR.CaseBB;
2181 Case& FrontCase = *CR.Range.first;
2182 Case& BackCase = *(CR.Range.second-1);
2183 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2185 // Size is the number of Cases represented by this range.
2186 unsigned Size = CR.Range.second - CR.Range.first;
2188 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2189 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2191 CaseItr Pivot = CR.Range.first + Size/2;
2193 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2194 // (heuristically) allow us to emit JumpTable's later.
2195 APInt TSize(First.getBitWidth(), 0);
2196 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2200 APInt LSize = FrontCase.size();
2201 APInt RSize = TSize-LSize;
2202 DEBUG(dbgs() << "Selecting best pivot: \n"
2203 << "First: " << First << ", Last: " << Last <<'\n'
2204 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2205 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2207 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2208 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2209 APInt Range = ComputeRange(LEnd, RBegin);
2210 assert((Range - 2ULL).isNonNegative() &&
2211 "Invalid case distance");
2212 // Use volatile double here to avoid excess precision issues on some hosts,
2213 // e.g. that use 80-bit X87 registers.
2214 volatile double LDensity =
2215 (double)LSize.roundToDouble() /
2216 (LEnd - First + 1ULL).roundToDouble();
2217 volatile double RDensity =
2218 (double)RSize.roundToDouble() /
2219 (Last - RBegin + 1ULL).roundToDouble();
2220 double Metric = Range.logBase2()*(LDensity+RDensity);
2221 // Should always split in some non-trivial place
2222 DEBUG(dbgs() <<"=>Step\n"
2223 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2224 << "LDensity: " << LDensity
2225 << ", RDensity: " << RDensity << '\n'
2226 << "Metric: " << Metric << '\n');
2227 if (FMetric < Metric) {
2230 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2236 if (areJTsAllowed(TLI)) {
2237 // If our case is dense we *really* should handle it earlier!
2238 assert((FMetric > 0) && "Should handle dense range earlier!");
2240 Pivot = CR.Range.first + Size/2;
2243 CaseRange LHSR(CR.Range.first, Pivot);
2244 CaseRange RHSR(Pivot, CR.Range.second);
2245 const Constant *C = Pivot->Low;
2246 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2248 // We know that we branch to the LHS if the Value being switched on is
2249 // less than the Pivot value, C. We use this to optimize our binary
2250 // tree a bit, by recognizing that if SV is greater than or equal to the
2251 // LHS's Case Value, and that Case Value is exactly one less than the
2252 // Pivot's Value, then we can branch directly to the LHS's Target,
2253 // rather than creating a leaf node for it.
2254 if ((LHSR.second - LHSR.first) == 1 &&
2255 LHSR.first->High == CR.GE &&
2256 cast<ConstantInt>(C)->getValue() ==
2257 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2258 TrueBB = LHSR.first->BB;
2260 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2261 CurMF->insert(BBI, TrueBB);
2262 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2264 // Put SV in a virtual register to make it available from the new blocks.
2265 ExportFromCurrentBlock(SV);
2268 // Similar to the optimization above, if the Value being switched on is
2269 // known to be less than the Constant CR.LT, and the current Case Value
2270 // is CR.LT - 1, then we can branch directly to the target block for
2271 // the current Case Value, rather than emitting a RHS leaf node for it.
2272 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2273 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2274 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2275 FalseBB = RHSR.first->BB;
2277 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2278 CurMF->insert(BBI, FalseBB);
2279 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2281 // Put SV in a virtual register to make it available from the new blocks.
2282 ExportFromCurrentBlock(SV);
2285 // Create a CaseBlock record representing a conditional branch to
2286 // the LHS node if the value being switched on SV is less than C.
2287 // Otherwise, branch to LHS.
2288 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2290 if (CR.CaseBB == SwitchBB)
2291 visitSwitchCase(CB, SwitchBB);
2293 SwitchCases.push_back(CB);
2298 /// handleBitTestsSwitchCase - if current case range has few destination and
2299 /// range span less, than machine word bitwidth, encode case range into series
2300 /// of masks and emit bit tests with these masks.
2301 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2302 CaseRecVector& WorkList,
2304 MachineBasicBlock* Default,
2305 MachineBasicBlock *SwitchBB){
2306 EVT PTy = TLI.getPointerTy();
2307 unsigned IntPtrBits = PTy.getSizeInBits();
2309 Case& FrontCase = *CR.Range.first;
2310 Case& BackCase = *(CR.Range.second-1);
2312 // Get the MachineFunction which holds the current MBB. This is used when
2313 // inserting any additional MBBs necessary to represent the switch.
2314 MachineFunction *CurMF = FuncInfo.MF;
2316 // If target does not have legal shift left, do not emit bit tests at all.
2317 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2321 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2323 // Single case counts one, case range - two.
2324 numCmps += (I->Low == I->High ? 1 : 2);
2327 // Count unique destinations
2328 SmallSet<MachineBasicBlock*, 4> Dests;
2329 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2330 Dests.insert(I->BB);
2331 if (Dests.size() > 3)
2332 // Don't bother the code below, if there are too much unique destinations
2335 DEBUG(dbgs() << "Total number of unique destinations: "
2336 << Dests.size() << '\n'
2337 << "Total number of comparisons: " << numCmps << '\n');
2339 // Compute span of values.
2340 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2341 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2342 APInt cmpRange = maxValue - minValue;
2344 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2345 << "Low bound: " << minValue << '\n'
2346 << "High bound: " << maxValue << '\n');
2348 if (cmpRange.uge(IntPtrBits) ||
2349 (!(Dests.size() == 1 && numCmps >= 3) &&
2350 !(Dests.size() == 2 && numCmps >= 5) &&
2351 !(Dests.size() >= 3 && numCmps >= 6)))
2354 DEBUG(dbgs() << "Emitting bit tests\n");
2355 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2357 // Optimize the case where all the case values fit in a
2358 // word without having to subtract minValue. In this case,
2359 // we can optimize away the subtraction.
2360 if (maxValue.ult(IntPtrBits)) {
2361 cmpRange = maxValue;
2363 lowBound = minValue;
2366 CaseBitsVector CasesBits;
2367 unsigned i, count = 0;
2369 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2370 MachineBasicBlock* Dest = I->BB;
2371 for (i = 0; i < count; ++i)
2372 if (Dest == CasesBits[i].BB)
2376 assert((count < 3) && "Too much destinations to test!");
2377 CasesBits.push_back(CaseBits(0, Dest, 0));
2381 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2382 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2384 uint64_t lo = (lowValue - lowBound).getZExtValue();
2385 uint64_t hi = (highValue - lowBound).getZExtValue();
2387 for (uint64_t j = lo; j <= hi; j++) {
2388 CasesBits[i].Mask |= 1ULL << j;
2389 CasesBits[i].Bits++;
2393 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2397 // Figure out which block is immediately after the current one.
2398 MachineFunction::iterator BBI = CR.CaseBB;
2401 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2403 DEBUG(dbgs() << "Cases:\n");
2404 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2405 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2406 << ", Bits: " << CasesBits[i].Bits
2407 << ", BB: " << CasesBits[i].BB << '\n');
2409 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2410 CurMF->insert(BBI, CaseBB);
2411 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2415 // Put SV in a virtual register to make it available from the new blocks.
2416 ExportFromCurrentBlock(SV);
2419 BitTestBlock BTB(lowBound, cmpRange, SV,
2420 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2421 CR.CaseBB, Default, BTC);
2423 if (CR.CaseBB == SwitchBB)
2424 visitBitTestHeader(BTB, SwitchBB);
2426 BitTestCases.push_back(BTB);
2431 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2432 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2433 const SwitchInst& SI) {
2435 /// Use a shorter form of declaration, and also
2436 /// show the we want to use CRSBuilder as Clusterifier.
2437 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier;
2439 Clusterifier TheClusterifier;
2441 // Start with "simple" cases
2442 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2444 const BasicBlock *SuccBB = i.getCaseSuccessor();
2445 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2447 TheClusterifier.add(i.getCaseValueEx(), SMBB);
2450 TheClusterifier.optimize();
2452 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2454 for (Clusterifier::RangeIterator i = TheClusterifier.begin(),
2455 e = TheClusterifier.end(); i != e; ++i, ++numCmps) {
2456 Clusterifier::Cluster &C = *i;
2459 W = BPI->getEdgeWeight(SI.getParent(), C.second->getBasicBlock());
2462 W *= C.first.Weight;
2463 BPI->setEdgeWeight(SI.getParent(), C.second->getBasicBlock(), W);
2466 // FIXME: Currently work with ConstantInt based numbers.
2467 // Changing it to APInt based is a pretty heavy for this commit.
2468 Cases.push_back(Case(C.first.getLow().toConstantInt(),
2469 C.first.getHigh().toConstantInt(), C.second, W));
2471 if (C.first.getLow() != C.first.getHigh())
2472 // A range counts double, since it requires two compares.
2479 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2480 MachineBasicBlock *Last) {
2482 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2483 if (JTCases[i].first.HeaderBB == First)
2484 JTCases[i].first.HeaderBB = Last;
2486 // Update BitTestCases.
2487 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2488 if (BitTestCases[i].Parent == First)
2489 BitTestCases[i].Parent = Last;
2492 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2493 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2495 // Figure out which block is immediately after the current one.
2496 MachineBasicBlock *NextBlock = 0;
2497 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2499 // If there is only the default destination, branch to it if it is not the
2500 // next basic block. Otherwise, just fall through.
2501 if (!SI.getNumCases()) {
2502 // Update machine-CFG edges.
2504 // If this is not a fall-through branch, emit the branch.
2505 SwitchMBB->addSuccessor(Default);
2506 if (Default != NextBlock)
2507 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2508 MVT::Other, getControlRoot(),
2509 DAG.getBasicBlock(Default)));
2514 // If there are any non-default case statements, create a vector of Cases
2515 // representing each one, and sort the vector so that we can efficiently
2516 // create a binary search tree from them.
2518 size_t numCmps = Clusterify(Cases, SI);
2519 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2520 << ". Total compares: " << numCmps << '\n');
2523 // Get the Value to be switched on and default basic blocks, which will be
2524 // inserted into CaseBlock records, representing basic blocks in the binary
2526 const Value *SV = SI.getCondition();
2528 // Push the initial CaseRec onto the worklist
2529 CaseRecVector WorkList;
2530 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2531 CaseRange(Cases.begin(),Cases.end())));
2533 while (!WorkList.empty()) {
2534 // Grab a record representing a case range to process off the worklist
2535 CaseRec CR = WorkList.back();
2536 WorkList.pop_back();
2538 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2541 // If the range has few cases (two or less) emit a series of specific
2543 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2546 // If the switch has more than 5 blocks, and at least 40% dense, and the
2547 // target supports indirect branches, then emit a jump table rather than
2548 // lowering the switch to a binary tree of conditional branches.
2549 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2552 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2553 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2554 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2558 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2559 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2561 // Update machine-CFG edges with unique successors.
2562 SmallVector<BasicBlock*, 32> succs;
2563 succs.reserve(I.getNumSuccessors());
2564 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2565 succs.push_back(I.getSuccessor(i));
2566 array_pod_sort(succs.begin(), succs.end());
2567 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2568 for (unsigned i = 0, e = succs.size(); i != e; ++i) {
2569 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]];
2570 addSuccessorWithWeight(IndirectBrMBB, Succ);
2573 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2574 MVT::Other, getControlRoot(),
2575 getValue(I.getAddress())));
2578 void SelectionDAGBuilder::visitFSub(const User &I) {
2579 // -0.0 - X --> fneg
2580 Type *Ty = I.getType();
2581 if (isa<Constant>(I.getOperand(0)) &&
2582 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2583 SDValue Op2 = getValue(I.getOperand(1));
2584 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2585 Op2.getValueType(), Op2));
2589 visitBinary(I, ISD::FSUB);
2592 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2593 SDValue Op1 = getValue(I.getOperand(0));
2594 SDValue Op2 = getValue(I.getOperand(1));
2595 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2596 Op1.getValueType(), Op1, Op2));
2599 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2600 SDValue Op1 = getValue(I.getOperand(0));
2601 SDValue Op2 = getValue(I.getOperand(1));
2603 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2605 // Coerce the shift amount to the right type if we can.
2606 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2607 unsigned ShiftSize = ShiftTy.getSizeInBits();
2608 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2609 DebugLoc DL = getCurDebugLoc();
2611 // If the operand is smaller than the shift count type, promote it.
2612 if (ShiftSize > Op2Size)
2613 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2615 // If the operand is larger than the shift count type but the shift
2616 // count type has enough bits to represent any shift value, truncate
2617 // it now. This is a common case and it exposes the truncate to
2618 // optimization early.
2619 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2620 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2621 // Otherwise we'll need to temporarily settle for some other convenient
2622 // type. Type legalization will make adjustments once the shiftee is split.
2624 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2627 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2628 Op1.getValueType(), Op1, Op2));
2631 void SelectionDAGBuilder::visitSDiv(const User &I) {
2632 SDValue Op1 = getValue(I.getOperand(0));
2633 SDValue Op2 = getValue(I.getOperand(1));
2635 // Turn exact SDivs into multiplications.
2636 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2638 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2639 !isa<ConstantSDNode>(Op1) &&
2640 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2641 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
2643 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
2647 void SelectionDAGBuilder::visitICmp(const User &I) {
2648 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2649 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2650 predicate = IC->getPredicate();
2651 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2652 predicate = ICmpInst::Predicate(IC->getPredicate());
2653 SDValue Op1 = getValue(I.getOperand(0));
2654 SDValue Op2 = getValue(I.getOperand(1));
2655 ISD::CondCode Opcode = getICmpCondCode(predicate);
2657 EVT DestVT = TLI.getValueType(I.getType());
2658 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2661 void SelectionDAGBuilder::visitFCmp(const User &I) {
2662 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2663 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2664 predicate = FC->getPredicate();
2665 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2666 predicate = FCmpInst::Predicate(FC->getPredicate());
2667 SDValue Op1 = getValue(I.getOperand(0));
2668 SDValue Op2 = getValue(I.getOperand(1));
2669 ISD::CondCode Condition = getFCmpCondCode(predicate);
2670 if (TM.Options.NoNaNsFPMath)
2671 Condition = getFCmpCodeWithoutNaN(Condition);
2672 EVT DestVT = TLI.getValueType(I.getType());
2673 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2676 void SelectionDAGBuilder::visitSelect(const User &I) {
2677 SmallVector<EVT, 4> ValueVTs;
2678 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2679 unsigned NumValues = ValueVTs.size();
2680 if (NumValues == 0) return;
2682 SmallVector<SDValue, 4> Values(NumValues);
2683 SDValue Cond = getValue(I.getOperand(0));
2684 SDValue TrueVal = getValue(I.getOperand(1));
2685 SDValue FalseVal = getValue(I.getOperand(2));
2686 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2687 ISD::VSELECT : ISD::SELECT;
2689 for (unsigned i = 0; i != NumValues; ++i)
2690 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(),
2691 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2693 SDValue(TrueVal.getNode(),
2694 TrueVal.getResNo() + i),
2695 SDValue(FalseVal.getNode(),
2696 FalseVal.getResNo() + i));
2698 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2699 DAG.getVTList(&ValueVTs[0], NumValues),
2700 &Values[0], NumValues));
2703 void SelectionDAGBuilder::visitTrunc(const User &I) {
2704 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2705 SDValue N = getValue(I.getOperand(0));
2706 EVT DestVT = TLI.getValueType(I.getType());
2707 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2710 void SelectionDAGBuilder::visitZExt(const User &I) {
2711 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2712 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2713 SDValue N = getValue(I.getOperand(0));
2714 EVT DestVT = TLI.getValueType(I.getType());
2715 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2718 void SelectionDAGBuilder::visitSExt(const User &I) {
2719 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2720 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2721 SDValue N = getValue(I.getOperand(0));
2722 EVT DestVT = TLI.getValueType(I.getType());
2723 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2726 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2727 // FPTrunc is never a no-op cast, no need to check
2728 SDValue N = getValue(I.getOperand(0));
2729 EVT DestVT = TLI.getValueType(I.getType());
2730 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2732 DAG.getTargetConstant(0, TLI.getPointerTy())));
2735 void SelectionDAGBuilder::visitFPExt(const User &I){
2736 // FPExt is never a no-op cast, no need to check
2737 SDValue N = getValue(I.getOperand(0));
2738 EVT DestVT = TLI.getValueType(I.getType());
2739 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2742 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2743 // FPToUI is never a no-op cast, no need to check
2744 SDValue N = getValue(I.getOperand(0));
2745 EVT DestVT = TLI.getValueType(I.getType());
2746 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2749 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2750 // FPToSI is never a no-op cast, no need to check
2751 SDValue N = getValue(I.getOperand(0));
2752 EVT DestVT = TLI.getValueType(I.getType());
2753 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2756 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2757 // UIToFP is never a no-op cast, no need to check
2758 SDValue N = getValue(I.getOperand(0));
2759 EVT DestVT = TLI.getValueType(I.getType());
2760 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2763 void SelectionDAGBuilder::visitSIToFP(const User &I){
2764 // SIToFP is never a no-op cast, no need to check
2765 SDValue N = getValue(I.getOperand(0));
2766 EVT DestVT = TLI.getValueType(I.getType());
2767 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2770 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2771 // What to do depends on the size of the integer and the size of the pointer.
2772 // We can either truncate, zero extend, or no-op, accordingly.
2773 SDValue N = getValue(I.getOperand(0));
2774 EVT DestVT = TLI.getValueType(I.getType());
2775 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2778 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2779 // What to do depends on the size of the integer and the size of the pointer.
2780 // We can either truncate, zero extend, or no-op, accordingly.
2781 SDValue N = getValue(I.getOperand(0));
2782 EVT DestVT = TLI.getValueType(I.getType());
2783 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2786 void SelectionDAGBuilder::visitBitCast(const User &I) {
2787 SDValue N = getValue(I.getOperand(0));
2788 EVT DestVT = TLI.getValueType(I.getType());
2790 // BitCast assures us that source and destination are the same size so this is
2791 // either a BITCAST or a no-op.
2792 if (DestVT != N.getValueType())
2793 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2794 DestVT, N)); // convert types.
2796 setValue(&I, N); // noop cast.
2799 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2800 SDValue InVec = getValue(I.getOperand(0));
2801 SDValue InVal = getValue(I.getOperand(1));
2802 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2804 getValue(I.getOperand(2)));
2805 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2806 TLI.getValueType(I.getType()),
2807 InVec, InVal, InIdx));
2810 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2811 SDValue InVec = getValue(I.getOperand(0));
2812 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2814 getValue(I.getOperand(1)));
2815 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2816 TLI.getValueType(I.getType()), InVec, InIdx));
2819 // Utility for visitShuffleVector - Return true if every element in Mask,
2820 // beginning from position Pos and ending in Pos+Size, falls within the
2821 // specified sequential range [L, L+Pos). or is undef.
2822 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2823 unsigned Pos, unsigned Size, int Low) {
2824 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2825 if (Mask[i] >= 0 && Mask[i] != Low)
2830 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2831 SDValue Src1 = getValue(I.getOperand(0));
2832 SDValue Src2 = getValue(I.getOperand(1));
2834 SmallVector<int, 8> Mask;
2835 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2836 unsigned MaskNumElts = Mask.size();
2838 EVT VT = TLI.getValueType(I.getType());
2839 EVT SrcVT = Src1.getValueType();
2840 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2842 if (SrcNumElts == MaskNumElts) {
2843 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2848 // Normalize the shuffle vector since mask and vector length don't match.
2849 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2850 // Mask is longer than the source vectors and is a multiple of the source
2851 // vectors. We can use concatenate vector to make the mask and vectors
2853 if (SrcNumElts*2 == MaskNumElts) {
2854 // First check for Src1 in low and Src2 in high
2855 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2856 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2857 // The shuffle is concatenating two vectors together.
2858 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2862 // Then check for Src2 in low and Src1 in high
2863 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2864 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2865 // The shuffle is concatenating two vectors together.
2866 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2872 // Pad both vectors with undefs to make them the same length as the mask.
2873 unsigned NumConcat = MaskNumElts / SrcNumElts;
2874 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2875 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2876 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2878 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2879 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2883 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2884 getCurDebugLoc(), VT,
2885 &MOps1[0], NumConcat);
2886 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2887 getCurDebugLoc(), VT,
2888 &MOps2[0], NumConcat);
2890 // Readjust mask for new input vector length.
2891 SmallVector<int, 8> MappedOps;
2892 for (unsigned i = 0; i != MaskNumElts; ++i) {
2894 if (Idx >= (int)SrcNumElts)
2895 Idx -= SrcNumElts - MaskNumElts;
2896 MappedOps.push_back(Idx);
2899 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2904 if (SrcNumElts > MaskNumElts) {
2905 // Analyze the access pattern of the vector to see if we can extract
2906 // two subvectors and do the shuffle. The analysis is done by calculating
2907 // the range of elements the mask access on both vectors.
2908 int MinRange[2] = { static_cast<int>(SrcNumElts),
2909 static_cast<int>(SrcNumElts)};
2910 int MaxRange[2] = {-1, -1};
2912 for (unsigned i = 0; i != MaskNumElts; ++i) {
2918 if (Idx >= (int)SrcNumElts) {
2922 if (Idx > MaxRange[Input])
2923 MaxRange[Input] = Idx;
2924 if (Idx < MinRange[Input])
2925 MinRange[Input] = Idx;
2928 // Check if the access is smaller than the vector size and can we find
2929 // a reasonable extract index.
2930 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2932 int StartIdx[2]; // StartIdx to extract from
2933 for (unsigned Input = 0; Input < 2; ++Input) {
2934 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2935 RangeUse[Input] = 0; // Unused
2936 StartIdx[Input] = 0;
2940 // Find a good start index that is a multiple of the mask length. Then
2941 // see if the rest of the elements are in range.
2942 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2943 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2944 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2945 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2948 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2949 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2952 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2953 // Extract appropriate subvector and generate a vector shuffle
2954 for (unsigned Input = 0; Input < 2; ++Input) {
2955 SDValue &Src = Input == 0 ? Src1 : Src2;
2956 if (RangeUse[Input] == 0)
2957 Src = DAG.getUNDEF(VT);
2959 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2960 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2963 // Calculate new mask.
2964 SmallVector<int, 8> MappedOps;
2965 for (unsigned i = 0; i != MaskNumElts; ++i) {
2968 if (Idx < (int)SrcNumElts)
2971 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2973 MappedOps.push_back(Idx);
2976 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2982 // We can't use either concat vectors or extract subvectors so fall back to
2983 // replacing the shuffle with extract and build vector.
2984 // to insert and build vector.
2985 EVT EltVT = VT.getVectorElementType();
2986 EVT PtrVT = TLI.getPointerTy();
2987 SmallVector<SDValue,8> Ops;
2988 for (unsigned i = 0; i != MaskNumElts; ++i) {
2993 Res = DAG.getUNDEF(EltVT);
2995 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2996 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2998 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2999 EltVT, Src, DAG.getConstant(Idx, PtrVT));
3005 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
3006 VT, &Ops[0], Ops.size()));
3009 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3010 const Value *Op0 = I.getOperand(0);
3011 const Value *Op1 = I.getOperand(1);
3012 Type *AggTy = I.getType();
3013 Type *ValTy = Op1->getType();
3014 bool IntoUndef = isa<UndefValue>(Op0);
3015 bool FromUndef = isa<UndefValue>(Op1);
3017 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3019 SmallVector<EVT, 4> AggValueVTs;
3020 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3021 SmallVector<EVT, 4> ValValueVTs;
3022 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3024 unsigned NumAggValues = AggValueVTs.size();
3025 unsigned NumValValues = ValValueVTs.size();
3026 SmallVector<SDValue, 4> Values(NumAggValues);
3028 SDValue Agg = getValue(Op0);
3030 // Copy the beginning value(s) from the original aggregate.
3031 for (; i != LinearIndex; ++i)
3032 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3033 SDValue(Agg.getNode(), Agg.getResNo() + i);
3034 // Copy values from the inserted value(s).
3036 SDValue Val = getValue(Op1);
3037 for (; i != LinearIndex + NumValValues; ++i)
3038 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3039 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3041 // Copy remaining value(s) from the original aggregate.
3042 for (; i != NumAggValues; ++i)
3043 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3044 SDValue(Agg.getNode(), Agg.getResNo() + i);
3046 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3047 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3048 &Values[0], NumAggValues));
3051 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3052 const Value *Op0 = I.getOperand(0);
3053 Type *AggTy = Op0->getType();
3054 Type *ValTy = I.getType();
3055 bool OutOfUndef = isa<UndefValue>(Op0);
3057 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3059 SmallVector<EVT, 4> ValValueVTs;
3060 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3062 unsigned NumValValues = ValValueVTs.size();
3064 // Ignore a extractvalue that produces an empty object
3065 if (!NumValValues) {
3066 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3070 SmallVector<SDValue, 4> Values(NumValValues);
3072 SDValue Agg = getValue(Op0);
3073 // Copy out the selected value(s).
3074 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3075 Values[i - LinearIndex] =
3077 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3078 SDValue(Agg.getNode(), Agg.getResNo() + i);
3080 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3081 DAG.getVTList(&ValValueVTs[0], NumValValues),
3082 &Values[0], NumValValues));
3085 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3086 SDValue N = getValue(I.getOperand(0));
3087 // Note that the pointer operand may be a vector of pointers. Take the scalar
3088 // element which holds a pointer.
3089 Type *Ty = I.getOperand(0)->getType()->getScalarType();
3091 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3093 const Value *Idx = *OI;
3094 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3095 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
3098 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3099 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3100 DAG.getIntPtrConstant(Offset));
3103 Ty = StTy->getElementType(Field);
3105 Ty = cast<SequentialType>(Ty)->getElementType();
3107 // If this is a constant subscript, handle it quickly.
3108 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3109 if (CI->isZero()) continue;
3111 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3113 EVT PTy = TLI.getPointerTy();
3114 unsigned PtrBits = PTy.getSizeInBits();
3116 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
3118 DAG.getConstant(Offs, MVT::i64));
3120 OffsVal = DAG.getIntPtrConstant(Offs);
3122 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3127 // N = N + Idx * ElementSize;
3128 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
3129 TD->getTypeAllocSize(Ty));
3130 SDValue IdxN = getValue(Idx);
3132 // If the index is smaller or larger than intptr_t, truncate or extend
3134 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
3136 // If this is a multiply by a power of two, turn it into a shl
3137 // immediately. This is a very common case.
3138 if (ElementSize != 1) {
3139 if (ElementSize.isPowerOf2()) {
3140 unsigned Amt = ElementSize.logBase2();
3141 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
3142 N.getValueType(), IdxN,
3143 DAG.getConstant(Amt, IdxN.getValueType()));
3145 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
3146 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
3147 N.getValueType(), IdxN, Scale);
3151 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3152 N.getValueType(), N, IdxN);
3159 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3160 // If this is a fixed sized alloca in the entry block of the function,
3161 // allocate it statically on the stack.
3162 if (FuncInfo.StaticAllocaMap.count(&I))
3163 return; // getValue will auto-populate this.
3165 Type *Ty = I.getAllocatedType();
3166 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
3168 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
3171 SDValue AllocSize = getValue(I.getArraySize());
3173 EVT IntPtr = TLI.getPointerTy();
3174 if (AllocSize.getValueType() != IntPtr)
3175 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
3177 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
3179 DAG.getConstant(TySize, IntPtr));
3181 // Handle alignment. If the requested alignment is less than or equal to
3182 // the stack alignment, ignore it. If the size is greater than or equal to
3183 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3184 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3185 if (Align <= StackAlign)
3188 // Round the size of the allocation up to the stack alignment size
3189 // by add SA-1 to the size.
3190 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3191 AllocSize.getValueType(), AllocSize,
3192 DAG.getIntPtrConstant(StackAlign-1));
3194 // Mask out the low bits for alignment purposes.
3195 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
3196 AllocSize.getValueType(), AllocSize,
3197 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3199 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3200 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3201 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3204 DAG.setRoot(DSA.getValue(1));
3206 // Inform the Frame Information that we have just allocated a variable-sized
3208 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3211 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3213 return visitAtomicLoad(I);
3215 const Value *SV = I.getOperand(0);
3216 SDValue Ptr = getValue(SV);
3218 Type *Ty = I.getType();
3220 bool isVolatile = I.isVolatile();
3221 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3222 bool isInvariant = I.getMetadata("invariant.load") != 0;
3223 unsigned Alignment = I.getAlignment();
3224 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3225 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3227 SmallVector<EVT, 4> ValueVTs;
3228 SmallVector<uint64_t, 4> Offsets;
3229 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3230 unsigned NumValues = ValueVTs.size();
3235 bool ConstantMemory = false;
3236 if (I.isVolatile() || NumValues > MaxParallelChains)
3237 // Serialize volatile loads with other side effects.
3239 else if (AA->pointsToConstantMemory(
3240 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3241 // Do not serialize (non-volatile) loads of constant memory with anything.
3242 Root = DAG.getEntryNode();
3243 ConstantMemory = true;
3245 // Do not serialize non-volatile loads against each other.
3246 Root = DAG.getRoot();
3249 SmallVector<SDValue, 4> Values(NumValues);
3250 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3252 EVT PtrVT = Ptr.getValueType();
3253 unsigned ChainI = 0;
3254 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3255 // Serializing loads here may result in excessive register pressure, and
3256 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3257 // could recover a bit by hoisting nodes upward in the chain by recognizing
3258 // they are side-effect free or do not alias. The optimizer should really
3259 // avoid this case by converting large object/array copies to llvm.memcpy
3260 // (MaxParallelChains should always remain as failsafe).
3261 if (ChainI == MaxParallelChains) {
3262 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3263 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3264 MVT::Other, &Chains[0], ChainI);
3268 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3270 DAG.getConstant(Offsets[i], PtrVT));
3271 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3272 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3273 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3277 Chains[ChainI] = L.getValue(1);
3280 if (!ConstantMemory) {
3281 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3282 MVT::Other, &Chains[0], ChainI);
3286 PendingLoads.push_back(Chain);
3289 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3290 DAG.getVTList(&ValueVTs[0], NumValues),
3291 &Values[0], NumValues));
3294 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3296 return visitAtomicStore(I);
3298 const Value *SrcV = I.getOperand(0);
3299 const Value *PtrV = I.getOperand(1);
3301 SmallVector<EVT, 4> ValueVTs;
3302 SmallVector<uint64_t, 4> Offsets;
3303 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3304 unsigned NumValues = ValueVTs.size();
3308 // Get the lowered operands. Note that we do this after
3309 // checking if NumResults is zero, because with zero results
3310 // the operands won't have values in the map.
3311 SDValue Src = getValue(SrcV);
3312 SDValue Ptr = getValue(PtrV);
3314 SDValue Root = getRoot();
3315 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3317 EVT PtrVT = Ptr.getValueType();
3318 bool isVolatile = I.isVolatile();
3319 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3320 unsigned Alignment = I.getAlignment();
3321 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3323 unsigned ChainI = 0;
3324 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3325 // See visitLoad comments.
3326 if (ChainI == MaxParallelChains) {
3327 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3328 MVT::Other, &Chains[0], ChainI);
3332 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3333 DAG.getConstant(Offsets[i], PtrVT));
3334 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3335 SDValue(Src.getNode(), Src.getResNo() + i),
3336 Add, MachinePointerInfo(PtrV, Offsets[i]),
3337 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3338 Chains[ChainI] = St;
3341 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3342 MVT::Other, &Chains[0], ChainI);
3344 AssignOrderingToNode(StoreNode.getNode());
3345 DAG.setRoot(StoreNode);
3348 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3349 SynchronizationScope Scope,
3350 bool Before, DebugLoc dl,
3352 const TargetLowering &TLI) {
3353 // Fence, if necessary
3355 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3357 else if (Order == Acquire || Order == Monotonic)
3360 if (Order == AcquireRelease)
3362 else if (Order == Release || Order == Monotonic)
3367 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3368 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3369 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3372 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3373 DebugLoc dl = getCurDebugLoc();
3374 AtomicOrdering Order = I.getOrdering();
3375 SynchronizationScope Scope = I.getSynchScope();
3377 SDValue InChain = getRoot();
3379 if (TLI.getInsertFencesForAtomic())
3380 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3384 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3385 getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
3387 getValue(I.getPointerOperand()),
3388 getValue(I.getCompareOperand()),
3389 getValue(I.getNewValOperand()),
3390 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3391 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3394 SDValue OutChain = L.getValue(1);
3396 if (TLI.getInsertFencesForAtomic())
3397 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3401 DAG.setRoot(OutChain);
3404 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3405 DebugLoc dl = getCurDebugLoc();
3407 switch (I.getOperation()) {
3408 default: llvm_unreachable("Unknown atomicrmw operation");
3409 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3410 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3411 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3412 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3413 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3414 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3415 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3416 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3417 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3418 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3419 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3421 AtomicOrdering Order = I.getOrdering();
3422 SynchronizationScope Scope = I.getSynchScope();
3424 SDValue InChain = getRoot();
3426 if (TLI.getInsertFencesForAtomic())
3427 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3431 DAG.getAtomic(NT, dl,
3432 getValue(I.getValOperand()).getValueType().getSimpleVT(),
3434 getValue(I.getPointerOperand()),
3435 getValue(I.getValOperand()),
3436 I.getPointerOperand(), 0 /* Alignment */,
3437 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3440 SDValue OutChain = L.getValue(1);
3442 if (TLI.getInsertFencesForAtomic())
3443 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3447 DAG.setRoot(OutChain);
3450 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3451 DebugLoc dl = getCurDebugLoc();
3454 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3455 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3456 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3459 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3460 DebugLoc dl = getCurDebugLoc();
3461 AtomicOrdering Order = I.getOrdering();
3462 SynchronizationScope Scope = I.getSynchScope();
3464 SDValue InChain = getRoot();
3466 EVT VT = TLI.getValueType(I.getType());
3468 if (I.getAlignment() * 8 < VT.getSizeInBits())
3469 report_fatal_error("Cannot generate unaligned atomic load");
3472 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3473 getValue(I.getPointerOperand()),
3474 I.getPointerOperand(), I.getAlignment(),
3475 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3478 SDValue OutChain = L.getValue(1);
3480 if (TLI.getInsertFencesForAtomic())
3481 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3485 DAG.setRoot(OutChain);
3488 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3489 DebugLoc dl = getCurDebugLoc();
3491 AtomicOrdering Order = I.getOrdering();
3492 SynchronizationScope Scope = I.getSynchScope();
3494 SDValue InChain = getRoot();
3496 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3498 if (I.getAlignment() * 8 < VT.getSizeInBits())
3499 report_fatal_error("Cannot generate unaligned atomic store");
3501 if (TLI.getInsertFencesForAtomic())
3502 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3506 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3508 getValue(I.getPointerOperand()),
3509 getValue(I.getValueOperand()),
3510 I.getPointerOperand(), I.getAlignment(),
3511 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3514 if (TLI.getInsertFencesForAtomic())
3515 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3518 DAG.setRoot(OutChain);
3521 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3523 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3524 unsigned Intrinsic) {
3525 bool HasChain = !I.doesNotAccessMemory();
3526 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3528 // Build the operand list.
3529 SmallVector<SDValue, 8> Ops;
3530 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3532 // We don't need to serialize loads against other loads.
3533 Ops.push_back(DAG.getRoot());
3535 Ops.push_back(getRoot());
3539 // Info is set by getTgtMemInstrinsic
3540 TargetLowering::IntrinsicInfo Info;
3541 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3543 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3544 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3545 Info.opc == ISD::INTRINSIC_W_CHAIN)
3546 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3548 // Add all operands of the call to the operand list.
3549 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3550 SDValue Op = getValue(I.getArgOperand(i));
3554 SmallVector<EVT, 4> ValueVTs;
3555 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3558 ValueVTs.push_back(MVT::Other);
3560 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3564 if (IsTgtIntrinsic) {
3565 // This is target intrinsic that touches memory
3566 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3567 VTs, &Ops[0], Ops.size(),
3569 MachinePointerInfo(Info.ptrVal, Info.offset),
3570 Info.align, Info.vol,
3571 Info.readMem, Info.writeMem);
3572 } else if (!HasChain) {
3573 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3574 VTs, &Ops[0], Ops.size());
3575 } else if (!I.getType()->isVoidTy()) {
3576 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3577 VTs, &Ops[0], Ops.size());
3579 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3580 VTs, &Ops[0], Ops.size());
3584 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3586 PendingLoads.push_back(Chain);
3591 if (!I.getType()->isVoidTy()) {
3592 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3593 EVT VT = TLI.getValueType(PTy);
3594 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3597 setValue(&I, Result);
3599 // Assign order to result here. If the intrinsic does not produce a result,
3600 // it won't be mapped to a SDNode and visit() will not assign it an order
3603 AssignOrderingToNode(Result.getNode());
3607 /// GetSignificand - Get the significand and build it into a floating-point
3608 /// number with exponent of 1:
3610 /// Op = (Op & 0x007fffff) | 0x3f800000;
3612 /// where Op is the hexidecimal representation of floating point value.
3614 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3615 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3616 DAG.getConstant(0x007fffff, MVT::i32));
3617 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3618 DAG.getConstant(0x3f800000, MVT::i32));
3619 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3622 /// GetExponent - Get the exponent:
3624 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3626 /// where Op is the hexidecimal representation of floating point value.
3628 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3630 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3631 DAG.getConstant(0x7f800000, MVT::i32));
3632 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3633 DAG.getConstant(23, TLI.getPointerTy()));
3634 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3635 DAG.getConstant(127, MVT::i32));
3636 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3639 /// getF32Constant - Get 32-bit floating point constant.
3641 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3642 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3645 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3646 /// limited-precision mode.
3648 SelectionDAGBuilder::visitExp(const CallInst &I) {
3650 DebugLoc dl = getCurDebugLoc();
3652 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3653 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3654 SDValue Op = getValue(I.getArgOperand(0));
3656 // Put the exponent in the right bit position for later addition to the
3659 // #define LOG2OFe 1.4426950f
3660 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3661 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3662 getF32Constant(DAG, 0x3fb8aa3b));
3663 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3665 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3666 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3667 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3669 // IntegerPartOfX <<= 23;
3670 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3671 DAG.getConstant(23, TLI.getPointerTy()));
3673 if (LimitFloatPrecision <= 6) {
3674 // For floating-point precision of 6:
3676 // TwoToFractionalPartOfX =
3678 // (0.735607626f + 0.252464424f * x) * x;
3680 // error 0.0144103317, which is 6 bits
3681 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3682 getF32Constant(DAG, 0x3e814304));
3683 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3684 getF32Constant(DAG, 0x3f3c50c8));
3685 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3686 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3687 getF32Constant(DAG, 0x3f7f5e7e));
3688 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3690 // Add the exponent into the result in integer domain.
3691 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3692 TwoToFracPartOfX, IntegerPartOfX);
3694 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3695 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3696 // For floating-point precision of 12:
3698 // TwoToFractionalPartOfX =
3701 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3703 // 0.000107046256 error, which is 13 to 14 bits
3704 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3705 getF32Constant(DAG, 0x3da235e3));
3706 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3707 getF32Constant(DAG, 0x3e65b8f3));
3708 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3709 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3710 getF32Constant(DAG, 0x3f324b07));
3711 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3712 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3713 getF32Constant(DAG, 0x3f7ff8fd));
3714 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3716 // Add the exponent into the result in integer domain.
3717 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3718 TwoToFracPartOfX, IntegerPartOfX);
3720 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3721 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3722 // For floating-point precision of 18:
3724 // TwoToFractionalPartOfX =
3728 // (0.554906021e-1f +
3729 // (0.961591928e-2f +
3730 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3732 // error 2.47208000*10^(-7), which is better than 18 bits
3733 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3734 getF32Constant(DAG, 0x3924b03e));
3735 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3736 getF32Constant(DAG, 0x3ab24b87));
3737 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3738 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3739 getF32Constant(DAG, 0x3c1d8c17));
3740 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3741 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3742 getF32Constant(DAG, 0x3d634a1d));
3743 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3744 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3745 getF32Constant(DAG, 0x3e75fe14));
3746 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3747 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3748 getF32Constant(DAG, 0x3f317234));
3749 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3750 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3751 getF32Constant(DAG, 0x3f800000));
3752 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3755 // Add the exponent into the result in integer domain.
3756 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3757 TwoToFracPartOfX, IntegerPartOfX);
3759 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3762 // No special expansion.
3763 result = DAG.getNode(ISD::FEXP, dl,
3764 getValue(I.getArgOperand(0)).getValueType(),
3765 getValue(I.getArgOperand(0)));
3768 setValue(&I, result);
3771 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3772 /// limited-precision mode.
3774 SelectionDAGBuilder::visitLog(const CallInst &I) {
3776 DebugLoc dl = getCurDebugLoc();
3778 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3779 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3780 SDValue Op = getValue(I.getArgOperand(0));
3781 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3783 // Scale the exponent by log(2) [0.69314718f].
3784 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3785 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3786 getF32Constant(DAG, 0x3f317218));
3788 // Get the significand and build it into a floating-point number with
3790 SDValue X = GetSignificand(DAG, Op1, dl);
3792 if (LimitFloatPrecision <= 6) {
3793 // For floating-point precision of 6:
3797 // (1.4034025f - 0.23903021f * x) * x;
3799 // error 0.0034276066, which is better than 8 bits
3800 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3801 getF32Constant(DAG, 0xbe74c456));
3802 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3803 getF32Constant(DAG, 0x3fb3a2b1));
3804 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3805 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3806 getF32Constant(DAG, 0x3f949a29));
3808 result = DAG.getNode(ISD::FADD, dl,
3809 MVT::f32, LogOfExponent, LogOfMantissa);
3810 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3811 // For floating-point precision of 12:
3817 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3819 // error 0.000061011436, which is 14 bits
3820 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3821 getF32Constant(DAG, 0xbd67b6d6));
3822 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3823 getF32Constant(DAG, 0x3ee4f4b8));
3824 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3825 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3826 getF32Constant(DAG, 0x3fbc278b));
3827 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3828 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3829 getF32Constant(DAG, 0x40348e95));
3830 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3831 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3832 getF32Constant(DAG, 0x3fdef31a));
3834 result = DAG.getNode(ISD::FADD, dl,
3835 MVT::f32, LogOfExponent, LogOfMantissa);
3836 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3837 // For floating-point precision of 18:
3845 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3847 // error 0.0000023660568, which is better than 18 bits
3848 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3849 getF32Constant(DAG, 0xbc91e5ac));
3850 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3851 getF32Constant(DAG, 0x3e4350aa));
3852 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3853 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3854 getF32Constant(DAG, 0x3f60d3e3));
3855 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3856 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3857 getF32Constant(DAG, 0x4011cdf0));
3858 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3859 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3860 getF32Constant(DAG, 0x406cfd1c));
3861 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3862 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3863 getF32Constant(DAG, 0x408797cb));
3864 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3865 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3866 getF32Constant(DAG, 0x4006dcab));
3868 result = DAG.getNode(ISD::FADD, dl,
3869 MVT::f32, LogOfExponent, LogOfMantissa);
3872 // No special expansion.
3873 result = DAG.getNode(ISD::FLOG, dl,
3874 getValue(I.getArgOperand(0)).getValueType(),
3875 getValue(I.getArgOperand(0)));
3878 setValue(&I, result);
3881 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3882 /// limited-precision mode.
3884 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3886 DebugLoc dl = getCurDebugLoc();
3888 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3889 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3890 SDValue Op = getValue(I.getArgOperand(0));
3891 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3893 // Get the exponent.
3894 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3896 // Get the significand and build it into a floating-point number with
3898 SDValue X = GetSignificand(DAG, Op1, dl);
3900 // Different possible minimax approximations of significand in
3901 // floating-point for various degrees of accuracy over [1,2].
3902 if (LimitFloatPrecision <= 6) {
3903 // For floating-point precision of 6:
3905 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3907 // error 0.0049451742, which is more than 7 bits
3908 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3909 getF32Constant(DAG, 0xbeb08fe0));
3910 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3911 getF32Constant(DAG, 0x40019463));
3912 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3913 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3914 getF32Constant(DAG, 0x3fd6633d));
3916 result = DAG.getNode(ISD::FADD, dl,
3917 MVT::f32, LogOfExponent, Log2ofMantissa);
3918 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3919 // For floating-point precision of 12:
3925 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3927 // error 0.0000876136000, which is better than 13 bits
3928 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3929 getF32Constant(DAG, 0xbda7262e));
3930 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3931 getF32Constant(DAG, 0x3f25280b));
3932 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3933 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3934 getF32Constant(DAG, 0x4007b923));
3935 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3936 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3937 getF32Constant(DAG, 0x40823e2f));
3938 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3939 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3940 getF32Constant(DAG, 0x4020d29c));
3942 result = DAG.getNode(ISD::FADD, dl,
3943 MVT::f32, LogOfExponent, Log2ofMantissa);
3944 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3945 // For floating-point precision of 18:
3954 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3956 // error 0.0000018516, which is better than 18 bits
3957 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3958 getF32Constant(DAG, 0xbcd2769e));
3959 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3960 getF32Constant(DAG, 0x3e8ce0b9));
3961 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3962 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3963 getF32Constant(DAG, 0x3fa22ae7));
3964 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3965 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3966 getF32Constant(DAG, 0x40525723));
3967 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3968 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3969 getF32Constant(DAG, 0x40aaf200));
3970 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3971 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3972 getF32Constant(DAG, 0x40c39dad));
3973 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3974 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3975 getF32Constant(DAG, 0x4042902c));
3977 result = DAG.getNode(ISD::FADD, dl,
3978 MVT::f32, LogOfExponent, Log2ofMantissa);
3981 // No special expansion.
3982 result = DAG.getNode(ISD::FLOG2, dl,
3983 getValue(I.getArgOperand(0)).getValueType(),
3984 getValue(I.getArgOperand(0)));
3987 setValue(&I, result);
3990 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3991 /// limited-precision mode.
3993 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3995 DebugLoc dl = getCurDebugLoc();
3997 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3998 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3999 SDValue Op = getValue(I.getArgOperand(0));
4000 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4002 // Scale the exponent by log10(2) [0.30102999f].
4003 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4004 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4005 getF32Constant(DAG, 0x3e9a209a));
4007 // Get the significand and build it into a floating-point number with
4009 SDValue X = GetSignificand(DAG, Op1, dl);
4011 if (LimitFloatPrecision <= 6) {
4012 // For floating-point precision of 6:
4014 // Log10ofMantissa =
4016 // (0.60948995f - 0.10380950f * x) * x;
4018 // error 0.0014886165, which is 6 bits
4019 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4020 getF32Constant(DAG, 0xbdd49a13));
4021 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4022 getF32Constant(DAG, 0x3f1c0789));
4023 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4024 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4025 getF32Constant(DAG, 0x3f011300));
4027 result = DAG.getNode(ISD::FADD, dl,
4028 MVT::f32, LogOfExponent, Log10ofMantissa);
4029 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4030 // For floating-point precision of 12:
4032 // Log10ofMantissa =
4035 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4037 // error 0.00019228036, which is better than 12 bits
4038 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4039 getF32Constant(DAG, 0x3d431f31));
4040 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4041 getF32Constant(DAG, 0x3ea21fb2));
4042 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4043 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4044 getF32Constant(DAG, 0x3f6ae232));
4045 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4046 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4047 getF32Constant(DAG, 0x3f25f7c3));
4049 result = DAG.getNode(ISD::FADD, dl,
4050 MVT::f32, LogOfExponent, Log10ofMantissa);
4051 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4052 // For floating-point precision of 18:
4054 // Log10ofMantissa =
4059 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4061 // error 0.0000037995730, which is better than 18 bits
4062 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4063 getF32Constant(DAG, 0x3c5d51ce));
4064 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4065 getF32Constant(DAG, 0x3e00685a));
4066 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4067 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4068 getF32Constant(DAG, 0x3efb6798));
4069 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4070 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4071 getF32Constant(DAG, 0x3f88d192));
4072 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4073 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4074 getF32Constant(DAG, 0x3fc4316c));
4075 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4076 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4077 getF32Constant(DAG, 0x3f57ce70));
4079 result = DAG.getNode(ISD::FADD, dl,
4080 MVT::f32, LogOfExponent, Log10ofMantissa);
4083 // No special expansion.
4084 result = DAG.getNode(ISD::FLOG10, dl,
4085 getValue(I.getArgOperand(0)).getValueType(),
4086 getValue(I.getArgOperand(0)));
4089 setValue(&I, result);
4092 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4093 /// limited-precision mode.
4095 SelectionDAGBuilder::visitExp2(const CallInst &I) {
4097 DebugLoc dl = getCurDebugLoc();
4099 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
4100 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4101 SDValue Op = getValue(I.getArgOperand(0));
4103 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4105 // FractionalPartOfX = x - (float)IntegerPartOfX;
4106 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4107 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4109 // IntegerPartOfX <<= 23;
4110 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4111 DAG.getConstant(23, TLI.getPointerTy()));
4113 if (LimitFloatPrecision <= 6) {
4114 // For floating-point precision of 6:
4116 // TwoToFractionalPartOfX =
4118 // (0.735607626f + 0.252464424f * x) * x;
4120 // error 0.0144103317, which is 6 bits
4121 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4122 getF32Constant(DAG, 0x3e814304));
4123 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4124 getF32Constant(DAG, 0x3f3c50c8));
4125 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4126 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4127 getF32Constant(DAG, 0x3f7f5e7e));
4128 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4129 SDValue TwoToFractionalPartOfX =
4130 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4132 result = DAG.getNode(ISD::BITCAST, dl,
4133 MVT::f32, TwoToFractionalPartOfX);
4134 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4135 // For floating-point precision of 12:
4137 // TwoToFractionalPartOfX =
4140 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4142 // error 0.000107046256, which is 13 to 14 bits
4143 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4144 getF32Constant(DAG, 0x3da235e3));
4145 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4146 getF32Constant(DAG, 0x3e65b8f3));
4147 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4148 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4149 getF32Constant(DAG, 0x3f324b07));
4150 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4151 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4152 getF32Constant(DAG, 0x3f7ff8fd));
4153 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4154 SDValue TwoToFractionalPartOfX =
4155 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4157 result = DAG.getNode(ISD::BITCAST, dl,
4158 MVT::f32, TwoToFractionalPartOfX);
4159 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4160 // For floating-point precision of 18:
4162 // TwoToFractionalPartOfX =
4166 // (0.554906021e-1f +
4167 // (0.961591928e-2f +
4168 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4169 // error 2.47208000*10^(-7), which is better than 18 bits
4170 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4171 getF32Constant(DAG, 0x3924b03e));
4172 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4173 getF32Constant(DAG, 0x3ab24b87));
4174 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4175 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4176 getF32Constant(DAG, 0x3c1d8c17));
4177 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4178 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4179 getF32Constant(DAG, 0x3d634a1d));
4180 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4181 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4182 getF32Constant(DAG, 0x3e75fe14));
4183 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4184 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4185 getF32Constant(DAG, 0x3f317234));
4186 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4187 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4188 getF32Constant(DAG, 0x3f800000));
4189 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4190 SDValue TwoToFractionalPartOfX =
4191 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4193 result = DAG.getNode(ISD::BITCAST, dl,
4194 MVT::f32, TwoToFractionalPartOfX);
4197 // No special expansion.
4198 result = DAG.getNode(ISD::FEXP2, dl,
4199 getValue(I.getArgOperand(0)).getValueType(),
4200 getValue(I.getArgOperand(0)));
4203 setValue(&I, result);
4206 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4207 /// limited-precision mode with x == 10.0f.
4209 SelectionDAGBuilder::visitPow(const CallInst &I) {
4211 const Value *Val = I.getArgOperand(0);
4212 DebugLoc dl = getCurDebugLoc();
4213 bool IsExp10 = false;
4215 if (getValue(Val).getValueType() == MVT::f32 &&
4216 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
4217 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4218 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
4219 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
4221 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
4226 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4227 SDValue Op = getValue(I.getArgOperand(1));
4229 // Put the exponent in the right bit position for later addition to the
4232 // #define LOG2OF10 3.3219281f
4233 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4234 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4235 getF32Constant(DAG, 0x40549a78));
4236 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4238 // FractionalPartOfX = x - (float)IntegerPartOfX;
4239 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4240 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4242 // IntegerPartOfX <<= 23;
4243 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4244 DAG.getConstant(23, TLI.getPointerTy()));
4246 if (LimitFloatPrecision <= 6) {
4247 // For floating-point precision of 6:
4249 // twoToFractionalPartOfX =
4251 // (0.735607626f + 0.252464424f * x) * x;
4253 // error 0.0144103317, which is 6 bits
4254 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4255 getF32Constant(DAG, 0x3e814304));
4256 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4257 getF32Constant(DAG, 0x3f3c50c8));
4258 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4259 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4260 getF32Constant(DAG, 0x3f7f5e7e));
4261 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4262 SDValue TwoToFractionalPartOfX =
4263 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4265 result = DAG.getNode(ISD::BITCAST, dl,
4266 MVT::f32, TwoToFractionalPartOfX);
4267 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4268 // For floating-point precision of 12:
4270 // TwoToFractionalPartOfX =
4273 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4275 // error 0.000107046256, which is 13 to 14 bits
4276 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4277 getF32Constant(DAG, 0x3da235e3));
4278 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4279 getF32Constant(DAG, 0x3e65b8f3));
4280 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4281 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4282 getF32Constant(DAG, 0x3f324b07));
4283 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4284 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4285 getF32Constant(DAG, 0x3f7ff8fd));
4286 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4287 SDValue TwoToFractionalPartOfX =
4288 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4290 result = DAG.getNode(ISD::BITCAST, dl,
4291 MVT::f32, TwoToFractionalPartOfX);
4292 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4293 // For floating-point precision of 18:
4295 // TwoToFractionalPartOfX =
4299 // (0.554906021e-1f +
4300 // (0.961591928e-2f +
4301 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4302 // error 2.47208000*10^(-7), which is better than 18 bits
4303 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4304 getF32Constant(DAG, 0x3924b03e));
4305 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4306 getF32Constant(DAG, 0x3ab24b87));
4307 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4308 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4309 getF32Constant(DAG, 0x3c1d8c17));
4310 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4311 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4312 getF32Constant(DAG, 0x3d634a1d));
4313 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4314 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4315 getF32Constant(DAG, 0x3e75fe14));
4316 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4317 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4318 getF32Constant(DAG, 0x3f317234));
4319 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4320 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4321 getF32Constant(DAG, 0x3f800000));
4322 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4323 SDValue TwoToFractionalPartOfX =
4324 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4326 result = DAG.getNode(ISD::BITCAST, dl,
4327 MVT::f32, TwoToFractionalPartOfX);
4330 // No special expansion.
4331 result = DAG.getNode(ISD::FPOW, dl,
4332 getValue(I.getArgOperand(0)).getValueType(),
4333 getValue(I.getArgOperand(0)),
4334 getValue(I.getArgOperand(1)));
4337 setValue(&I, result);
4341 /// ExpandPowI - Expand a llvm.powi intrinsic.
4342 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
4343 SelectionDAG &DAG) {
4344 // If RHS is a constant, we can expand this out to a multiplication tree,
4345 // otherwise we end up lowering to a call to __powidf2 (for example). When
4346 // optimizing for size, we only want to do this if the expansion would produce
4347 // a small number of multiplies, otherwise we do the full expansion.
4348 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4349 // Get the exponent as a positive value.
4350 unsigned Val = RHSC->getSExtValue();
4351 if ((int)Val < 0) Val = -Val;
4353 // powi(x, 0) -> 1.0
4355 return DAG.getConstantFP(1.0, LHS.getValueType());
4357 const Function *F = DAG.getMachineFunction().getFunction();
4358 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
4359 // If optimizing for size, don't insert too many multiplies. This
4360 // inserts up to 5 multiplies.
4361 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4362 // We use the simple binary decomposition method to generate the multiply
4363 // sequence. There are more optimal ways to do this (for example,
4364 // powi(x,15) generates one more multiply than it should), but this has
4365 // the benefit of being both really simple and much better than a libcall.
4366 SDValue Res; // Logically starts equal to 1.0
4367 SDValue CurSquare = LHS;
4371 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4373 Res = CurSquare; // 1.0*CurSquare.
4376 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4377 CurSquare, CurSquare);
4381 // If the original was negative, invert the result, producing 1/(x*x*x).
4382 if (RHSC->getSExtValue() < 0)
4383 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4384 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4389 // Otherwise, expand to a libcall.
4390 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4393 // getTruncatedArgReg - Find underlying register used for an truncated
4395 static unsigned getTruncatedArgReg(const SDValue &N) {
4396 if (N.getOpcode() != ISD::TRUNCATE)
4399 const SDValue &Ext = N.getOperand(0);
4400 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4401 const SDValue &CFR = Ext.getOperand(0);
4402 if (CFR.getOpcode() == ISD::CopyFromReg)
4403 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4404 if (CFR.getOpcode() == ISD::TRUNCATE)
4405 return getTruncatedArgReg(CFR);
4410 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4411 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4412 /// At the end of instruction selection, they will be inserted to the entry BB.
4414 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4417 const Argument *Arg = dyn_cast<Argument>(V);
4421 MachineFunction &MF = DAG.getMachineFunction();
4422 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4423 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4425 // Ignore inlined function arguments here.
4426 DIVariable DV(Variable);
4427 if (DV.isInlinedFnArgument(MF.getFunction()))
4431 // Some arguments' frame index is recorded during argument lowering.
4432 Offset = FuncInfo.getArgumentFrameIndex(Arg);
4434 Reg = TRI->getFrameRegister(MF);
4436 if (!Reg && N.getNode()) {
4437 if (N.getOpcode() == ISD::CopyFromReg)
4438 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4440 Reg = getTruncatedArgReg(N);
4441 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4442 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4443 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4450 // Check if ValueMap has reg number.
4451 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4452 if (VMI != FuncInfo.ValueMap.end())
4456 if (!Reg && N.getNode()) {
4457 // Check if frame index is available.
4458 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4459 if (FrameIndexSDNode *FINode =
4460 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4461 Reg = TRI->getFrameRegister(MF);
4462 Offset = FINode->getIndex();
4469 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4470 TII->get(TargetOpcode::DBG_VALUE))
4471 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4472 FuncInfo.ArgDbgValues.push_back(&*MIB);
4476 // VisualStudio defines setjmp as _setjmp
4477 #if defined(_MSC_VER) && defined(setjmp) && \
4478 !defined(setjmp_undefined_for_msvc)
4479 # pragma push_macro("setjmp")
4481 # define setjmp_undefined_for_msvc
4484 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4485 /// we want to emit this as a call to a named external function, return the name
4486 /// otherwise lower it and return null.
4488 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4489 DebugLoc dl = getCurDebugLoc();
4492 switch (Intrinsic) {
4494 // By default, turn this into a target intrinsic node.
4495 visitTargetIntrinsic(I, Intrinsic);
4497 case Intrinsic::vastart: visitVAStart(I); return 0;
4498 case Intrinsic::vaend: visitVAEnd(I); return 0;
4499 case Intrinsic::vacopy: visitVACopy(I); return 0;
4500 case Intrinsic::returnaddress:
4501 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4502 getValue(I.getArgOperand(0))));
4504 case Intrinsic::frameaddress:
4505 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4506 getValue(I.getArgOperand(0))));
4508 case Intrinsic::setjmp:
4509 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4510 case Intrinsic::longjmp:
4511 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4512 case Intrinsic::memcpy: {
4513 // Assert for address < 256 since we support only user defined address
4515 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4517 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4519 "Unknown address space");
4520 SDValue Op1 = getValue(I.getArgOperand(0));
4521 SDValue Op2 = getValue(I.getArgOperand(1));
4522 SDValue Op3 = getValue(I.getArgOperand(2));
4523 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4524 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4525 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4526 MachinePointerInfo(I.getArgOperand(0)),
4527 MachinePointerInfo(I.getArgOperand(1))));
4530 case Intrinsic::memset: {
4531 // Assert for address < 256 since we support only user defined address
4533 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4535 "Unknown address space");
4536 SDValue Op1 = getValue(I.getArgOperand(0));
4537 SDValue Op2 = getValue(I.getArgOperand(1));
4538 SDValue Op3 = getValue(I.getArgOperand(2));
4539 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4540 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4541 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4542 MachinePointerInfo(I.getArgOperand(0))));
4545 case Intrinsic::memmove: {
4546 // Assert for address < 256 since we support only user defined address
4548 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4550 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4552 "Unknown address space");
4553 SDValue Op1 = getValue(I.getArgOperand(0));
4554 SDValue Op2 = getValue(I.getArgOperand(1));
4555 SDValue Op3 = getValue(I.getArgOperand(2));
4556 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4557 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4558 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4559 MachinePointerInfo(I.getArgOperand(0)),
4560 MachinePointerInfo(I.getArgOperand(1))));
4563 case Intrinsic::dbg_declare: {
4564 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4565 MDNode *Variable = DI.getVariable();
4566 const Value *Address = DI.getAddress();
4567 if (!Address || !DIVariable(Variable).Verify()) {
4568 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4572 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4573 // but do not always have a corresponding SDNode built. The SDNodeOrder
4574 // absolute, but not relative, values are different depending on whether
4575 // debug info exists.
4578 // Check if address has undef value.
4579 if (isa<UndefValue>(Address) ||
4580 (Address->use_empty() && !isa<Argument>(Address))) {
4581 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4585 SDValue &N = NodeMap[Address];
4586 if (!N.getNode() && isa<Argument>(Address))
4587 // Check unused arguments map.
4588 N = UnusedArgNodeMap[Address];
4591 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4592 Address = BCI->getOperand(0);
4593 // Parameters are handled specially.
4595 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4596 isa<Argument>(Address));
4598 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4600 if (isParameter && !AI) {
4601 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4603 // Byval parameter. We have a frame index at this point.
4604 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4605 0, dl, SDNodeOrder);
4607 // Address is an argument, so try to emit its dbg value using
4608 // virtual register info from the FuncInfo.ValueMap.
4609 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4613 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4614 0, dl, SDNodeOrder);
4616 // Can't do anything with other non-AI cases yet.
4617 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4618 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4619 DEBUG(Address->dump());
4622 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4624 // If Address is an argument then try to emit its dbg value using
4625 // virtual register info from the FuncInfo.ValueMap.
4626 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4627 // If variable is pinned by a alloca in dominating bb then
4628 // use StaticAllocaMap.
4629 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4630 if (AI->getParent() != DI.getParent()) {
4631 DenseMap<const AllocaInst*, int>::iterator SI =
4632 FuncInfo.StaticAllocaMap.find(AI);
4633 if (SI != FuncInfo.StaticAllocaMap.end()) {
4634 SDV = DAG.getDbgValue(Variable, SI->second,
4635 0, dl, SDNodeOrder);
4636 DAG.AddDbgValue(SDV, 0, false);
4641 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4646 case Intrinsic::dbg_value: {
4647 const DbgValueInst &DI = cast<DbgValueInst>(I);
4648 if (!DIVariable(DI.getVariable()).Verify())
4651 MDNode *Variable = DI.getVariable();
4652 uint64_t Offset = DI.getOffset();
4653 const Value *V = DI.getValue();
4657 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4658 // but do not always have a corresponding SDNode built. The SDNodeOrder
4659 // absolute, but not relative, values are different depending on whether
4660 // debug info exists.
4663 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4664 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4665 DAG.AddDbgValue(SDV, 0, false);
4667 // Do not use getValue() in here; we don't want to generate code at
4668 // this point if it hasn't been done yet.
4669 SDValue N = NodeMap[V];
4670 if (!N.getNode() && isa<Argument>(V))
4671 // Check unused arguments map.
4672 N = UnusedArgNodeMap[V];
4674 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4675 SDV = DAG.getDbgValue(Variable, N.getNode(),
4676 N.getResNo(), Offset, dl, SDNodeOrder);
4677 DAG.AddDbgValue(SDV, N.getNode(), false);
4679 } else if (!V->use_empty() ) {
4680 // Do not call getValue(V) yet, as we don't want to generate code.
4681 // Remember it for later.
4682 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4683 DanglingDebugInfoMap[V] = DDI;
4685 // We may expand this to cover more cases. One case where we have no
4686 // data available is an unreferenced parameter.
4687 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4691 // Build a debug info table entry.
4692 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4693 V = BCI->getOperand(0);
4694 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4695 // Don't handle byval struct arguments or VLAs, for example.
4697 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4698 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4701 DenseMap<const AllocaInst*, int>::iterator SI =
4702 FuncInfo.StaticAllocaMap.find(AI);
4703 if (SI == FuncInfo.StaticAllocaMap.end())
4705 int FI = SI->second;
4707 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4708 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4709 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4713 case Intrinsic::eh_typeid_for: {
4714 // Find the type id for the given typeinfo.
4715 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4716 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4717 Res = DAG.getConstant(TypeID, MVT::i32);
4722 case Intrinsic::eh_return_i32:
4723 case Intrinsic::eh_return_i64:
4724 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4725 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4728 getValue(I.getArgOperand(0)),
4729 getValue(I.getArgOperand(1))));
4731 case Intrinsic::eh_unwind_init:
4732 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4734 case Intrinsic::eh_dwarf_cfa: {
4735 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4736 TLI.getPointerTy());
4737 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4739 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4740 TLI.getPointerTy()),
4742 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4744 DAG.getConstant(0, TLI.getPointerTy()));
4745 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4749 case Intrinsic::eh_sjlj_callsite: {
4750 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4751 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4752 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4753 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4755 MMI.setCurrentCallSite(CI->getZExtValue());
4758 case Intrinsic::eh_sjlj_functioncontext: {
4759 // Get and store the index of the function context.
4760 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4762 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4763 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4764 MFI->setFunctionContextIndex(FI);
4767 case Intrinsic::eh_sjlj_setjmp: {
4770 Ops[1] = getValue(I.getArgOperand(0));
4771 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl,
4772 DAG.getVTList(MVT::i32, MVT::Other),
4774 setValue(&I, Op.getValue(0));
4775 DAG.setRoot(Op.getValue(1));
4778 case Intrinsic::eh_sjlj_longjmp: {
4779 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4780 getRoot(), getValue(I.getArgOperand(0))));
4784 case Intrinsic::x86_mmx_pslli_w:
4785 case Intrinsic::x86_mmx_pslli_d:
4786 case Intrinsic::x86_mmx_pslli_q:
4787 case Intrinsic::x86_mmx_psrli_w:
4788 case Intrinsic::x86_mmx_psrli_d:
4789 case Intrinsic::x86_mmx_psrli_q:
4790 case Intrinsic::x86_mmx_psrai_w:
4791 case Intrinsic::x86_mmx_psrai_d: {
4792 SDValue ShAmt = getValue(I.getArgOperand(1));
4793 if (isa<ConstantSDNode>(ShAmt)) {
4794 visitTargetIntrinsic(I, Intrinsic);
4797 unsigned NewIntrinsic = 0;
4798 EVT ShAmtVT = MVT::v2i32;
4799 switch (Intrinsic) {
4800 case Intrinsic::x86_mmx_pslli_w:
4801 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4803 case Intrinsic::x86_mmx_pslli_d:
4804 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4806 case Intrinsic::x86_mmx_pslli_q:
4807 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4809 case Intrinsic::x86_mmx_psrli_w:
4810 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4812 case Intrinsic::x86_mmx_psrli_d:
4813 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4815 case Intrinsic::x86_mmx_psrli_q:
4816 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4818 case Intrinsic::x86_mmx_psrai_w:
4819 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4821 case Intrinsic::x86_mmx_psrai_d:
4822 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4824 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4827 // The vector shift intrinsics with scalars uses 32b shift amounts but
4828 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4830 // We must do this early because v2i32 is not a legal type.
4831 DebugLoc dl = getCurDebugLoc();
4834 ShOps[1] = DAG.getConstant(0, MVT::i32);
4835 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4836 EVT DestVT = TLI.getValueType(I.getType());
4837 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4838 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4839 DAG.getConstant(NewIntrinsic, MVT::i32),
4840 getValue(I.getArgOperand(0)), ShAmt);
4844 case Intrinsic::x86_avx_vinsertf128_pd_256:
4845 case Intrinsic::x86_avx_vinsertf128_ps_256:
4846 case Intrinsic::x86_avx_vinsertf128_si_256:
4847 case Intrinsic::x86_avx2_vinserti128: {
4848 DebugLoc dl = getCurDebugLoc();
4849 EVT DestVT = TLI.getValueType(I.getType());
4850 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
4851 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4852 ElVT.getVectorNumElements();
4853 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT,
4854 getValue(I.getArgOperand(0)),
4855 getValue(I.getArgOperand(1)),
4856 DAG.getConstant(Idx, MVT::i32));
4860 case Intrinsic::convertff:
4861 case Intrinsic::convertfsi:
4862 case Intrinsic::convertfui:
4863 case Intrinsic::convertsif:
4864 case Intrinsic::convertuif:
4865 case Intrinsic::convertss:
4866 case Intrinsic::convertsu:
4867 case Intrinsic::convertus:
4868 case Intrinsic::convertuu: {
4869 ISD::CvtCode Code = ISD::CVT_INVALID;
4870 switch (Intrinsic) {
4871 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4872 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4873 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4874 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4875 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4876 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4877 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4878 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4879 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4880 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4882 EVT DestVT = TLI.getValueType(I.getType());
4883 const Value *Op1 = I.getArgOperand(0);
4884 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4885 DAG.getValueType(DestVT),
4886 DAG.getValueType(getValue(Op1).getValueType()),
4887 getValue(I.getArgOperand(1)),
4888 getValue(I.getArgOperand(2)),
4893 case Intrinsic::sqrt:
4894 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4895 getValue(I.getArgOperand(0)).getValueType(),
4896 getValue(I.getArgOperand(0))));
4898 case Intrinsic::powi:
4899 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4900 getValue(I.getArgOperand(1)), DAG));
4902 case Intrinsic::sin:
4903 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4904 getValue(I.getArgOperand(0)).getValueType(),
4905 getValue(I.getArgOperand(0))));
4907 case Intrinsic::cos:
4908 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4909 getValue(I.getArgOperand(0)).getValueType(),
4910 getValue(I.getArgOperand(0))));
4912 case Intrinsic::log:
4915 case Intrinsic::log2:
4918 case Intrinsic::log10:
4921 case Intrinsic::exp:
4924 case Intrinsic::exp2:
4927 case Intrinsic::pow:
4930 case Intrinsic::fabs:
4931 setValue(&I, DAG.getNode(ISD::FABS, dl,
4932 getValue(I.getArgOperand(0)).getValueType(),
4933 getValue(I.getArgOperand(0))));
4935 case Intrinsic::floor:
4936 setValue(&I, DAG.getNode(ISD::FFLOOR, dl,
4937 getValue(I.getArgOperand(0)).getValueType(),
4938 getValue(I.getArgOperand(0))));
4940 case Intrinsic::fma:
4941 setValue(&I, DAG.getNode(ISD::FMA, dl,
4942 getValue(I.getArgOperand(0)).getValueType(),
4943 getValue(I.getArgOperand(0)),
4944 getValue(I.getArgOperand(1)),
4945 getValue(I.getArgOperand(2))));
4947 case Intrinsic::fmuladd: {
4948 EVT VT = TLI.getValueType(I.getType());
4949 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4950 TLI.isOperationLegal(ISD::FMA, VT) &&
4951 TLI.isFMAFasterThanMulAndAdd(VT)){
4952 setValue(&I, DAG.getNode(ISD::FMA, dl,
4953 getValue(I.getArgOperand(0)).getValueType(),
4954 getValue(I.getArgOperand(0)),
4955 getValue(I.getArgOperand(1)),
4956 getValue(I.getArgOperand(2))));
4958 SDValue Mul = DAG.getNode(ISD::FMUL, dl,
4959 getValue(I.getArgOperand(0)).getValueType(),
4960 getValue(I.getArgOperand(0)),
4961 getValue(I.getArgOperand(1)));
4962 SDValue Add = DAG.getNode(ISD::FADD, dl,
4963 getValue(I.getArgOperand(0)).getValueType(),
4965 getValue(I.getArgOperand(2)));
4970 case Intrinsic::convert_to_fp16:
4971 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4972 MVT::i16, getValue(I.getArgOperand(0))));
4974 case Intrinsic::convert_from_fp16:
4975 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4976 MVT::f32, getValue(I.getArgOperand(0))));
4978 case Intrinsic::pcmarker: {
4979 SDValue Tmp = getValue(I.getArgOperand(0));
4980 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4983 case Intrinsic::readcyclecounter: {
4984 SDValue Op = getRoot();
4985 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4986 DAG.getVTList(MVT::i64, MVT::Other),
4989 DAG.setRoot(Res.getValue(1));
4992 case Intrinsic::bswap:
4993 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4994 getValue(I.getArgOperand(0)).getValueType(),
4995 getValue(I.getArgOperand(0))));
4997 case Intrinsic::cttz: {
4998 SDValue Arg = getValue(I.getArgOperand(0));
4999 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5000 EVT Ty = Arg.getValueType();
5001 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5005 case Intrinsic::ctlz: {
5006 SDValue Arg = getValue(I.getArgOperand(0));
5007 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5008 EVT Ty = Arg.getValueType();
5009 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5013 case Intrinsic::ctpop: {
5014 SDValue Arg = getValue(I.getArgOperand(0));
5015 EVT Ty = Arg.getValueType();
5016 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
5019 case Intrinsic::stacksave: {
5020 SDValue Op = getRoot();
5021 Res = DAG.getNode(ISD::STACKSAVE, dl,
5022 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
5024 DAG.setRoot(Res.getValue(1));
5027 case Intrinsic::stackrestore: {
5028 Res = getValue(I.getArgOperand(0));
5029 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
5032 case Intrinsic::stackprotector: {
5033 // Emit code into the DAG to store the stack guard onto the stack.
5034 MachineFunction &MF = DAG.getMachineFunction();
5035 MachineFrameInfo *MFI = MF.getFrameInfo();
5036 EVT PtrTy = TLI.getPointerTy();
5038 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
5039 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5041 int FI = FuncInfo.StaticAllocaMap[Slot];
5042 MFI->setStackProtectorIndex(FI);
5044 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5046 // Store the stack protector onto the stack.
5047 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
5048 MachinePointerInfo::getFixedStack(FI),
5054 case Intrinsic::objectsize: {
5055 // If we don't know by now, we're never going to know.
5056 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5058 assert(CI && "Non-constant type in __builtin_object_size?");
5060 SDValue Arg = getValue(I.getCalledValue());
5061 EVT Ty = Arg.getValueType();
5064 Res = DAG.getConstant(-1ULL, Ty);
5066 Res = DAG.getConstant(0, Ty);
5071 case Intrinsic::var_annotation:
5072 // Discard annotate attributes
5075 case Intrinsic::init_trampoline: {
5076 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5080 Ops[1] = getValue(I.getArgOperand(0));
5081 Ops[2] = getValue(I.getArgOperand(1));
5082 Ops[3] = getValue(I.getArgOperand(2));
5083 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5084 Ops[5] = DAG.getSrcValue(F);
5086 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6);
5091 case Intrinsic::adjust_trampoline: {
5092 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl,
5094 getValue(I.getArgOperand(0))));
5097 case Intrinsic::gcroot:
5099 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5100 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5102 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5103 GFI->addStackRoot(FI->getIndex(), TypeMap);
5106 case Intrinsic::gcread:
5107 case Intrinsic::gcwrite:
5108 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5109 case Intrinsic::flt_rounds:
5110 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
5113 case Intrinsic::expect: {
5114 // Just replace __builtin_expect(exp, c) with EXP.
5115 setValue(&I, getValue(I.getArgOperand(0)));
5119 case Intrinsic::trap: {
5120 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5121 if (TrapFuncName.empty()) {
5122 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
5125 TargetLowering::ArgListTy Args;
5127 CallLoweringInfo CLI(getRoot(), I.getType(),
5128 false, false, false, false, 0, CallingConv::C,
5129 /*isTailCall=*/false,
5130 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5131 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5132 Args, DAG, getCurDebugLoc());
5133 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5134 DAG.setRoot(Result.second);
5137 case Intrinsic::debugtrap: {
5138 DAG.setRoot(DAG.getNode(ISD::DEBUGTRAP, dl,MVT::Other, getRoot()));
5141 case Intrinsic::uadd_with_overflow:
5142 case Intrinsic::sadd_with_overflow:
5143 case Intrinsic::usub_with_overflow:
5144 case Intrinsic::ssub_with_overflow:
5145 case Intrinsic::umul_with_overflow:
5146 case Intrinsic::smul_with_overflow: {
5148 switch (Intrinsic) {
5149 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5150 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5151 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5152 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5153 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5154 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5155 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5157 SDValue Op1 = getValue(I.getArgOperand(0));
5158 SDValue Op2 = getValue(I.getArgOperand(1));
5160 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5161 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
5164 case Intrinsic::prefetch: {
5166 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5168 Ops[1] = getValue(I.getArgOperand(0));
5169 Ops[2] = getValue(I.getArgOperand(1));
5170 Ops[3] = getValue(I.getArgOperand(2));
5171 Ops[4] = getValue(I.getArgOperand(3));
5172 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
5173 DAG.getVTList(MVT::Other),
5175 EVT::getIntegerVT(*Context, 8),
5176 MachinePointerInfo(I.getArgOperand(0)),
5178 false, /* volatile */
5180 rw==1)); /* write */
5184 case Intrinsic::invariant_start:
5185 case Intrinsic::lifetime_start:
5186 // Discard region information.
5187 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5189 case Intrinsic::invariant_end:
5190 case Intrinsic::lifetime_end:
5191 // Discard region information.
5193 case Intrinsic::donothing:
5199 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5201 MachineBasicBlock *LandingPad) {
5202 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5203 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5204 Type *RetTy = FTy->getReturnType();
5205 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5206 MCSymbol *BeginLabel = 0;
5208 TargetLowering::ArgListTy Args;
5209 TargetLowering::ArgListEntry Entry;
5210 Args.reserve(CS.arg_size());
5212 // Check whether the function can return without sret-demotion.
5213 SmallVector<ISD::OutputArg, 4> Outs;
5214 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
5217 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
5218 DAG.getMachineFunction(),
5219 FTy->isVarArg(), Outs,
5222 SDValue DemoteStackSlot;
5223 int DemoteStackIdx = -100;
5225 if (!CanLowerReturn) {
5226 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
5227 FTy->getReturnType());
5228 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
5229 FTy->getReturnType());
5230 MachineFunction &MF = DAG.getMachineFunction();
5231 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5232 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5234 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
5235 Entry.Node = DemoteStackSlot;
5236 Entry.Ty = StackSlotPtrType;
5237 Entry.isSExt = false;
5238 Entry.isZExt = false;
5239 Entry.isInReg = false;
5240 Entry.isSRet = true;
5241 Entry.isNest = false;
5242 Entry.isByVal = false;
5243 Entry.Alignment = Align;
5244 Args.push_back(Entry);
5245 RetTy = Type::getVoidTy(FTy->getContext());
5248 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5250 const Value *V = *i;
5253 if (V->getType()->isEmptyTy())
5256 SDValue ArgNode = getValue(V);
5257 Entry.Node = ArgNode; Entry.Ty = V->getType();
5259 unsigned attrInd = i - CS.arg_begin() + 1;
5260 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
5261 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
5262 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5263 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
5264 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
5265 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
5266 Entry.Alignment = CS.getParamAlignment(attrInd);
5267 Args.push_back(Entry);
5271 // Insert a label before the invoke call to mark the try range. This can be
5272 // used to detect deletion of the invoke via the MachineModuleInfo.
5273 BeginLabel = MMI.getContext().CreateTempSymbol();
5275 // For SjLj, keep track of which landing pads go with which invokes
5276 // so as to maintain the ordering of pads in the LSDA.
5277 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5278 if (CallSiteIndex) {
5279 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5280 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5282 // Now that the call site is handled, stop tracking it.
5283 MMI.setCurrentCallSite(0);
5286 // Both PendingLoads and PendingExports must be flushed here;
5287 // this call might not return.
5289 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
5292 // Check if target-independent constraints permit a tail call here.
5293 // Target-dependent constraints are checked within TLI.LowerCallTo.
5295 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
5298 // If there's a possibility that fast-isel has already selected some amount
5299 // of the current basic block, don't emit a tail call.
5300 if (isTailCall && TM.Options.EnableFastISel)
5304 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
5305 getCurDebugLoc(), CS);
5306 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI);
5307 assert((isTailCall || Result.second.getNode()) &&
5308 "Non-null chain expected with non-tail call!");
5309 assert((Result.second.getNode() || !Result.first.getNode()) &&
5310 "Null value expected with tail call!");
5311 if (Result.first.getNode()) {
5312 setValue(CS.getInstruction(), Result.first);
5313 } else if (!CanLowerReturn && Result.second.getNode()) {
5314 // The instruction result is the result of loading from the
5315 // hidden sret parameter.
5316 SmallVector<EVT, 1> PVTs;
5317 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5319 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5320 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5321 EVT PtrVT = PVTs[0];
5323 SmallVector<EVT, 4> RetTys;
5324 SmallVector<uint64_t, 4> Offsets;
5325 RetTy = FTy->getReturnType();
5326 ComputeValueVTs(TLI, RetTy, RetTys, &Offsets);
5328 unsigned NumValues = RetTys.size();
5329 SmallVector<SDValue, 4> Values(NumValues);
5330 SmallVector<SDValue, 4> Chains(NumValues);
5332 for (unsigned i = 0; i < NumValues; ++i) {
5333 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5335 DAG.getConstant(Offsets[i], PtrVT));
5336 SDValue L = DAG.getLoad(RetTys[i], getCurDebugLoc(), Result.second, Add,
5337 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5338 false, false, false, 1);
5340 Chains[i] = L.getValue(1);
5343 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5344 MVT::Other, &Chains[0], NumValues);
5345 PendingLoads.push_back(Chain);
5347 setValue(CS.getInstruction(),
5348 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
5349 DAG.getVTList(&RetTys[0], RetTys.size()),
5350 &Values[0], Values.size()));
5353 // Assign order to nodes here. If the call does not produce a result, it won't
5354 // be mapped to a SDNode and visit() will not assign it an order number.
5355 if (!Result.second.getNode()) {
5356 // As a special case, a null chain means that a tail call has been emitted and
5357 // the DAG root is already updated.
5360 AssignOrderingToNode(DAG.getRoot().getNode());
5362 DAG.setRoot(Result.second);
5364 AssignOrderingToNode(Result.second.getNode());
5368 // Insert a label at the end of the invoke call to mark the try range. This
5369 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5370 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5371 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5373 // Inform MachineModuleInfo of range.
5374 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5378 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5379 /// value is equal or not-equal to zero.
5380 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5381 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5383 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5384 if (IC->isEquality())
5385 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5386 if (C->isNullValue())
5388 // Unknown instruction.
5394 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5396 SelectionDAGBuilder &Builder) {
5398 // Check to see if this load can be trivially constant folded, e.g. if the
5399 // input is from a string literal.
5400 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5401 // Cast pointer to the type we really want to load.
5402 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5403 PointerType::getUnqual(LoadTy));
5405 if (const Constant *LoadCst =
5406 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5408 return Builder.getValue(LoadCst);
5411 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5412 // still constant memory, the input chain can be the entry node.
5414 bool ConstantMemory = false;
5416 // Do not serialize (non-volatile) loads of constant memory with anything.
5417 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5418 Root = Builder.DAG.getEntryNode();
5419 ConstantMemory = true;
5421 // Do not serialize non-volatile loads against each other.
5422 Root = Builder.DAG.getRoot();
5425 SDValue Ptr = Builder.getValue(PtrVal);
5426 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5427 Ptr, MachinePointerInfo(PtrVal),
5429 false /*nontemporal*/,
5430 false /*isinvariant*/, 1 /* align=1 */);
5432 if (!ConstantMemory)
5433 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5438 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5439 /// If so, return true and lower it, otherwise return false and it will be
5440 /// lowered like a normal call.
5441 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5442 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5443 if (I.getNumArgOperands() != 3)
5446 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5447 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5448 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5449 !I.getType()->isIntegerTy())
5452 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5454 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5455 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5456 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5457 bool ActuallyDoIt = true;
5460 switch (Size->getZExtValue()) {
5462 LoadVT = MVT::Other;
5464 ActuallyDoIt = false;
5468 LoadTy = Type::getInt16Ty(Size->getContext());
5472 LoadTy = Type::getInt32Ty(Size->getContext());
5476 LoadTy = Type::getInt64Ty(Size->getContext());
5480 LoadVT = MVT::v4i32;
5481 LoadTy = Type::getInt32Ty(Size->getContext());
5482 LoadTy = VectorType::get(LoadTy, 4);
5487 // This turns into unaligned loads. We only do this if the target natively
5488 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5489 // we'll only produce a small number of byte loads.
5491 // Require that we can find a legal MVT, and only do this if the target
5492 // supports unaligned loads of that type. Expanding into byte loads would
5494 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5495 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5496 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5497 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5498 ActuallyDoIt = false;
5502 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5503 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5505 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5507 EVT CallVT = TLI.getValueType(I.getType(), true);
5508 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5517 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5518 /// operation (as expected), translate it to an SDNode with the specified opcode
5519 /// and return true.
5520 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5522 // Sanity check that it really is a unary floating-point call.
5523 if (I.getNumArgOperands() != 1 ||
5524 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5525 I.getType() != I.getArgOperand(0)->getType() ||
5526 !I.onlyReadsMemory())
5529 SDValue Tmp = getValue(I.getArgOperand(0));
5530 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), Tmp.getValueType(), Tmp));
5534 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5535 // Handle inline assembly differently.
5536 if (isa<InlineAsm>(I.getCalledValue())) {
5541 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5542 ComputeUsesVAFloatArgument(I, &MMI);
5544 const char *RenameFn = 0;
5545 if (Function *F = I.getCalledFunction()) {
5546 if (F->isDeclaration()) {
5547 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5548 if (unsigned IID = II->getIntrinsicID(F)) {
5549 RenameFn = visitIntrinsicCall(I, IID);
5554 if (unsigned IID = F->getIntrinsicID()) {
5555 RenameFn = visitIntrinsicCall(I, IID);
5561 // Check for well-known libc/libm calls. If the function is internal, it
5562 // can't be a library call.
5564 if (!F->hasLocalLinkage() && F->hasName() &&
5565 LibInfo->getLibFunc(F->getName(), Func) &&
5566 LibInfo->hasOptimizedCodeGen(Func)) {
5569 case LibFunc::copysign:
5570 case LibFunc::copysignf:
5571 case LibFunc::copysignl:
5572 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5573 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5574 I.getType() == I.getArgOperand(0)->getType() &&
5575 I.getType() == I.getArgOperand(1)->getType() &&
5576 I.onlyReadsMemory()) {
5577 SDValue LHS = getValue(I.getArgOperand(0));
5578 SDValue RHS = getValue(I.getArgOperand(1));
5579 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5580 LHS.getValueType(), LHS, RHS));
5585 case LibFunc::fabsf:
5586 case LibFunc::fabsl:
5587 if (visitUnaryFloatCall(I, ISD::FABS))
5593 if (visitUnaryFloatCall(I, ISD::FSIN))
5599 if (visitUnaryFloatCall(I, ISD::FCOS))
5603 case LibFunc::sqrtf:
5604 case LibFunc::sqrtl:
5605 if (visitUnaryFloatCall(I, ISD::FSQRT))
5608 case LibFunc::floor:
5609 case LibFunc::floorf:
5610 case LibFunc::floorl:
5611 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5614 case LibFunc::nearbyint:
5615 case LibFunc::nearbyintf:
5616 case LibFunc::nearbyintl:
5617 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5621 case LibFunc::ceilf:
5622 case LibFunc::ceill:
5623 if (visitUnaryFloatCall(I, ISD::FCEIL))
5627 case LibFunc::rintf:
5628 case LibFunc::rintl:
5629 if (visitUnaryFloatCall(I, ISD::FRINT))
5632 case LibFunc::trunc:
5633 case LibFunc::truncf:
5634 case LibFunc::truncl:
5635 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5639 case LibFunc::log2f:
5640 case LibFunc::log2l:
5641 if (visitUnaryFloatCall(I, ISD::FLOG2))
5645 case LibFunc::exp2f:
5646 case LibFunc::exp2l:
5647 if (visitUnaryFloatCall(I, ISD::FEXP2))
5650 case LibFunc::memcmp:
5651 if (visitMemCmpCall(I))
5660 Callee = getValue(I.getCalledValue());
5662 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5664 // Check if we can potentially perform a tail call. More detailed checking is
5665 // be done within LowerCallTo, after more information about the call is known.
5666 LowerCallTo(&I, Callee, I.isTailCall());
5671 /// AsmOperandInfo - This contains information for each constraint that we are
5673 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5675 /// CallOperand - If this is the result output operand or a clobber
5676 /// this is null, otherwise it is the incoming operand to the CallInst.
5677 /// This gets modified as the asm is processed.
5678 SDValue CallOperand;
5680 /// AssignedRegs - If this is a register or register class operand, this
5681 /// contains the set of register corresponding to the operand.
5682 RegsForValue AssignedRegs;
5684 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5685 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5688 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5689 /// corresponds to. If there is no Value* for this operand, it returns
5691 EVT getCallOperandValEVT(LLVMContext &Context,
5692 const TargetLowering &TLI,
5693 const TargetData *TD) const {
5694 if (CallOperandVal == 0) return MVT::Other;
5696 if (isa<BasicBlock>(CallOperandVal))
5697 return TLI.getPointerTy();
5699 llvm::Type *OpTy = CallOperandVal->getType();
5701 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5702 // If this is an indirect operand, the operand is a pointer to the
5705 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5707 report_fatal_error("Indirect operand for inline asm not a pointer!");
5708 OpTy = PtrTy->getElementType();
5711 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5712 if (StructType *STy = dyn_cast<StructType>(OpTy))
5713 if (STy->getNumElements() == 1)
5714 OpTy = STy->getElementType(0);
5716 // If OpTy is not a single value, it may be a struct/union that we
5717 // can tile with integers.
5718 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5719 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5728 OpTy = IntegerType::get(Context, BitSize);
5733 return TLI.getValueType(OpTy, true);
5737 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5739 } // end anonymous namespace
5741 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5742 /// specified operand. We prefer to assign virtual registers, to allow the
5743 /// register allocator to handle the assignment process. However, if the asm
5744 /// uses features that we can't model on machineinstrs, we have SDISel do the
5745 /// allocation. This produces generally horrible, but correct, code.
5747 /// OpInfo describes the operand.
5749 static void GetRegistersForValue(SelectionDAG &DAG,
5750 const TargetLowering &TLI,
5752 SDISelAsmOperandInfo &OpInfo) {
5753 LLVMContext &Context = *DAG.getContext();
5755 MachineFunction &MF = DAG.getMachineFunction();
5756 SmallVector<unsigned, 4> Regs;
5758 // If this is a constraint for a single physreg, or a constraint for a
5759 // register class, find it.
5760 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5761 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5762 OpInfo.ConstraintVT);
5764 unsigned NumRegs = 1;
5765 if (OpInfo.ConstraintVT != MVT::Other) {
5766 // If this is a FP input in an integer register (or visa versa) insert a bit
5767 // cast of the input value. More generally, handle any case where the input
5768 // value disagrees with the register class we plan to stick this in.
5769 if (OpInfo.Type == InlineAsm::isInput &&
5770 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5771 // Try to convert to the first EVT that the reg class contains. If the
5772 // types are identical size, use a bitcast to convert (e.g. two differing
5774 EVT RegVT = *PhysReg.second->vt_begin();
5775 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5776 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5777 RegVT, OpInfo.CallOperand);
5778 OpInfo.ConstraintVT = RegVT;
5779 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5780 // If the input is a FP value and we want it in FP registers, do a
5781 // bitcast to the corresponding integer type. This turns an f64 value
5782 // into i64, which can be passed with two i32 values on a 32-bit
5784 RegVT = EVT::getIntegerVT(Context,
5785 OpInfo.ConstraintVT.getSizeInBits());
5786 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5787 RegVT, OpInfo.CallOperand);
5788 OpInfo.ConstraintVT = RegVT;
5792 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5796 EVT ValueVT = OpInfo.ConstraintVT;
5798 // If this is a constraint for a specific physical register, like {r17},
5800 if (unsigned AssignedReg = PhysReg.first) {
5801 const TargetRegisterClass *RC = PhysReg.second;
5802 if (OpInfo.ConstraintVT == MVT::Other)
5803 ValueVT = *RC->vt_begin();
5805 // Get the actual register value type. This is important, because the user
5806 // may have asked for (e.g.) the AX register in i32 type. We need to
5807 // remember that AX is actually i16 to get the right extension.
5808 RegVT = *RC->vt_begin();
5810 // This is a explicit reference to a physical register.
5811 Regs.push_back(AssignedReg);
5813 // If this is an expanded reference, add the rest of the regs to Regs.
5815 TargetRegisterClass::iterator I = RC->begin();
5816 for (; *I != AssignedReg; ++I)
5817 assert(I != RC->end() && "Didn't find reg!");
5819 // Already added the first reg.
5821 for (; NumRegs; --NumRegs, ++I) {
5822 assert(I != RC->end() && "Ran out of registers to allocate!");
5827 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5831 // Otherwise, if this was a reference to an LLVM register class, create vregs
5832 // for this reference.
5833 if (const TargetRegisterClass *RC = PhysReg.second) {
5834 RegVT = *RC->vt_begin();
5835 if (OpInfo.ConstraintVT == MVT::Other)
5838 // Create the appropriate number of virtual registers.
5839 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5840 for (; NumRegs; --NumRegs)
5841 Regs.push_back(RegInfo.createVirtualRegister(RC));
5843 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5847 // Otherwise, we couldn't allocate enough registers for this.
5850 /// visitInlineAsm - Handle a call to an InlineAsm object.
5852 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5853 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5855 /// ConstraintOperands - Information about all of the constraints.
5856 SDISelAsmOperandInfoVector ConstraintOperands;
5858 TargetLowering::AsmOperandInfoVector
5859 TargetConstraints = TLI.ParseConstraints(CS);
5861 bool hasMemory = false;
5863 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5864 unsigned ResNo = 0; // ResNo - The result number of the next output.
5865 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5866 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5867 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5869 EVT OpVT = MVT::Other;
5871 // Compute the value type for each operand.
5872 switch (OpInfo.Type) {
5873 case InlineAsm::isOutput:
5874 // Indirect outputs just consume an argument.
5875 if (OpInfo.isIndirect) {
5876 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5880 // The return value of the call is this value. As such, there is no
5881 // corresponding argument.
5882 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5883 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5884 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5886 assert(ResNo == 0 && "Asm only has one result!");
5887 OpVT = TLI.getValueType(CS.getType());
5891 case InlineAsm::isInput:
5892 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5894 case InlineAsm::isClobber:
5899 // If this is an input or an indirect output, process the call argument.
5900 // BasicBlocks are labels, currently appearing only in asm's.
5901 if (OpInfo.CallOperandVal) {
5902 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5903 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5905 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5908 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5911 OpInfo.ConstraintVT = OpVT;
5913 // Indirect operand accesses access memory.
5914 if (OpInfo.isIndirect)
5917 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5918 TargetLowering::ConstraintType
5919 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5920 if (CType == TargetLowering::C_Memory) {
5928 SDValue Chain, Flag;
5930 // We won't need to flush pending loads if this asm doesn't touch
5931 // memory and is nonvolatile.
5932 if (hasMemory || IA->hasSideEffects())
5935 Chain = DAG.getRoot();
5937 // Second pass over the constraints: compute which constraint option to use
5938 // and assign registers to constraints that want a specific physreg.
5939 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5940 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5942 // If this is an output operand with a matching input operand, look up the
5943 // matching input. If their types mismatch, e.g. one is an integer, the
5944 // other is floating point, or their sizes are different, flag it as an
5946 if (OpInfo.hasMatchingInput()) {
5947 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5949 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5950 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5951 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5952 OpInfo.ConstraintVT);
5953 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5954 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
5955 Input.ConstraintVT);
5956 if ((OpInfo.ConstraintVT.isInteger() !=
5957 Input.ConstraintVT.isInteger()) ||
5958 (MatchRC.second != InputRC.second)) {
5959 report_fatal_error("Unsupported asm: input constraint"
5960 " with a matching output constraint of"
5961 " incompatible type!");
5963 Input.ConstraintVT = OpInfo.ConstraintVT;
5967 // Compute the constraint code and ConstraintType to use.
5968 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5970 // If this is a memory input, and if the operand is not indirect, do what we
5971 // need to to provide an address for the memory input.
5972 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5973 !OpInfo.isIndirect) {
5974 assert((OpInfo.isMultipleAlternative ||
5975 (OpInfo.Type == InlineAsm::isInput)) &&
5976 "Can only indirectify direct input operands!");
5978 // Memory operands really want the address of the value. If we don't have
5979 // an indirect input, put it in the constpool if we can, otherwise spill
5980 // it to a stack slot.
5981 // TODO: This isn't quite right. We need to handle these according to
5982 // the addressing mode that the constraint wants. Also, this may take
5983 // an additional register for the computation and we don't want that
5986 // If the operand is a float, integer, or vector constant, spill to a
5987 // constant pool entry to get its address.
5988 const Value *OpVal = OpInfo.CallOperandVal;
5989 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5990 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5991 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5992 TLI.getPointerTy());
5994 // Otherwise, create a stack slot and emit a store to it before the
5996 Type *Ty = OpVal->getType();
5997 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5998 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5999 MachineFunction &MF = DAG.getMachineFunction();
6000 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6001 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6002 Chain = DAG.getStore(Chain, getCurDebugLoc(),
6003 OpInfo.CallOperand, StackSlot,
6004 MachinePointerInfo::getFixedStack(SSFI),
6006 OpInfo.CallOperand = StackSlot;
6009 // There is no longer a Value* corresponding to this operand.
6010 OpInfo.CallOperandVal = 0;
6012 // It is now an indirect operand.
6013 OpInfo.isIndirect = true;
6016 // If this constraint is for a specific register, allocate it before
6018 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6019 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6022 // Second pass - Loop over all of the operands, assigning virtual or physregs
6023 // to register class operands.
6024 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6025 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6027 // C_Register operands have already been allocated, Other/Memory don't need
6029 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6030 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6033 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6034 std::vector<SDValue> AsmNodeOperands;
6035 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6036 AsmNodeOperands.push_back(
6037 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6038 TLI.getPointerTy()));
6040 // If we have a !srcloc metadata node associated with it, we want to attach
6041 // this to the ultimately generated inline asm machineinstr. To do this, we
6042 // pass in the third operand as this (potentially null) inline asm MDNode.
6043 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6044 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6046 // Remember the HasSideEffect and AlignStack bits as operand 3.
6047 unsigned ExtraInfo = 0;
6048 if (IA->hasSideEffects())
6049 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6050 if (IA->isAlignStack())
6051 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6052 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6053 TLI.getPointerTy()));
6055 // Loop over all of the inputs, copying the operand values into the
6056 // appropriate registers and processing the output regs.
6057 RegsForValue RetValRegs;
6059 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6060 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6062 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6063 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6065 switch (OpInfo.Type) {
6066 case InlineAsm::isOutput: {
6067 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6068 OpInfo.ConstraintType != TargetLowering::C_Register) {
6069 // Memory output, or 'other' output (e.g. 'X' constraint).
6070 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6072 // Add information to the INLINEASM node to know about this output.
6073 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6074 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6075 TLI.getPointerTy()));
6076 AsmNodeOperands.push_back(OpInfo.CallOperand);
6080 // Otherwise, this is a register or register class output.
6082 // Copy the output from the appropriate register. Find a register that
6084 if (OpInfo.AssignedRegs.Regs.empty()) {
6085 LLVMContext &Ctx = *DAG.getContext();
6086 Ctx.emitError(CS.getInstruction(),
6087 "couldn't allocate output register for constraint '" +
6088 Twine(OpInfo.ConstraintCode) + "'");
6092 // If this is an indirect operand, store through the pointer after the
6094 if (OpInfo.isIndirect) {
6095 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6096 OpInfo.CallOperandVal));
6098 // This is the result value of the call.
6099 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6100 // Concatenate this output onto the outputs list.
6101 RetValRegs.append(OpInfo.AssignedRegs);
6104 // Add information to the INLINEASM node to know that this register is
6106 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6107 InlineAsm::Kind_RegDefEarlyClobber :
6108 InlineAsm::Kind_RegDef,
6115 case InlineAsm::isInput: {
6116 SDValue InOperandVal = OpInfo.CallOperand;
6118 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6119 // If this is required to match an output register we have already set,
6120 // just use its register.
6121 unsigned OperandNo = OpInfo.getMatchedOperand();
6123 // Scan until we find the definition we already emitted of this operand.
6124 // When we find it, create a RegsForValue operand.
6125 unsigned CurOp = InlineAsm::Op_FirstOperand;
6126 for (; OperandNo; --OperandNo) {
6127 // Advance to the next operand.
6129 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6130 assert((InlineAsm::isRegDefKind(OpFlag) ||
6131 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6132 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6133 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6137 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6138 if (InlineAsm::isRegDefKind(OpFlag) ||
6139 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6140 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6141 if (OpInfo.isIndirect) {
6142 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6143 LLVMContext &Ctx = *DAG.getContext();
6144 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6145 " don't know how to handle tied "
6146 "indirect register inputs");
6149 RegsForValue MatchedRegs;
6150 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6151 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
6152 MatchedRegs.RegVTs.push_back(RegVT);
6153 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6154 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6156 MatchedRegs.Regs.push_back
6157 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
6159 // Use the produced MatchedRegs object to
6160 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6162 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6163 true, OpInfo.getMatchedOperand(),
6164 DAG, AsmNodeOperands);
6168 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6169 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6170 "Unexpected number of operands");
6171 // Add information to the INLINEASM node to know about this input.
6172 // See InlineAsm.h isUseOperandTiedToDef.
6173 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6174 OpInfo.getMatchedOperand());
6175 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6176 TLI.getPointerTy()));
6177 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6181 // Treat indirect 'X' constraint as memory.
6182 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6184 OpInfo.ConstraintType = TargetLowering::C_Memory;
6186 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6187 std::vector<SDValue> Ops;
6188 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6191 LLVMContext &Ctx = *DAG.getContext();
6192 Ctx.emitError(CS.getInstruction(),
6193 "invalid operand for inline asm constraint '" +
6194 Twine(OpInfo.ConstraintCode) + "'");
6198 // Add information to the INLINEASM node to know about this input.
6199 unsigned ResOpType =
6200 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6201 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6202 TLI.getPointerTy()));
6203 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6207 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6208 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6209 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6210 "Memory operands expect pointer values");
6212 // Add information to the INLINEASM node to know about this input.
6213 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6214 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6215 TLI.getPointerTy()));
6216 AsmNodeOperands.push_back(InOperandVal);
6220 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6221 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6222 "Unknown constraint type!");
6224 // TODO: Support this.
6225 if (OpInfo.isIndirect) {
6226 LLVMContext &Ctx = *DAG.getContext();
6227 Ctx.emitError(CS.getInstruction(),
6228 "Don't know how to handle indirect register inputs yet "
6229 "for constraint '" + Twine(OpInfo.ConstraintCode) + "'");
6233 // Copy the input into the appropriate registers.
6234 if (OpInfo.AssignedRegs.Regs.empty()) {
6235 LLVMContext &Ctx = *DAG.getContext();
6236 Ctx.emitError(CS.getInstruction(),
6237 "couldn't allocate input reg for constraint '" +
6238 Twine(OpInfo.ConstraintCode) + "'");
6242 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6245 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6246 DAG, AsmNodeOperands);
6249 case InlineAsm::isClobber: {
6250 // Add the clobbered value to the operand list, so that the register
6251 // allocator is aware that the physreg got clobbered.
6252 if (!OpInfo.AssignedRegs.Regs.empty())
6253 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6261 // Finish up input operands. Set the input chain and add the flag last.
6262 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6263 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6265 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6266 DAG.getVTList(MVT::Other, MVT::Glue),
6267 &AsmNodeOperands[0], AsmNodeOperands.size());
6268 Flag = Chain.getValue(1);
6270 // If this asm returns a register value, copy the result from that register
6271 // and set it as the value of the call.
6272 if (!RetValRegs.Regs.empty()) {
6273 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6276 // FIXME: Why don't we do this for inline asms with MRVs?
6277 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6278 EVT ResultType = TLI.getValueType(CS.getType());
6280 // If any of the results of the inline asm is a vector, it may have the
6281 // wrong width/num elts. This can happen for register classes that can
6282 // contain multiple different value types. The preg or vreg allocated may
6283 // not have the same VT as was expected. Convert it to the right type
6284 // with bit_convert.
6285 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6286 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6289 } else if (ResultType != Val.getValueType() &&
6290 ResultType.isInteger() && Val.getValueType().isInteger()) {
6291 // If a result value was tied to an input value, the computed result may
6292 // have a wider width than the expected result. Extract the relevant
6294 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6297 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6300 setValue(CS.getInstruction(), Val);
6301 // Don't need to use this as a chain in this case.
6302 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6306 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6308 // Process indirect outputs, first output all of the flagged copies out of
6310 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6311 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6312 const Value *Ptr = IndirectStoresToEmit[i].second;
6313 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6315 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6318 // Emit the non-flagged stores from the physregs.
6319 SmallVector<SDValue, 8> OutChains;
6320 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6321 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6322 StoresToEmit[i].first,
6323 getValue(StoresToEmit[i].second),
6324 MachinePointerInfo(StoresToEmit[i].second),
6326 OutChains.push_back(Val);
6329 if (!OutChains.empty())
6330 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6331 &OutChains[0], OutChains.size());
6336 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6337 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6338 MVT::Other, getRoot(),
6339 getValue(I.getArgOperand(0)),
6340 DAG.getSrcValue(I.getArgOperand(0))));
6343 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6344 const TargetData &TD = *TLI.getTargetData();
6345 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6346 getRoot(), getValue(I.getOperand(0)),
6347 DAG.getSrcValue(I.getOperand(0)),
6348 TD.getABITypeAlignment(I.getType()));
6350 DAG.setRoot(V.getValue(1));
6353 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6354 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6355 MVT::Other, getRoot(),
6356 getValue(I.getArgOperand(0)),
6357 DAG.getSrcValue(I.getArgOperand(0))));
6360 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6361 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6362 MVT::Other, getRoot(),
6363 getValue(I.getArgOperand(0)),
6364 getValue(I.getArgOperand(1)),
6365 DAG.getSrcValue(I.getArgOperand(0)),
6366 DAG.getSrcValue(I.getArgOperand(1))));
6369 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6370 /// implementation, which just calls LowerCall.
6371 /// FIXME: When all targets are
6372 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6373 std::pair<SDValue, SDValue>
6374 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6375 // Handle all of the outgoing arguments.
6377 CLI.OutVals.clear();
6378 ArgListTy &Args = CLI.Args;
6379 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6380 SmallVector<EVT, 4> ValueVTs;
6381 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6382 for (unsigned Value = 0, NumValues = ValueVTs.size();
6383 Value != NumValues; ++Value) {
6384 EVT VT = ValueVTs[Value];
6385 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6386 SDValue Op = SDValue(Args[i].Node.getNode(),
6387 Args[i].Node.getResNo() + Value);
6388 ISD::ArgFlagsTy Flags;
6389 unsigned OriginalAlignment =
6390 getTargetData()->getABITypeAlignment(ArgTy);
6396 if (Args[i].isInReg)
6400 if (Args[i].isByVal) {
6402 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6403 Type *ElementTy = Ty->getElementType();
6404 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy));
6405 // For ByVal, alignment should come from FE. BE will guess if this
6406 // info is not there but there are cases it cannot get right.
6407 unsigned FrameAlign;
6408 if (Args[i].Alignment)
6409 FrameAlign = Args[i].Alignment;
6411 FrameAlign = getByValTypeAlignment(ElementTy);
6412 Flags.setByValAlign(FrameAlign);
6416 Flags.setOrigAlign(OriginalAlignment);
6418 EVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6419 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6420 SmallVector<SDValue, 4> Parts(NumParts);
6421 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6424 ExtendKind = ISD::SIGN_EXTEND;
6425 else if (Args[i].isZExt)
6426 ExtendKind = ISD::ZERO_EXTEND;
6428 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts,
6429 PartVT, ExtendKind);
6431 for (unsigned j = 0; j != NumParts; ++j) {
6432 // if it isn't first piece, alignment must be 1
6433 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6434 i < CLI.NumFixedArgs);
6435 if (NumParts > 1 && j == 0)
6436 MyFlags.Flags.setSplit();
6438 MyFlags.Flags.setOrigAlign(1);
6440 CLI.Outs.push_back(MyFlags);
6441 CLI.OutVals.push_back(Parts[j]);
6446 // Handle the incoming return values from the call.
6448 SmallVector<EVT, 4> RetTys;
6449 ComputeValueVTs(*this, CLI.RetTy, RetTys);
6450 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6452 EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6453 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6454 for (unsigned i = 0; i != NumRegs; ++i) {
6455 ISD::InputArg MyFlags;
6456 MyFlags.VT = RegisterVT.getSimpleVT();
6457 MyFlags.Used = CLI.IsReturnValueUsed;
6459 MyFlags.Flags.setSExt();
6461 MyFlags.Flags.setZExt();
6463 MyFlags.Flags.setInReg();
6464 CLI.Ins.push_back(MyFlags);
6468 SmallVector<SDValue, 4> InVals;
6469 CLI.Chain = LowerCall(CLI, InVals);
6471 // Verify that the target's LowerCall behaved as expected.
6472 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6473 "LowerCall didn't return a valid chain!");
6474 assert((!CLI.IsTailCall || InVals.empty()) &&
6475 "LowerCall emitted a return value for a tail call!");
6476 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6477 "LowerCall didn't emit the correct number of values!");
6479 // For a tail call, the return value is merely live-out and there aren't
6480 // any nodes in the DAG representing it. Return a special value to
6481 // indicate that a tail call has been emitted and no more Instructions
6482 // should be processed in the current block.
6483 if (CLI.IsTailCall) {
6484 CLI.DAG.setRoot(CLI.Chain);
6485 return std::make_pair(SDValue(), SDValue());
6488 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6489 assert(InVals[i].getNode() &&
6490 "LowerCall emitted a null value!");
6491 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6492 "LowerCall emitted a value with the wrong type!");
6495 // Collect the legal value parts into potentially illegal values
6496 // that correspond to the original function's return values.
6497 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6499 AssertOp = ISD::AssertSext;
6500 else if (CLI.RetZExt)
6501 AssertOp = ISD::AssertZext;
6502 SmallVector<SDValue, 4> ReturnValues;
6503 unsigned CurReg = 0;
6504 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6506 EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6507 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6509 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6510 NumRegs, RegisterVT, VT,
6515 // For a function returning void, there is no return value. We can't create
6516 // such a node, so we just return a null return value in that case. In
6517 // that case, nothing will actually look at the value.
6518 if (ReturnValues.empty())
6519 return std::make_pair(SDValue(), CLI.Chain);
6521 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6522 CLI.DAG.getVTList(&RetTys[0], RetTys.size()),
6523 &ReturnValues[0], ReturnValues.size());
6524 return std::make_pair(Res, CLI.Chain);
6527 void TargetLowering::LowerOperationWrapper(SDNode *N,
6528 SmallVectorImpl<SDValue> &Results,
6529 SelectionDAG &DAG) const {
6530 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6532 Results.push_back(Res);
6535 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6536 llvm_unreachable("LowerOperation not implemented for this target!");
6540 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6541 SDValue Op = getNonRegisterValue(V);
6542 assert((Op.getOpcode() != ISD::CopyFromReg ||
6543 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6544 "Copy from a reg to the same reg!");
6545 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6547 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6548 SDValue Chain = DAG.getEntryNode();
6549 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6550 PendingExports.push_back(Chain);
6553 #include "llvm/CodeGen/SelectionDAGISel.h"
6555 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6556 /// entry block, return true. This includes arguments used by switches, since
6557 /// the switch may expand into multiple basic blocks.
6558 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6559 // With FastISel active, we may be splitting blocks, so force creation
6560 // of virtual registers for all non-dead arguments.
6562 return A->use_empty();
6564 const BasicBlock *Entry = A->getParent()->begin();
6565 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6567 const User *U = *UI;
6568 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6569 return false; // Use not in entry block.
6574 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6575 // If this is the entry block, emit arguments.
6576 const Function &F = *LLVMBB->getParent();
6577 SelectionDAG &DAG = SDB->DAG;
6578 DebugLoc dl = SDB->getCurDebugLoc();
6579 const TargetData *TD = TLI.getTargetData();
6580 SmallVector<ISD::InputArg, 16> Ins;
6582 // Check whether the function can return without sret-demotion.
6583 SmallVector<ISD::OutputArg, 4> Outs;
6584 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6587 if (!FuncInfo->CanLowerReturn) {
6588 // Put in an sret pointer parameter before all the other parameters.
6589 SmallVector<EVT, 1> ValueVTs;
6590 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6592 // NOTE: Assuming that a pointer will never break down to more than one VT
6594 ISD::ArgFlagsTy Flags;
6596 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6597 ISD::InputArg RetArg(Flags, RegisterVT, true);
6598 Ins.push_back(RetArg);
6601 // Set up the incoming argument description vector.
6603 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6604 I != E; ++I, ++Idx) {
6605 SmallVector<EVT, 4> ValueVTs;
6606 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6607 bool isArgValueUsed = !I->use_empty();
6608 for (unsigned Value = 0, NumValues = ValueVTs.size();
6609 Value != NumValues; ++Value) {
6610 EVT VT = ValueVTs[Value];
6611 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6612 ISD::ArgFlagsTy Flags;
6613 unsigned OriginalAlignment =
6614 TD->getABITypeAlignment(ArgTy);
6616 if (F.paramHasAttr(Idx, Attribute::ZExt))
6618 if (F.paramHasAttr(Idx, Attribute::SExt))
6620 if (F.paramHasAttr(Idx, Attribute::InReg))
6622 if (F.paramHasAttr(Idx, Attribute::StructRet))
6624 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6626 PointerType *Ty = cast<PointerType>(I->getType());
6627 Type *ElementTy = Ty->getElementType();
6628 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6629 // For ByVal, alignment should be passed from FE. BE will guess if
6630 // this info is not there but there are cases it cannot get right.
6631 unsigned FrameAlign;
6632 if (F.getParamAlignment(Idx))
6633 FrameAlign = F.getParamAlignment(Idx);
6635 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6636 Flags.setByValAlign(FrameAlign);
6638 if (F.paramHasAttr(Idx, Attribute::Nest))
6640 Flags.setOrigAlign(OriginalAlignment);
6642 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6643 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6644 for (unsigned i = 0; i != NumRegs; ++i) {
6645 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6646 if (NumRegs > 1 && i == 0)
6647 MyFlags.Flags.setSplit();
6648 // if it isn't first piece, alignment must be 1
6650 MyFlags.Flags.setOrigAlign(1);
6651 Ins.push_back(MyFlags);
6656 // Call the target to set up the argument values.
6657 SmallVector<SDValue, 8> InVals;
6658 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6662 // Verify that the target's LowerFormalArguments behaved as expected.
6663 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6664 "LowerFormalArguments didn't return a valid chain!");
6665 assert(InVals.size() == Ins.size() &&
6666 "LowerFormalArguments didn't emit the correct number of values!");
6668 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6669 assert(InVals[i].getNode() &&
6670 "LowerFormalArguments emitted a null value!");
6671 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6672 "LowerFormalArguments emitted a value with the wrong type!");
6676 // Update the DAG with the new chain value resulting from argument lowering.
6677 DAG.setRoot(NewRoot);
6679 // Set up the argument values.
6682 if (!FuncInfo->CanLowerReturn) {
6683 // Create a virtual register for the sret pointer, and put in a copy
6684 // from the sret argument into it.
6685 SmallVector<EVT, 1> ValueVTs;
6686 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6687 EVT VT = ValueVTs[0];
6688 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6689 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6690 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6691 RegVT, VT, AssertOp);
6693 MachineFunction& MF = SDB->DAG.getMachineFunction();
6694 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6695 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6696 FuncInfo->DemoteRegister = SRetReg;
6697 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6699 DAG.setRoot(NewRoot);
6701 // i indexes lowered arguments. Bump it past the hidden sret argument.
6702 // Idx indexes LLVM arguments. Don't touch it.
6706 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6708 SmallVector<SDValue, 4> ArgValues;
6709 SmallVector<EVT, 4> ValueVTs;
6710 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6711 unsigned NumValues = ValueVTs.size();
6713 // If this argument is unused then remember its value. It is used to generate
6714 // debugging information.
6715 if (I->use_empty() && NumValues)
6716 SDB->setUnusedArgValue(I, InVals[i]);
6718 for (unsigned Val = 0; Val != NumValues; ++Val) {
6719 EVT VT = ValueVTs[Val];
6720 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6721 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6723 if (!I->use_empty()) {
6724 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6725 if (F.paramHasAttr(Idx, Attribute::SExt))
6726 AssertOp = ISD::AssertSext;
6727 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6728 AssertOp = ISD::AssertZext;
6730 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6731 NumParts, PartVT, VT,
6738 // We don't need to do anything else for unused arguments.
6739 if (ArgValues.empty())
6742 // Note down frame index.
6743 if (FrameIndexSDNode *FI =
6744 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6745 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6747 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6748 SDB->getCurDebugLoc());
6750 SDB->setValue(I, Res);
6751 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6752 if (LoadSDNode *LNode =
6753 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
6754 if (FrameIndexSDNode *FI =
6755 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6756 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6759 // If this argument is live outside of the entry block, insert a copy from
6760 // wherever we got it to the vreg that other BB's will reference it as.
6761 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6762 // If we can, though, try to skip creating an unnecessary vreg.
6763 // FIXME: This isn't very clean... it would be nice to make this more
6764 // general. It's also subtly incompatible with the hacks FastISel
6766 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6767 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6768 FuncInfo->ValueMap[I] = Reg;
6772 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
6773 FuncInfo->InitializeRegForValue(I);
6774 SDB->CopyToExportRegsIfNeeded(I);
6778 assert(i == InVals.size() && "Argument register count mismatch!");
6780 // Finally, if the target has anything special to do, allow it to do so.
6781 // FIXME: this should insert code into the DAG!
6782 EmitFunctionEntryCode();
6785 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6786 /// ensure constants are generated when needed. Remember the virtual registers
6787 /// that need to be added to the Machine PHI nodes as input. We cannot just
6788 /// directly add them, because expansion might result in multiple MBB's for one
6789 /// BB. As such, the start of the BB might correspond to a different MBB than
6793 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6794 const TerminatorInst *TI = LLVMBB->getTerminator();
6796 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6798 // Check successor nodes' PHI nodes that expect a constant to be available
6800 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6801 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6802 if (!isa<PHINode>(SuccBB->begin())) continue;
6803 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6805 // If this terminator has multiple identical successors (common for
6806 // switches), only handle each succ once.
6807 if (!SuccsHandled.insert(SuccMBB)) continue;
6809 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6811 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6812 // nodes and Machine PHI nodes, but the incoming operands have not been
6814 for (BasicBlock::const_iterator I = SuccBB->begin();
6815 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6816 // Ignore dead phi's.
6817 if (PN->use_empty()) continue;
6820 if (PN->getType()->isEmptyTy())
6824 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6826 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6827 unsigned &RegOut = ConstantsOut[C];
6829 RegOut = FuncInfo.CreateRegs(C->getType());
6830 CopyValueToVirtualRegister(C, RegOut);
6834 DenseMap<const Value *, unsigned>::iterator I =
6835 FuncInfo.ValueMap.find(PHIOp);
6836 if (I != FuncInfo.ValueMap.end())
6839 assert(isa<AllocaInst>(PHIOp) &&
6840 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6841 "Didn't codegen value into a register!??");
6842 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6843 CopyValueToVirtualRegister(PHIOp, Reg);
6847 // Remember that this register needs to added to the machine PHI node as
6848 // the input for this MBB.
6849 SmallVector<EVT, 4> ValueVTs;
6850 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6851 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6852 EVT VT = ValueVTs[vti];
6853 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6854 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6855 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6856 Reg += NumRegisters;
6860 ConstantsOut.clear();