1 //===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAG class, which is a base class used by
11 // scheduling implementation classes.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "pre-RA-sched"
16 #include "SDNodeDbgValue.h"
17 #include "ScheduleDAGSDNodes.h"
18 #include "InstrEmitter.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Target/TargetSubtarget.h"
25 #include "llvm/ADT/DenseMap.h"
26 #include "llvm/ADT/SmallPtrSet.h"
27 #include "llvm/ADT/SmallSet.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/raw_ostream.h"
34 STATISTIC(LoadsClustered, "Number of loads clustered together");
36 ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
40 /// Run - perform scheduling.
42 void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb,
43 MachineBasicBlock::iterator insertPos) {
45 ScheduleDAG::Run(bb, insertPos);
48 /// NewSUnit - Creates a new SUnit and return a ptr to it.
50 SUnit *ScheduleDAGSDNodes::NewSUnit(SDNode *N) {
52 const SUnit *Addr = 0;
56 SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
57 assert((Addr == 0 || Addr == &SUnits[0]) &&
58 "SUnits std::vector reallocated on the fly!");
59 SUnits.back().OrigNode = &SUnits.back();
60 SUnit *SU = &SUnits.back();
61 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
62 if (N->isMachineOpcode() &&
63 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)
64 SU->SchedulingPref = Sched::None;
66 SU->SchedulingPref = TLI.getSchedulingPreference(N);
70 SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
71 SUnit *SU = NewSUnit(Old->getNode());
72 SU->OrigNode = Old->OrigNode;
73 SU->Latency = Old->Latency;
74 SU->isTwoAddress = Old->isTwoAddress;
75 SU->isCommutable = Old->isCommutable;
76 SU->hasPhysRegDefs = Old->hasPhysRegDefs;
77 SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
78 SU->SchedulingPref = Old->SchedulingPref;
83 /// CheckForPhysRegDependency - Check if the dependency between def and use of
84 /// a specified operand is a physical register dependency. If so, returns the
85 /// register and the cost of copying the register.
86 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
87 const TargetRegisterInfo *TRI,
88 const TargetInstrInfo *TII,
89 unsigned &PhysReg, int &Cost) {
90 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
93 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
94 if (TargetRegisterInfo::isVirtualRegister(Reg))
97 unsigned ResNo = User->getOperand(2).getResNo();
98 if (Def->isMachineOpcode()) {
99 const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
100 if (ResNo >= II.getNumDefs() &&
101 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
103 const TargetRegisterClass *RC =
104 TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo));
105 Cost = RC->getCopyCost();
110 static void AddFlags(SDNode *N, SDValue Flag, bool AddFlag,
112 SmallVector<EVT, 4> VTs;
113 SDNode *FlagDestNode = Flag.getNode();
115 // Don't add a flag from a node to itself.
116 if (FlagDestNode == N) return;
118 // Don't add a flag to something which already has a flag.
119 if (N->getValueType(N->getNumValues() - 1) == MVT::Flag) return;
121 for (unsigned I = 0, E = N->getNumValues(); I != E; ++I)
122 VTs.push_back(N->getValueType(I));
125 VTs.push_back(MVT::Flag);
127 SmallVector<SDValue, 4> Ops;
128 for (unsigned I = 0, E = N->getNumOperands(); I != E; ++I)
129 Ops.push_back(N->getOperand(I));
134 SDVTList VTList = DAG->getVTList(&VTs[0], VTs.size());
135 MachineSDNode::mmo_iterator Begin = 0, End = 0;
136 MachineSDNode *MN = dyn_cast<MachineSDNode>(N);
138 // Store memory references.
140 Begin = MN->memoperands_begin();
141 End = MN->memoperands_end();
144 DAG->MorphNodeTo(N, N->getOpcode(), VTList, &Ops[0], Ops.size());
146 // Reset the memory references
148 MN->setMemRefs(Begin, End);
151 /// ClusterNeighboringLoads - Force nearby loads together by "flagging" them.
152 /// This function finds loads of the same base and different offsets. If the
153 /// offsets are not far apart (target specific), it add MVT::Flag inputs and
154 /// outputs to ensure they are scheduled together and in order. This
155 /// optimization may benefit some targets by improving cache locality.
156 void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
158 unsigned NumOps = Node->getNumOperands();
159 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
160 Chain = Node->getOperand(NumOps-1).getNode();
164 // Look for other loads of the same chain. Find loads that are loading from
165 // the same base pointer and different offsets.
166 SmallPtrSet<SDNode*, 16> Visited;
167 SmallVector<int64_t, 4> Offsets;
168 DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode.
169 bool Cluster = false;
172 for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
175 if (User == Node || !Visited.insert(User))
177 int64_t Offset1, Offset2;
178 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
180 // FIXME: Should be ok if they addresses are identical. But earlier
181 // optimizations really should have eliminated one of the loads.
183 if (O2SMap.insert(std::make_pair(Offset1, Base)).second)
184 Offsets.push_back(Offset1);
185 O2SMap.insert(std::make_pair(Offset2, User));
186 Offsets.push_back(Offset2);
187 if (Offset2 < Offset1) {
189 BaseOffset = Offset2;
191 BaseOffset = Offset1;
199 // Sort them in increasing order.
200 std::sort(Offsets.begin(), Offsets.end());
202 // Check if the loads are close enough.
203 SmallVector<SDNode*, 4> Loads;
204 unsigned NumLoads = 0;
205 int64_t BaseOff = Offsets[0];
206 SDNode *BaseLoad = O2SMap[BaseOff];
207 Loads.push_back(BaseLoad);
208 for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {
209 int64_t Offset = Offsets[i];
210 SDNode *Load = O2SMap[Offset];
211 if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
212 break; // Stop right here. Ignore loads that are further away.
213 Loads.push_back(Load);
220 // Cluster loads by adding MVT::Flag outputs and inputs. This also
221 // ensure they are scheduled in order of increasing addresses.
222 SDNode *Lead = Loads[0];
223 AddFlags(Lead, SDValue(0, 0), true, DAG);
225 SDValue InFlag = SDValue(Lead, Lead->getNumValues() - 1);
226 for (unsigned I = 1, E = Loads.size(); I != E; ++I) {
227 bool OutFlag = I < E - 1;
228 SDNode *Load = Loads[I];
230 AddFlags(Load, InFlag, OutFlag, DAG);
233 InFlag = SDValue(Load, Load->getNumValues() - 1);
239 /// ClusterNodes - Cluster certain nodes which should be scheduled together.
241 void ScheduleDAGSDNodes::ClusterNodes() {
242 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
243 E = DAG->allnodes_end(); NI != E; ++NI) {
245 if (!Node || !Node->isMachineOpcode())
248 unsigned Opc = Node->getMachineOpcode();
249 const TargetInstrDesc &TID = TII->get(Opc);
251 // Cluster loads from "near" addresses into combined SUnits.
252 ClusterNeighboringLoads(Node);
256 void ScheduleDAGSDNodes::BuildSchedUnits() {
257 // During scheduling, the NodeId field of SDNode is used to map SDNodes
258 // to their associated SUnits by holding SUnits table indices. A value
259 // of -1 means the SDNode does not yet have an associated SUnit.
260 unsigned NumNodes = 0;
261 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
262 E = DAG->allnodes_end(); NI != E; ++NI) {
267 // Reserve entries in the vector for each of the SUnits we are creating. This
268 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
270 // FIXME: Multiply by 2 because we may clone nodes during scheduling.
271 // This is a temporary workaround.
272 SUnits.reserve(NumNodes * 2);
274 // Add all nodes in depth first order.
275 SmallVector<SDNode*, 64> Worklist;
276 SmallPtrSet<SDNode*, 64> Visited;
277 Worklist.push_back(DAG->getRoot().getNode());
278 Visited.insert(DAG->getRoot().getNode());
280 while (!Worklist.empty()) {
281 SDNode *NI = Worklist.pop_back_val();
283 // Add all operands to the worklist unless they've already been added.
284 for (unsigned i = 0, e = NI->getNumOperands(); i != e; ++i)
285 if (Visited.insert(NI->getOperand(i).getNode()))
286 Worklist.push_back(NI->getOperand(i).getNode());
288 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
291 // If this node has already been processed, stop now.
292 if (NI->getNodeId() != -1) continue;
294 SUnit *NodeSUnit = NewSUnit(NI);
296 // See if anything is flagged to this node, if so, add them to flagged
297 // nodes. Nodes can have at most one flag input and one flag output. Flags
298 // are required to be the last operand and result of a node.
300 // Scan up to find flagged preds.
302 while (N->getNumOperands() &&
303 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
304 N = N->getOperand(N->getNumOperands()-1).getNode();
305 assert(N->getNodeId() == -1 && "Node already inserted!");
306 N->setNodeId(NodeSUnit->NodeNum);
309 // Scan down to find any flagged succs.
311 while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
312 SDValue FlagVal(N, N->getNumValues()-1);
314 // There are either zero or one users of the Flag result.
315 bool HasFlagUse = false;
316 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
318 if (FlagVal.isOperandOf(*UI)) {
320 assert(N->getNodeId() == -1 && "Node already inserted!");
321 N->setNodeId(NodeSUnit->NodeNum);
325 if (!HasFlagUse) break;
328 // If there are flag operands involved, N is now the bottom-most node
329 // of the sequence of nodes that are flagged together.
331 NodeSUnit->setNode(N);
332 assert(N->getNodeId() == -1 && "Node already inserted!");
333 N->setNodeId(NodeSUnit->NodeNum);
335 // Assign the Latency field of NodeSUnit using target-provided information.
336 ComputeLatency(NodeSUnit);
340 void ScheduleDAGSDNodes::AddSchedEdges() {
341 const TargetSubtarget &ST = TM.getSubtarget<TargetSubtarget>();
343 // Check to see if the scheduler cares about latencies.
344 bool UnitLatencies = ForceUnitLatencies();
346 // Pass 2: add the preds, succs, etc.
347 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
348 SUnit *SU = &SUnits[su];
349 SDNode *MainNode = SU->getNode();
351 if (MainNode->isMachineOpcode()) {
352 unsigned Opc = MainNode->getMachineOpcode();
353 const TargetInstrDesc &TID = TII->get(Opc);
354 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
355 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
356 SU->isTwoAddress = true;
360 if (TID.isCommutable())
361 SU->isCommutable = true;
364 // Find all predecessors and successors of the group.
365 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
366 if (N->isMachineOpcode() &&
367 TII->get(N->getMachineOpcode()).getImplicitDefs()) {
368 SU->hasPhysRegClobbers = true;
369 unsigned NumUsed = InstrEmitter::CountResults(N);
370 while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
371 --NumUsed; // Skip over unused values at the end.
372 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
373 SU->hasPhysRegDefs = true;
376 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
377 SDNode *OpN = N->getOperand(i).getNode();
378 if (isPassiveNode(OpN)) continue; // Not scheduled.
379 SUnit *OpSU = &SUnits[OpN->getNodeId()];
380 assert(OpSU && "Node has no SUnit!");
381 if (OpSU == SU) continue; // In the same group.
383 EVT OpVT = N->getOperand(i).getValueType();
384 assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
385 bool isChain = OpVT == MVT::Other;
387 unsigned PhysReg = 0;
389 // Determine if this is a physical register dependency.
390 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
391 assert((PhysReg == 0 || !isChain) &&
392 "Chain dependence via physreg data?");
393 // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
394 // emits a copy from the physical register to a virtual register unless
395 // it requires a cross class copy (cost < 0). That means we are only
396 // treating "expensive to copy" register dependency as physical register
397 // dependency. This may change in the future though.
401 // If this is a ctrl dep, latency is 1.
402 unsigned OpLatency = isChain ? 1 : OpSU->Latency;
403 const SDep &dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data,
405 if (!isChain && !UnitLatencies) {
406 ComputeOperandLatency(OpN, N, i, const_cast<SDep &>(dep));
407 ST.adjustSchedDependency(OpSU, SU, const_cast<SDep &>(dep));
416 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
417 /// are input. This SUnit graph is similar to the SelectionDAG, but
418 /// excludes nodes that aren't interesting to scheduling, and represents
419 /// flagged together nodes with a single SUnit.
420 void ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) {
421 // Cluster certain nodes which should be scheduled together.
423 // Populate the SUnits array.
425 // Compute all the scheduling dependencies between nodes.
429 void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
430 // Check to see if the scheduler cares about latencies.
431 if (ForceUnitLatencies()) {
436 const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
437 if (InstrItins.isEmpty()) {
442 // Compute the latency for the node. We use the sum of the latencies for
443 // all nodes flagged together into this SUnit.
445 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
446 if (N->isMachineOpcode()) {
447 SU->Latency += InstrItins.
448 getStageLatency(TII->get(N->getMachineOpcode()).getSchedClass());
452 void ScheduleDAGSDNodes::ComputeOperandLatency(SDNode *Def, SDNode *Use,
453 unsigned OpIdx, SDep& dep) const{
454 // Check to see if the scheduler cares about latencies.
455 if (ForceUnitLatencies())
458 const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
459 if (InstrItins.isEmpty())
462 if (dep.getKind() != SDep::Data)
465 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
466 if (Def->isMachineOpcode()) {
467 const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
468 if (DefIdx >= II.getNumDefs())
470 int DefCycle = InstrItins.getOperandCycle(II.getSchedClass(), DefIdx);
474 if (Use->isMachineOpcode()) {
475 const unsigned UseClass = TII->get(Use->getMachineOpcode()).getSchedClass();
476 UseCycle = InstrItins.getOperandCycle(UseClass, OpIdx);
479 int Latency = DefCycle - UseCycle + 1;
481 dep.setLatency(Latency);
486 void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
487 if (!SU->getNode()) {
488 dbgs() << "PHYS REG COPY\n";
492 SU->getNode()->dump(DAG);
494 SmallVector<SDNode *, 4> FlaggedNodes;
495 for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
496 FlaggedNodes.push_back(N);
497 while (!FlaggedNodes.empty()) {
499 FlaggedNodes.back()->dump(DAG);
501 FlaggedNodes.pop_back();
507 bool operator()(const std::pair<unsigned, MachineInstr*> &A,
508 const std::pair<unsigned, MachineInstr*> &B) {
509 return A.first < B.first;
514 // ProcessSourceNode - Process nodes with source order numbers. These are added
515 // to a vector which EmitSchedule use to determine how to insert dbg_value
516 // instructions in the right order.
517 static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,
518 InstrEmitter &Emitter,
519 DenseMap<SDValue, unsigned> &VRBaseMap,
520 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
521 SmallSet<unsigned, 8> &Seen) {
522 unsigned Order = DAG->GetOrdering(N);
523 if (!Order || !Seen.insert(Order))
526 MachineBasicBlock *BB = Emitter.getBlock();
527 if (BB->empty() || BB->back().isPHI()) {
528 // Did not insert any instruction.
529 Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
533 Orders.push_back(std::make_pair(Order, &BB->back()));
534 if (!N->getHasDebugValue())
536 // Opportunistically insert immediate dbg_value uses, i.e. those with source
537 // order number right after the N.
538 MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
539 SmallVector<SDDbgValue*,2> &DVs = DAG->GetDbgValues(N);
540 for (unsigned i = 0, e = DVs.size(); i != e; ++i) {
541 if (DVs[i]->isInvalidated())
543 unsigned DVOrder = DVs[i]->getOrder();
544 if (DVOrder == ++Order) {
545 MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap);
547 Orders.push_back(std::make_pair(DVOrder, DbgMI));
548 BB->insert(InsertPos, DbgMI);
550 DVs[i]->setIsInvalidated();
556 /// EmitSchedule - Emit the machine code in scheduled order.
557 MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
558 InstrEmitter Emitter(BB, InsertPos);
559 DenseMap<SDValue, unsigned> VRBaseMap;
560 DenseMap<SUnit*, unsigned> CopyVRBaseMap;
561 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
562 SmallSet<unsigned, 8> Seen;
563 bool HasDbg = DAG->hasDebugValues();
565 // If this is the first BB, emit byval parameter dbg_value's.
566 if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
567 SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin();
568 SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd();
569 for (; PDI != PDE; ++PDI) {
570 MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
572 BB->push_back(DbgMI);
576 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
577 SUnit *SU = Sequence[i];
579 // Null SUnit* is a noop.
584 // For pre-regalloc scheduling, create instructions corresponding to the
585 // SDNode and any flagged SDNodes and append them to the block.
586 if (!SU->getNode()) {
588 EmitPhysRegCopy(SU, CopyVRBaseMap);
592 SmallVector<SDNode *, 4> FlaggedNodes;
593 for (SDNode *N = SU->getNode()->getFlaggedNode(); N;
594 N = N->getFlaggedNode())
595 FlaggedNodes.push_back(N);
596 while (!FlaggedNodes.empty()) {
597 SDNode *N = FlaggedNodes.back();
598 Emitter.EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,
600 // Remember the source order of the inserted instruction.
602 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
603 FlaggedNodes.pop_back();
605 Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
607 // Remember the source order of the inserted instruction.
609 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
613 // Insert all the dbg_values which have not already been inserted in source
616 MachineBasicBlock::iterator BBBegin = BB->empty() ? BB->end() : BB->begin();
617 while (BBBegin != BB->end() && BBBegin->isPHI())
620 // Sort the source order instructions and use the order to insert debug
622 std::sort(Orders.begin(), Orders.end(), OrderSorter());
624 SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
625 SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
626 // Now emit the rest according to source order.
627 unsigned LastOrder = 0;
628 MachineInstr *LastMI = 0;
629 for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
630 unsigned Order = Orders[i].first;
631 MachineInstr *MI = Orders[i].second;
632 // Insert all SDDbgValue's whose order(s) are before "Order".
635 MachineBasicBlock *MIBB = MI->getParent();
637 unsigned LastDIOrder = 0;
640 (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
642 assert((*DI)->getOrder() >= LastDIOrder &&
643 "SDDbgValue nodes must be in source order!");
644 LastDIOrder = (*DI)->getOrder();
646 if ((*DI)->isInvalidated())
648 MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap);
651 // Insert to start of the BB (after PHIs).
652 BB->insert(BBBegin, DbgMI);
654 MachineBasicBlock::iterator Pos = MI;
655 MIBB->insert(llvm::next(Pos), DbgMI);
662 // Add trailing DbgValue's before the terminator. FIXME: May want to add
663 // some of them before one or more conditional branches?
665 MachineBasicBlock *InsertBB = Emitter.getBlock();
666 MachineBasicBlock::iterator Pos= Emitter.getBlock()->getFirstTerminator();
667 if (!(*DI)->isInvalidated()) {
668 MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, VRBaseMap);
670 InsertBB->insert(Pos, DbgMI);
676 BB = Emitter.getBlock();
677 InsertPos = Emitter.getInsertPos();