1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
14 //===----------------------------------------------------------------------===//
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/ScopedHashTable.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/RecyclingAllocator.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
31 #define DEBUG_TYPE "machine-cse"
33 STATISTIC(NumCoalesces, "Number of copies coalesced");
34 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
35 STATISTIC(NumPhysCSEs,
36 "Number of physreg referencing common subexpr eliminated");
37 STATISTIC(NumCrossBBCSEs,
38 "Number of cross-MBB physreg referencing CS eliminated");
39 STATISTIC(NumCommutes, "Number of copies coalesced after commuting");
42 class MachineCSE : public MachineFunctionPass {
43 const TargetInstrInfo *TII;
44 const TargetRegisterInfo *TRI;
46 MachineDominatorTree *DT;
47 MachineRegisterInfo *MRI;
49 static char ID; // Pass identification
50 MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) {
51 initializeMachineCSEPass(*PassRegistry::getPassRegistry());
54 bool runOnMachineFunction(MachineFunction &MF) override;
56 void getAnalysisUsage(AnalysisUsage &AU) const override {
58 MachineFunctionPass::getAnalysisUsage(AU);
59 AU.addRequired<AliasAnalysis>();
60 AU.addPreservedID(MachineLoopInfoID);
61 AU.addRequired<MachineDominatorTree>();
62 AU.addPreserved<MachineDominatorTree>();
65 void releaseMemory() override {
71 const unsigned LookAheadLimit;
72 typedef RecyclingAllocator<BumpPtrAllocator,
73 ScopedHashTableVal<MachineInstr*, unsigned> > AllocatorTy;
74 typedef ScopedHashTable<MachineInstr*, unsigned,
75 MachineInstrExpressionTrait, AllocatorTy> ScopedHTType;
76 typedef ScopedHTType::ScopeTy ScopeType;
77 DenseMap<MachineBasicBlock*, ScopeType*> ScopeMap;
79 SmallVector<MachineInstr*, 64> Exps;
82 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
83 bool isPhysDefTriviallyDead(unsigned Reg,
84 MachineBasicBlock::const_iterator I,
85 MachineBasicBlock::const_iterator E) const;
86 bool hasLivePhysRegDefUses(const MachineInstr *MI,
87 const MachineBasicBlock *MBB,
88 SmallSet<unsigned,8> &PhysRefs,
89 SmallVectorImpl<unsigned> &PhysDefs,
90 bool &PhysUseDef) const;
91 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
92 SmallSet<unsigned,8> &PhysRefs,
93 SmallVectorImpl<unsigned> &PhysDefs,
94 bool &NonLocal) const;
95 bool isCSECandidate(MachineInstr *MI);
96 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
97 MachineInstr *CSMI, MachineInstr *MI);
98 void EnterScope(MachineBasicBlock *MBB);
99 void ExitScope(MachineBasicBlock *MBB);
100 bool ProcessBlock(MachineBasicBlock *MBB);
101 void ExitScopeIfDone(MachineDomTreeNode *Node,
102 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren);
103 bool PerformCSE(MachineDomTreeNode *Node);
105 } // end anonymous namespace
107 char MachineCSE::ID = 0;
108 char &llvm::MachineCSEID = MachineCSE::ID;
109 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
110 "Machine Common Subexpression Elimination", false, false)
111 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
112 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
113 INITIALIZE_PASS_END(MachineCSE, "machine-cse",
114 "Machine Common Subexpression Elimination", false, false)
116 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
117 MachineBasicBlock *MBB) {
118 bool Changed = false;
119 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
120 MachineOperand &MO = MI->getOperand(i);
121 if (!MO.isReg() || !MO.isUse())
123 unsigned Reg = MO.getReg();
124 if (!TargetRegisterInfo::isVirtualRegister(Reg))
126 if (!MRI->hasOneNonDBGUse(Reg))
127 // Only coalesce single use copies. This ensure the copy will be
130 MachineInstr *DefMI = MRI->getVRegDef(Reg);
131 if (!DefMI->isCopy())
133 unsigned SrcReg = DefMI->getOperand(1).getReg();
134 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
136 if (DefMI->getOperand(0).getSubReg())
138 // FIXME: We should trivially coalesce subregister copies to expose CSE
139 // opportunities on instructions with truncated operands (see
140 // cse-add-with-overflow.ll). This can be done here as follows:
142 // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
144 // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
146 // The 2-addr pass has been updated to handle coalesced subregs. However,
147 // some machine-specific code still can't handle it.
148 // To handle it properly we also need a way find a constrained subregister
149 // class given a super-reg class and subreg index.
150 if (DefMI->getOperand(1).getSubReg())
152 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
153 if (!MRI->constrainRegClass(SrcReg, RC))
155 DEBUG(dbgs() << "Coalescing: " << *DefMI);
156 DEBUG(dbgs() << "*** to: " << *MI);
158 MRI->clearKillFlags(SrcReg);
159 DefMI->eraseFromParent();
168 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
169 MachineBasicBlock::const_iterator I,
170 MachineBasicBlock::const_iterator E) const {
171 unsigned LookAheadLeft = LookAheadLimit;
172 while (LookAheadLeft) {
173 // Skip over dbg_value's.
174 while (I != E && I->isDebugValue())
178 // Reached end of block, register is obviously dead.
181 bool SeenDef = false;
182 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
183 const MachineOperand &MO = I->getOperand(i);
184 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
186 if (!MO.isReg() || !MO.getReg())
188 if (!TRI->regsOverlap(MO.getReg(), Reg))
196 // See a def of Reg (or an alias) before encountering any use, it's
206 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
207 /// physical registers (except for dead defs of physical registers). It also
208 /// returns the physical register def by reference if it's the only one and the
209 /// instruction does not uses a physical register.
210 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
211 const MachineBasicBlock *MBB,
212 SmallSet<unsigned,8> &PhysRefs,
213 SmallVectorImpl<unsigned> &PhysDefs,
214 bool &PhysUseDef) const{
215 // First, add all uses to PhysRefs.
216 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
217 const MachineOperand &MO = MI->getOperand(i);
218 if (!MO.isReg() || MO.isDef())
220 unsigned Reg = MO.getReg();
223 if (TargetRegisterInfo::isVirtualRegister(Reg))
225 // Reading constant physregs is ok.
226 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
227 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
228 PhysRefs.insert(*AI);
231 // Next, collect all defs into PhysDefs. If any is already in PhysRefs
232 // (which currently contains only uses), set the PhysUseDef flag.
234 MachineBasicBlock::const_iterator I = MI; I = std::next(I);
235 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
236 const MachineOperand &MO = MI->getOperand(i);
237 if (!MO.isReg() || !MO.isDef())
239 unsigned Reg = MO.getReg();
242 if (TargetRegisterInfo::isVirtualRegister(Reg))
244 // Check against PhysRefs even if the def is "dead".
245 if (PhysRefs.count(Reg))
247 // If the def is dead, it's ok. But the def may not marked "dead". That's
248 // common since this pass is run before livevariables. We can scan
249 // forward a few instructions and check if it is obviously dead.
250 if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
251 PhysDefs.push_back(Reg);
254 // Finally, add all defs to PhysRefs as well.
255 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
256 for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI)
257 PhysRefs.insert(*AI);
259 return !PhysRefs.empty();
262 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
263 SmallSet<unsigned,8> &PhysRefs,
264 SmallVectorImpl<unsigned> &PhysDefs,
265 bool &NonLocal) const {
266 // For now conservatively returns false if the common subexpression is
267 // not in the same basic block as the given instruction. The only exception
268 // is if the common subexpression is in the sole predecessor block.
269 const MachineBasicBlock *MBB = MI->getParent();
270 const MachineBasicBlock *CSMBB = CSMI->getParent();
272 bool CrossMBB = false;
274 if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
277 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
278 if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i]))
279 // Avoid extending live range of physical registers if they are
280 //allocatable or reserved.
285 MachineBasicBlock::const_iterator I = CSMI; I = std::next(I);
286 MachineBasicBlock::const_iterator E = MI;
287 MachineBasicBlock::const_iterator EE = CSMBB->end();
288 unsigned LookAheadLeft = LookAheadLimit;
289 while (LookAheadLeft) {
290 // Skip over dbg_value's.
291 while (I != E && I != EE && I->isDebugValue())
295 assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
307 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
308 const MachineOperand &MO = I->getOperand(i);
309 // RegMasks go on instructions like calls that clobber lots of physregs.
310 // Don't attempt to CSE across such an instruction.
313 if (!MO.isReg() || !MO.isDef())
315 unsigned MOReg = MO.getReg();
316 if (TargetRegisterInfo::isVirtualRegister(MOReg))
318 if (PhysRefs.count(MOReg))
329 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
330 if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() || MI->isKill() ||
331 MI->isInlineAsm() || MI->isDebugValue())
335 if (MI->isCopyLike())
338 // Ignore stuff that we obviously can't move.
339 if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
340 MI->hasUnmodeledSideEffects())
344 // Okay, this instruction does a load. As a refinement, we allow the target
345 // to decide whether the loaded value is actually a constant. If so, we can
346 // actually use it as a load.
347 if (!MI->isInvariantLoad(AA))
348 // FIXME: we should be able to hoist loads with no other side effects if
349 // there are no other instructions which can change memory in this loop.
350 // This is a trivial form of alias analysis.
356 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
357 /// common expression that defines Reg.
358 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
359 MachineInstr *CSMI, MachineInstr *MI) {
360 // FIXME: Heuristics that works around the lack the live range splitting.
362 // If CSReg is used at all uses of Reg, CSE should not increase register
363 // pressure of CSReg.
364 bool MayIncreasePressure = true;
365 if (TargetRegisterInfo::isVirtualRegister(CSReg) &&
366 TargetRegisterInfo::isVirtualRegister(Reg)) {
367 MayIncreasePressure = false;
368 SmallPtrSet<MachineInstr*, 8> CSUses;
369 for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {
372 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
373 if (!CSUses.count(&MI)) {
374 MayIncreasePressure = true;
379 if (!MayIncreasePressure) return true;
381 // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
382 // an immediate predecessor. We don't want to increase register pressure and
383 // end up causing other computation to be spilled.
384 if (TII->isAsCheapAsAMove(MI)) {
385 MachineBasicBlock *CSBB = CSMI->getParent();
386 MachineBasicBlock *BB = MI->getParent();
387 if (CSBB != BB && !CSBB->isSuccessor(BB))
391 // Heuristics #2: If the expression doesn't not use a vr and the only use
392 // of the redundant computation are copies, do not cse.
393 bool HasVRegUse = false;
394 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
395 const MachineOperand &MO = MI->getOperand(i);
396 if (MO.isReg() && MO.isUse() &&
397 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
403 bool HasNonCopyUse = false;
404 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
406 if (!MI.isCopyLike()) {
407 HasNonCopyUse = true;
415 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
416 // it unless the defined value is already used in the BB of the new use.
418 SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
419 for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {
420 HasPHI |= MI.isPHI();
421 CSBBs.insert(MI.getParent());
426 return CSBBs.count(MI->getParent());
429 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
430 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
431 ScopeType *Scope = new ScopeType(VNT);
432 ScopeMap[MBB] = Scope;
435 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
436 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
437 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
438 assert(SI != ScopeMap.end());
443 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
444 bool Changed = false;
446 SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
447 SmallVector<unsigned, 2> ImplicitDefsToUpdate;
448 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
449 MachineInstr *MI = &*I;
452 if (!isCSECandidate(MI))
455 bool FoundCSE = VNT.count(MI);
457 // Look for trivial copy coalescing opportunities.
458 if (PerformTrivialCoalescing(MI, MBB)) {
461 // After coalescing MI itself may become a copy.
462 if (MI->isCopyLike())
464 FoundCSE = VNT.count(MI);
468 // Commute commutable instructions.
469 bool Commuted = false;
470 if (!FoundCSE && MI->isCommutable()) {
471 MachineInstr *NewMI = TII->commuteInstruction(MI);
474 FoundCSE = VNT.count(NewMI);
476 // New instruction. It doesn't need to be kept.
477 NewMI->eraseFromParent();
479 } else if (!FoundCSE)
480 // MI was changed but it didn't help, commute it back!
481 (void)TII->commuteInstruction(MI);
485 // If the instruction defines physical registers and the values *may* be
486 // used, then it's not safe to replace it with a common subexpression.
487 // It's also not safe if the instruction uses physical registers.
488 bool CrossMBBPhysDef = false;
489 SmallSet<unsigned, 8> PhysRefs;
490 SmallVector<unsigned, 2> PhysDefs;
491 bool PhysUseDef = false;
492 if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs,
493 PhysDefs, PhysUseDef)) {
496 // ... Unless the CS is local or is in the sole predecessor block
497 // and it also defines the physical register which is not clobbered
498 // in between and the physical register uses were not clobbered.
499 // This can never be the case if the instruction both uses and
500 // defines the same physical register, which was detected above.
502 unsigned CSVN = VNT.lookup(MI);
503 MachineInstr *CSMI = Exps[CSVN];
504 if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
510 VNT.insert(MI, CurrVN++);
515 // Found a common subexpression, eliminate it.
516 unsigned CSVN = VNT.lookup(MI);
517 MachineInstr *CSMI = Exps[CSVN];
518 DEBUG(dbgs() << "Examining: " << *MI);
519 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
521 // Check if it's profitable to perform this CSE.
523 unsigned NumDefs = MI->getDesc().getNumDefs() +
524 MI->getDesc().getNumImplicitDefs();
526 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
527 MachineOperand &MO = MI->getOperand(i);
528 if (!MO.isReg() || !MO.isDef())
530 unsigned OldReg = MO.getReg();
531 unsigned NewReg = CSMI->getOperand(i).getReg();
533 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
534 // we should make sure it is not dead at CSMI.
535 if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
536 ImplicitDefsToUpdate.push_back(i);
537 if (OldReg == NewReg) {
542 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
543 TargetRegisterInfo::isVirtualRegister(NewReg) &&
544 "Do not CSE physical register defs!");
546 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
547 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
552 // Don't perform CSE if the result of the old instruction cannot exist
553 // within the register class of the new instruction.
554 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
555 if (!MRI->constrainRegClass(NewReg, OldRC)) {
556 DEBUG(dbgs() << "*** Not the same register class, avoid CSE!\n");
561 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
565 // Actually perform the elimination.
567 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
568 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
569 MRI->clearKillFlags(CSEPairs[i].second);
572 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
573 // we should make sure it is not dead at CSMI.
574 for (unsigned i = 0, e = ImplicitDefsToUpdate.size(); i != e; ++i)
575 CSMI->getOperand(ImplicitDefsToUpdate[i]).setIsDead(false);
577 if (CrossMBBPhysDef) {
578 // Add physical register defs now coming in from a predecessor to MBB
580 while (!PhysDefs.empty()) {
581 unsigned LiveIn = PhysDefs.pop_back_val();
582 if (!MBB->isLiveIn(LiveIn))
583 MBB->addLiveIn(LiveIn);
588 MI->eraseFromParent();
590 if (!PhysRefs.empty())
596 VNT.insert(MI, CurrVN++);
600 ImplicitDefsToUpdate.clear();
606 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
607 /// dominator tree node if its a leaf or all of its children are done. Walk
608 /// up the dominator tree to destroy ancestors which are now done.
610 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
611 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren) {
612 if (OpenChildren[Node])
616 ExitScope(Node->getBlock());
618 // Now traverse upwards to pop ancestors whose offsprings are all done.
619 while (MachineDomTreeNode *Parent = Node->getIDom()) {
620 unsigned Left = --OpenChildren[Parent];
623 ExitScope(Parent->getBlock());
628 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
629 SmallVector<MachineDomTreeNode*, 32> Scopes;
630 SmallVector<MachineDomTreeNode*, 8> WorkList;
631 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
635 // Perform a DFS walk to determine the order of visit.
636 WorkList.push_back(Node);
638 Node = WorkList.pop_back_val();
639 Scopes.push_back(Node);
640 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
641 unsigned NumChildren = Children.size();
642 OpenChildren[Node] = NumChildren;
643 for (unsigned i = 0; i != NumChildren; ++i) {
644 MachineDomTreeNode *Child = Children[i];
645 WorkList.push_back(Child);
647 } while (!WorkList.empty());
650 bool Changed = false;
651 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
652 MachineDomTreeNode *Node = Scopes[i];
653 MachineBasicBlock *MBB = Node->getBlock();
655 Changed |= ProcessBlock(MBB);
656 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
657 ExitScopeIfDone(Node, OpenChildren);
663 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
664 if (skipOptnoneFunction(*MF.getFunction()))
667 TII = MF.getSubtarget().getInstrInfo();
668 TRI = MF.getSubtarget().getRegisterInfo();
669 MRI = &MF.getRegInfo();
670 AA = &getAnalysis<AliasAnalysis>();
671 DT = &getAnalysis<MachineDominatorTree>();
672 return PerformCSE(DT->getRootNode());