arm64: dts: rockchip: enable cdn_dp_fb node for rk3399-mid

Change-Id: I2f2dd5758f449749e5b25dc1c8bb36aa829401f3
Signed-off-by: Bin Yang <yangbin@rock-chips.com>

UPSTREAM: Bluetooth: hci_ldisc: Fix null pointer derefence in case of early data

HCI_UART_PROTO_SET flag is set before hci_uart_set_proto call. If we
receive data from tty layer during this procedure, proto pointer may
not be assigned yet, leading to null pointer dereference in rx method
hci_uart_tty_receive.

This patch fixes this issue by introducing HCI_UART_PROTO_READY flag in
order to avoid any proto operation before proto opening and assignment.

Signed-off-by: Loic Poulain <loic.poulain@intel.com>
Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
Change-Id: Ibe366f3222cbe7a093cd08aaecbc0de1004088c8
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit 84cb3df02aea4b00405521e67c4c67c2d525c364)

video: rockchip: vop: 3399: vop lite lut and edp output is 8 bit

Change-Id: Icb333d92713cba2dda14b977ea9c6a1617e88bbf
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

mfd: rk808: close rtc int when power off

Change-Id: I1f1bfe3d6c106632c45b51bec3c18361572df865
Signed-off-by: Binyuan Lan <lby@rock-chips.com>

video: rockchip: vop: 3399: update for cabc

If enable cabc function, close auto gating, because cabc and auto gating
can't enable at the same time, in addition cabc open and close will lead
to splash screen, so when close cabc, we just set stage up and down to 0.

Change-Id: Ia4561d6adafa956c26d1921caecc7eed97dd218a
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

arm64: rockchip_defconfig: enable rk_headset

Change-Id: I6644e71b9a1fc5a10a711b55fab3056c4152105c
Signed-off-by: zhangjun <zhangjun@rock-chips.com>

power: rk818 charger: fix otg supply on/off error

As we register regmap irq to manage rk818 irqs, it should
not enable/disable irq by modifying register directly. And
check otg on/off line state before setting new state.

Change-Id: I45d45d62bea05b1c489337ac7f3334fbafcd4166
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

power: rk818 charger: remove suspend and resume callback

CHG_CVTLIM_INT is default disabled yet

Change-Id: I07123ad023322e7a88a3b992988980498256b284
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

mfd: rk808: add RK818_IRQ_CHG_CVTLIM into rk818 regmap irq

Change-Id: Iae2bf8e6aa86c0fd82b6905c9f37fffe2c719479
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

clk: rockchip: rk3399: fix up the spi softrst ID

fix up the spi3 and spi5 softrst ID.

Change-Id: Ib8870ef765284e04674ce80acf0b4702ed77cebc
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

MALI: midgard: RK: not to power off all the pm cores

This is a workaround for the issue that
"400M, 500M and 600M of clk_gpu needs high vdd_gpu",
according to "6.1" of Mali Application Note
"Potential glitches on Power Domain interfaces".

Change-Id: I58daa3cf796802f073f67bacb62734516be76205
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

dt-bindings: screen-timing: Add RAYKEN RK055AUWI5003 single channel MIPI screen dts

Change-Id: I2e2e9b30bdb19be765cecd38f31e651872d03e82
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

dt-bindings: screen-timing: set h381dln01 75fps, add screen-width and screen-hight

Change-Id: I88166845112a2c17c86a44a6c43bdea4ac26347f
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

clk: rockchip: rk3399: fix up the dclk_vop1_div parents

if the dclk_vop0_div allow CLK_SET_RATE_PARENT for VPLL,
the dclk_vop1_div parent is not allowed in vpll.

Change-Id: I9973014e8ed2fcf1c351e3f62c00040677391ff7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

rk_headset: re-enable driver/headset_observe/

Change-Id: I84a05b94894b0240d8dd6fbd9ef7bc693b933da9
Signed-off-by: zhangjun <zhangjun@rock-chips.com>

arm64: dts: rk3399: add power-domain property for edp

Change-Id: Ic6df7a80cbb1572725d4b8cbb7b3074bcd28d13c
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

ARM64: dts: rk3399-android: Set ramoops_mem size to 0xf0000

Change-Id: I3c0c4a51ed2ff19e4baad17349e3e87efc43a2f6
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

ARM64: dts: rk3399-android-next: Set ramoops_mem size to 0xf0000

Change-Id: I69c2416fb07b4364f1e02fe21be351771b1b6c6b
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

drivers: iio: imu: fix initial screen offset when switch app

Change-Id: Ia65b4b5e03b712d0c69546d69ea7b4364f30b05b
Signed-off-by: lanshh <lsh@rock-chips.com>

rk_fiq_debugger: Reset and set uart to loopback mode before init

The uart may be reinitialized when resume, if uart is in busy
state, which would fail to configure the baud rate. So reset
and set uart to loopback mode can make sure uart is in idle
state.

Change-Id: I54d9ac8de1531cd06da8c223583cd2e330178eff
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

arm64: rockchip_defconfig: enable hall sensor mh248

Change-Id: Id2818a07865e114f45f57b2bb5a70bb886d7fc38
Signed-off-by: Bin Yang <yangbin@rock-chips.com>

input: sensors: hall: do not enable hall default

Change-Id: I773b1cd05b8cf5aef26035f356732b3a487fc6e0
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

usb: dwc3: unregister extcon notify if probe fail

When the pointer of hcd is NULL, dwc3 driver will probe again. In this
case the notify sync function will issue "Bad mode in Synchronous Abort
handler detected" error if the extcon notify is not unregisted before
next probe. This patch add unregister extcon notify function and
unregister extcon notify when hcd is NULL.

Change-Id: Id55ce4280518e0c7e36a64133e38189bb4a7d29e
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

input: keyboard: rk_keys: Add support for configuring adc drift value from DT

If the adc drift value is 70, some keys maybe report twice, because
the range of adc_value +/-70 is overlapping other keys' adc range.
So it is better configuring adc drift value from DT, that also can
support more keys at a adc channel. The default adc drift value is
70, if it does not get the drift value from DT.

Change-Id: I46cef235094116d4f03af5e5c0cd3a6dfe7e8b0d
Signed-off-by: David Wu <david.wu@rock-chips.com>

usb: u2phy: add support for otg function

In the case of platform designed in usb2.0 only mode, which
the dwc3 controller connect without fusb302 and type-c phy
does not work, the u2phy need to support hot plug and detect
otg mode, this patch add support of otg function in this mode.

Change-Id: I428a4f6d17d847c6114d124733e62c0a6236b94e
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

usb: dwc3: fix logical error during controller probe

The probe function of usb controller will remove hcd struct in host
or otg mode, while the hcd is alloced after xhci driver registed. So
there is a logical error if xhci driver is registed after usb
controller and it results in the pointer of hcd point to NULL. This
patch make usb controller probe again if hcd point to NULL.

Change-Id: I659f86decac59fca610b355356fc971b3a86d4be
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

mfd: fusb302: correct the wrong pointer type used in regmap_read

used unsigned int pointer that regmap_read wanted instead of unsigned char
pointer

Change-Id: I89f838144a4d27a3bf695232acc4dbbe920863bf
Signed-off-by: zain wang <wzz@rock-chips.com>

HACK: mmc: core: fix switching clk 400K to 52/200M status error

Change-Id: I56285d306e8e3a52039a7612fae666ed40117a4a
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

mmc: sdhci-of-arasan: add sdhci_arasan_voltage_switch for arasan,5.1

Per the vendor's requirement, we shouldn't do any setting for
1.8V Signaling Enable, otherwise the interaction/behaviour between
phy and controller will be undefined. Mostly it works fine if we do
that, but we still see failures. Anyway, let's fix it to meet the
vendor's requirement. The error log looks like:

 [   93.405085] mmc1: unexpected status 0x800900 after switch
 [   93.408474] mmc1: switch to bus width 1 failed
 [   93.408482] mmc1: mmc_select_hs200 failed, error -110
 [   93.408492] mmc1: error -110 during resume (card was removed?)
 [   93.408705] PM: resume of devices complete after 213.453 msecs

Change-Id: Icc5457355c3f57b84bd6073f0c4e01350bcc9ee6
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

mmc: core: changes frequency to hs_max_dtr when selecting hs400es

Per JESD84-B51 P69, Host need to change frequency to <=52MHz after
setting HS_TIMING to 0x1, and host may changes frequency to <= 200MHz
after setting HS_TIMING to 0x3. It seems there is no difference if
we don't change frequency to <= 52MHz as f_init is already less than
52MHz. But actually it does make difference. When doing compatibility
test we see failures for some eMMC devices without changing the
frequency to hs_max_dtr. And let's read the spec again, we could see
that "Host may changes frequency to 200MHz" implies that it's not
mandatory. But the "Host need to change frequency to <= 52MHz" implies
that we should do this.

Change-Id: I1dc9f5fa8dc217e033fc4b1689ca1b0204c294c0
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

mmc: core: switch to 1V8 or 1V2 for hs400es mode

When introducing hs400es, I didn't notice that we haven't
switched voltage to 1V2 or 1V8 for it. That happens to work
as the first controller claiming to support hs400es, arasan(5.1),
which is designed to only support 1V8. So the voltage is fixed to 1V8.
But it actually is wrong, and will not fit for other host controllers.
Let's fix it.

Change-Id: I982bf34b3d305123ab7debd858e60f2454123c24
Fixes: commit 81ac2af65793ecf ("mmc: core: implement enhanced strobe support")
Cc: <stable@vger.kernel.org> 4.4# +
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

mmc: core: don't try to switch block size for dual rate mode

Per spec, block size should always be 512 bytes for dual rate mode,
so any attempts to switch the block size under dual rate mode should
be neglected.

Change-Id: I6ede0d8fd6c7b8e4903a51c1c2a1b96d350bd2e2
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

UPSTREAM: ARM64: dts: rockchip: update rk3399.dtsi for emmc&phy

Change-Id: I97948c250f63423c5a7f305cfaa3a10b190f736f
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

UPSTREAM: phy: update phy-rockchip-emmc.c upstream version

Change-Id: I9f582f28492a301fb281a3dce92421abb782c822
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

UPSTREAM: mmc: update sdhci-of-arasan.c upstream version

Change-Id: I72285f9d962f7399428102db483ad3c3ed19f998
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

UPSTREAM: mmc: core: update mmc.c upstream version

Change-Id: Ie67d23ca74708467d5af01b4ca801efa5dcd2f51
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

arm64: dts: rockchip: adjust the backlight level table on rk3399 mid

Change-Id: Ia5a7ca623d4db8b4fbd32fab45d5c4b924413bee
Signed-off-by: Zhou weixin <zwx@rock-chips.com>

arm64: dts: rk3399-sapphire-excavator-edp: disable hdmi audio

due to ff8a0000.i2s can't bound to card "rockchip,hdmi" and
"rockchip,cdn-dp-fb" at the same time

Change-Id: Ie43bf882f0eacb6e87d10ba5eba0fd38dbb5462e
Signed-off-by: zhangjun <zhangjun@rock-chips.com>

ARM64: dts: rk3399-mid: update for emmc&phy

Change-Id: I4dffff1475a6e05344ef1ea4cb9bd662e32e53fc
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

ARM64: dts: rk3399-vr: update for emmc&phy

Change-Id: I59c767a37ef072132c3b81fe1029763202420593
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

usb: dwc3: fix logical errors and improve stability for rockchip platform

1. put clks err handle at the end of probe.

2. register extcon notifier after dwc3 core initialized successfully.

3. try to get extcon cable state in probe, this can avoid to
   lose the first extcon state notifier.

4. fix pm runtime handle and disable clks in remove operation

Change-Id: I0bea71206801139efb37a835b65562c051a2072e
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

UPSTREAM: regmap: fix deadlock on _regmap_raw_write() error path

Commit 815806e39bf6 ("regmap: drop cache if the bus transfer error")
added a call to regcache_drop_region() to error path in
_regmap_raw_write(). However that path runs with regmap lock taken,
and regcache_drop_region() tries to re-take it, causing a deadlock.
Fix that by calling map->cache_ops->drop() directly.

Change-Id: I55c6d3ed490c47e8b3f5ca774d051a700f707b6e
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from git.kernel.org broonie/regmap.git for-next
 commit f0aa1ce6259eb65f53f969b3250c1d0aac84f30b)

drm/rockchip: vop: support interlace display

Change-Id: I39c66ff90d85c2ee7bc8495ed313c359f0d457d6
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

ARM64: dts: rk3399-vr: add n-key for return

Change-Id: I06654319d61d57eabe7556d45501cf081cdd6b39
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

i2c: rk3x: Fix variable 'min_total_ns' unused warning

This patch fixs the following warning:
drivers/i2c/busses/i2c-rk3x.c: In function 'rk3x_i2c_v1_calc_timings':
drivers/i2c/busses/i2c-rk3x.c:745:41: warning: variable 'min_total_ns' set but not used [-Wunused-but-set-variable]

Change-Id: I99da5c5dc80da040eb5333bdf204a71de472a332
Reported-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>

i2c: rk3x: Fix sparse warning

This patch fixes the following sparse warning:
drivers/i2c/busses/i2c-rk3x.c:888:17: warning: cast truncates bits from constant value (ffffffffff00 becomes ffffff00)

Change-Id: If4ffda2f57ce967a6824765093823bd7ff75ebe3
Reported-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>

arm64: configs: add COMPAT configuration

I don't know why it was removed by former savedefconfig.
Maybe I make mistakes..

Change-Id: I4d852320c5b57ba9c72b7ef2981b6b66d76ba0b8
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

arm: dts: add ramp delay to vdd_gpu for rk3288

for mali devfreq

Change-Id: I561fe2db1a38bafcf56db7e8991172d6031da41a
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

drm/rockchip: vop: support csc convert for win0/1

Change-Id: I7be5dfb7d2711de5a5aeed730aea0ffd9e080945
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: vop: init vskiplines on scale calculate

Here is a Bug on scale calculate:
   int vskiplines = 0;
   maybe vskiplines = 2 on yrgb scl_vop_cal_scale
   maybe vskiplines not update on cbcr scl_vop_cal_scale.
   Then cbcr path would get vskiplines = 2, that is unexpect.

Change-Id: Iaeb0d125c7bbcfb95fe32005ef5c938703d03ed4
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

UPSTREAM: regulator: core: remove lockdep assert from suspend_prepare

suspend_prepare can be called during regulator init time also, where
the mutex is not locked yet. This causes a false lockdep warning.
To avoid the problem, remove the lockdep assertion from the function
causing the issue. An alternative would be to lock the mutex during
init, but this would cause other problems (some APIs used during init
will attempt to lock the mutex also, causing deadlock.)

Change-Id: I4a4367f3ebc9c7a00d6a08b547f2cebecd600483
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 07c5c3ad98926dc15d31aa86de62fd4170f2a745)

pinctrl: rockchip: better show irq chip name

When call irq_alloc_domain_generic_chips, pass the name of the irq
chip with bank name instead of just rockchip_gpio_irq.
So we can know the irq belong to which gpio by read /proc/interrupts.

cat /proc/interrupts

before:
 56:        435  rockchip_gpio_irq   3 Level     bcmsdh_sdmmc
 58:          0  rockchip_gpio_irq   5 Edge      power
 87:          2  rockchip_gpio_irq   2 Level     fusb302
105:         36  rockchip_gpio_irq  20 Level     gt9xx
106:          0  rockchip_gpio_irq  21 Level     rk808
109:          0  rockchip_gpio_irq  24 Level     fusb302
209:         42  rockchip_gpio_irq  28 Edge      es8316_interrupt

after:
 56:        401     gpio0   3 Level     bcmsdh_sdmmc
 58:          0     gpio0   5 Edge      power
 87:          2     gpio1   2 Level     fusb302
105:         39     gpio1  20 Level     gt9xx
106:          0     gpio1  21 Level     rk808
109:          0     gpio1  24 Level     fusb302
209:         37     gpio4  28 Edge      es8316_interrupt

Change-Id: Iff7afda770e8493dc4c105c1d251aeae0f69f639
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

arm64: configs: update rockchip config by savedefconfig

Change-Id: Ib70a45ed0a7207705ca5cb3609831a93af5510e9
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

power: rk818-battery: update to v7.1

1. ajust zero algorithm to smooth low power area;
2. set two level speed for finish charging;
3. check divisor to avoid to be zero;
4. add timeout times for finish adc cablibration;
5. fix some logic error and add more debug info.

Change-Id: I248dc6792304b91473af895d549d2f40bcb7a6e2
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

camsys_head: 0.0xd.0

Change-Id: Iba577aeda613a7383d1ea0ef05b1a27e3d251f95
Signed-off-by: dalong.zhang <dalon.zhang@rock-chips.com>

drm/rockchip: vop: optimize register take effect check

Previous version check all the win, check its yrgb_mst and
enable bit, it wastes too manys times.

We can simple check the vop cfg_done register to sure vop register
take effect. when we have a new config, set cfg_done to 1, then the
cfg_done would auto clear at frame start event. So when cfg_done is
zero, means that there is no pending configs.

Change-Id: Ib87114cdaea4d3bbc23fd9e0bd9b49d02f4ae1e3
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

phy: rockchip-inno-usb2: release mutex lock if otg in host mode

We add a mutex lock in rockchip_usb2phy_init(), but foget to
release it if otg port work in host only mode.

Change-Id: I45abf173097be4463b668b51eece99a72047fb18
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

ARM64: dts: rk3399-evb: disable dmc

Since ddr initalize codes have some update, so ddr dmc driver
needs to update.

Disable the dmc currently for evb to boot success.

Change-Id: Ica259a81f5412da31d41b68c841dfda7d8c2e3b2
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

arm64: dts: rockchip: add usb2 phy-phandle for ohci on rk3366

This adds support usb2.0 phy-phandle for ohci controller on rk3366.

Change-Id: I9b5e27636e7574669ba01e4302c741d8895c68ff
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

arm64: dts: rockchip: correct usb-controler reference clk for rk3366

We found that the system on rk3366-sdk will crash at the first time
after updating the whole firmware, the root cause is the 480m clock
from usb-phy has some issues.

Since the new usb-phy driver have taken over the 480m clock's
maintenance, the clock tree have a bit changes, so related
reference clock for usb-controler also need to correct.

Change-Id: I54dcc6f416adf61c34df2b9b897e5b58f3b6fed8
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

ARM64: dts: rk3366-tb: add rk818 battery node

Change-Id: I03c2668f157b33bdfeff36c474104dd337632aa0
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

video: rockchip: hdmi: v2: improved the hdmi nlpcm_mode for bitstream output

- Add the corresponding to samplerate for bitstream
- Add the audio type judgement when open the mode

Change-Id: Ic5bbd2ee214e707fd3695f1a1f359cd43fed9618
Signed-off-by: smj <smj@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ARM: dts: add 'support-emmcs' flag for RK3228 EVB board

Private flag of our downstream kernel.

Change-Id: I6dbfcb04748e9d54492df6df20382367ce1218b2
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM: configs: rockchip: enable es8323 support

Default enable es8323 codec in rockchip defconfig

Change-Id: I9a080fa72069d15bfe188d4b33c1fd06358f4839
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>

ARM: dts: rockchip: add codec es8323 for rk3288 fennec

This patch makes es8323 work well on the RK3288-Fennec boards.

Change-Id: Ia71101363c5cc4a9650c21c5dbebcad4d785ebf8
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>

ASoC: es8323: update codec es8323 driver

This patch update the es8323 codec drivers as follows:

o Remove snd_soc_control_type:
  Now that upstream remove definition of snd_soc_control_type.

o Replace SOC_DAPM_VALUE_ENUM:
  SOC_DAPM_VALUE_ENUM is replaced by SOC_DAPM_ENUM.

o Remove codec->dapm.bias_level = level:
  The line at the end of the set_bias_level callback to update the bias_level state. Now that upstream move this update into snd_soc_dapm_force_bias_level().

o Remove .owner = THIS_MODULE:
  No need to set .owner here.The i2c_driver core will do.

o module_i2c_driver:
  Convert to use module_i2c_driver is simple.

o Add match table:
  Add a device tree match table for es8323 codec driver.

o Add mclk:
  The I2S block provide the output clock as the mclk,so add it.

o Adjust code format:
  Adjust some problems of code format.

Change-Id: I8e0647310eb11325c39ebb408f75cc9ed28df71d
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>

video: rockchip: dp: add sharp2.89" and AUO3.81" lcd for rockchip discrete vr device.

Change-Id: I6a43bb7da3feeb2a96df56b09aa4e77a9c4d8812
Signed-off-by: wjh <wjh@rock-chips.com>

ARM64: dts: rockchip: rk3399: add edp power domain

add pd_edp node.
add the edp needed power domain node for rk3399.

Change-Id: Ie1a4a7013b0d5cfc2b0180f701341a6b977a637a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

video: rockchip: edp: runtime get sync in probe if support uboot display

Change-Id: I0373ef165cf7e21410b05159d4ed25c69bf05d5e
Signed-off-by: xubilv <xbl@rock-chips.com>

ARM64: configs: remove btsdio in linux defconfig

It will cause conflict if we are using other vendor driver.

Change-Id: Ia5f6ccc22c1f733abc1569486d5a864e41d4f4a5
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

arm: configs: remove btsdio in linux defconfig

It will cause conflict if we are using other vendor driver.

Change-Id: I269c253fae874acf1b0290f5f16ca1433cf33b15
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

arm64: dts: rockchip: add hall-sensor device node for rk3399-mid

Change-Id: Iaf9c8aebc1006fe6058536689c1561c66ddde162
Signed-off-by: Bin Yang <yangbin@rock-chips.com>

sensor: add hall sensor mh248 driver support

Change-Id: Idc8a068af8de06c058a2553d174b75166436a5ed
Signed-off-by: Bin Yang <yangbin@rock-chips.com>

Documentation: bindings: add DT documentation for rk_sensor.txt

Change-Id: I06710a0adf648deff3700ec66fba5ac658a49fe7
Signed-off-by: Bin Yang <yangbin@rock-chips.com>

drm/rockchip: vop: fix rk3036 no display

Rk3036 vop default is blank, so init vop with unblank.

Change-Id: I10c21af70cec95b7073f8c999e655031ee154747
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

arm: configs: enable mali devfreq in rockchip_linux_defconfig

Change-Id: Idb43bc4a60c4d1b22d330cf2ea1d0e4b48b60d4d
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

UPSTREAM: i2c: rk3x: Restore clock settings at resume time

Depending on a number of factors including:
- Which exact Rockchip SoC we're working with
- How deep we suspend
- Which i2c port we're on

We might lose the state of the i2c registers at suspend time.
Specifically we've found that on rk3399 the i2c ports that are not in
the PMU power domain lose their state with the current suspend depth
configured by ARM Tursted Firmware.

Note that there are very few actual i2c registers that aren't configured
per transfer anyway so all we actually need to re-configure are the
clock config registers.  We'll just add a call to rk3x_i2c_adapt_div()
at resume time and be done with it.

NOTE: On rk3399 on ports whose power was lost, I put printouts in at
resume time.  I saw things like:
  before: con=0x00010300, div=0x00060006
  after:  con=0x00010200, div=0x00180025

Change-Id: I9799a77b9f332ef6b72ca2a8c1ee348b470a4d53
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: David Wu <david.wu@rock-chips.com>
Tested-by: David Wu <david.wu@rock-chips.com>
[wsa: removed duplicate const]
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>

hid: rkvr: add remove sync process, add sync ioctl to sync with nanoc before trasmitting

Change-Id: I46c8577b2a9c8dd9b66597fba3775966f030ecfd
Signed-off-by: lanshh <lsh@rock-chips.com>

drivers: iio: imu: remove sync attribute in sysfs, we direct access hid-rkvr by ioctl

Change-Id: Ic3605da06f3c8388910b162cf468e03709a98dd0
Signed-off-by: lanshh <lsh@rock-chips.com>

arm64: dts: rockchip: keep wlan power in suspend for rk3399_evb

Change-Id: Iad47ee30f9668ad8ad558dbcebc9023b737911a1
Signed-off-by: zzc <zzc@rock-chips.com>

video: rockchip: fb: update for one vop dual mipi ver scan mode

Change-Id: I07b5970a6f3dc01110dde59615e537612c408e2a
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

phy: rockchip-inno-usb2: don't cancel chg_work if otg in host mode

Because chg_work is used for charge detection, so if OTG works in
Host mode, we don't need to initialize chg_work, and aslo we don't
need to cancel it when phy exit.

Change-Id: I19cbede5aeb4c1f7f8faa32f195fffb0fc71eca9
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

ARM64: dts: rk3399-evb: support ddr devfreq

Enable ddr devfreq for rk3399-evb.

Change-Id: Ie9f0f6d149f547fea35cabc995fe87f33e5c934d
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

ARM: dts: rockchip: add ums boot mode for Linux

Change-Id: I7f5edb9edbe5b9656fafdfb84f523aa45aa93d93
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

dt-bindings: soc: rockchip: add ums mode

On upstream uboot, we use ums mode to update firmware.
Add this flag to help enter USB Mass Storage mode.

Change-Id: I0e515bfd8703bd48d950b72787b365226af11ce9
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

FROMLIST: ARM: dts: rockchip: add syscon-reboot-mode DT node

Rockchip platform use a SYSCON mapped register store
the reboot mode magic value for bootloader to use when
system reboot. So add syscon-reboot-mode driver DT node
for rk3xxx/rk3036/rk3288 based platform

Change-Id: I625613021621bd07a531d29cdb4b7c31a8bfc364
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

arm: dts: add rk3288 miqi board

Change-Id: I2056e5698bc9f3ccad773859fd5168607516b6eb
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

MALI: rockchip: upgrade midgard DDK to r13p0-00rel0

Conflicts:

drivers/gpu/arm/midgard/backend/gpu/mali_kbase_devfreq.c
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_power_model_simple.c
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_power_model_simple.h
drivers/gpu/arm/midgard/mali_kbase_defs.h

Change-Id: Ia7b8004b09ce31a5af6414c27b8ec776c247835a
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

drm/rockchip: vop: reject vlank control when vop is disabled

drm enable/disable_vblank callback maybe call when vop is disabled,
it would cause system hang, we need reject it.

Change-Id: I3825fc9074203579bba0f71b1135f77075af85bb
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

ARM: config: enable syscon reboot mode in rockchip linux defconfig

Change-Id: I4285f478d3923792ae75eadfbc146e332376c90c
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

drivers: rk_nand: move inline function from asm code to c code

move inline function "copy_from_user" and "copy_to_user" from
rk_ftl_arm_v8.S to rk_nand_base.c

Change-Id: Ibac121c2ef04357d1abb35c4dd225bd424503e02
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>

arm64: dts: rockchip: move vibrator node to properly position on rk3399 tablet product

Change-Id: I352ae9e429de997cf9300f14320a363d93ce57b1
Signed-off-by: jerry.zhang <jerry.zhang@rock-chips.com>

ARM64: dts: rockchip: rk3399-evb: increase sdio clk to 150M

Change-Id: Id35a5ce58517fb48d2a3f348eb7c4571b83d3f5e
Signed-off-by: Weilong Gao <gwl@rock-chips.com>

arm64: dts: rockchip: pull down rst-gpio of gmac-phy at suspend for rk3399-box

Some phys would not enter low power mode by writing 'power down'
bit into phy common register0 such as RTL8211E. And pulling down
reset gpio is also a common way to make phy get low consumption,
if the supplied regulator of phy could not be disabled at suspend.

Change-Id: Ib01f48ec8c0bdec633868bb79e4155561ca6c471
Signed-off-by: David Wu <david.wu@rock-chips.com>

phy: rockchip-inno-usb2: support host only mode for otg port

With this patch, we can support host only mode for otg port
(e.g. rk3399 Type-C1 USB). We use of_usb_get_dr_mode_by_phy()
to get the string from property 'dr_mode' of the controller
device node.

Right now, we only support host only mode for phys which do
not have phy-cells, and don't support #phy-cells >= 1.

Change-Id: Ic15b4afdfd954d91e38dbce3c996176bf2d6f101
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

arm64: dts: rockchip: enable Type-C1 phy for rk3399 box USB3 Host

There is an USB3 Standard-A receptacle on the rk3399 box platform
with Type-C1 phy, this patch enalbe Type-C1 phy for the USB3 port.

Change-Id: I77074823e713b8a4c5e4ff693746d1bd2c3c139c
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

phy: phy-rockchip-typec: support Type-C phy work without extcon

There is a Standard-A receptacle on the rk3399 box platform with
Type-C phy, which does not have an extern Type-C controller
(e.g. FUSB302), this result in failure when typec probe, this patch
add support without extcon for usb3.0, support of dp is not included
in this patch.

Change-Id: I1af87d311707a5d385017e10478f992d940000b8
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

usb: dwc3: introduce a connection flag for rockchip platform

We used dwc->connected flag for rockchip platform before, but this
flag can be modified both in dwc3_gadget_disconnect_interrupt() and
dwc3_rockchip_otg_extcon_evt_work(), this result in race condition
may casue USB hot plug failed.

A typical error case is:
Set DWC3 works as peripheral device, connect to PC, after
PC identifies the USB device, and then disconnet USB cable,
if dwc3_gadget_disconnect_interrupt() is called prior to
dwc3_rockchip_otg_extcon_evt_work(), it will cause extcon
work unable to do disconnect operation, and let DWC3 core
device stay in runtime active status. Then if we plug in
USB cable again, we'll fail to do runtime resume DWC3 core
and reinit it.

Change-Id: I1c06fa55c10b3dfb749b689a116ab939a6e13f97
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

UPSTREAM: USB: Fix of_usb_get_dr_mode_by_phy with a shared phy block

Some SoCs have a single phy-hw-block with multiple phys, this is
modelled by a single phy dts node, so we end up with multiple
controller nodes with a phys property pointing to the phy-node
of the otg-phy.

Only one of these controllers typically is an otg controller, yet we
were checking the first controller who uses a phy from the block and
then end up looking for a dr_mode property in e.g. the ehci controller.

This commit fixes this by adding an arg0 parameter to
of_usb_get_dr_mode_by_phy and make of_usb_get_dr_mode_by_phy
check that this matches the phandle args[0] value when looking for
the otg controller.

Conflicts:
drivers/usb/phy/phy-am335x.c

Change-Id: I0b999a7445399cb2c86060bdf662db8aab96d1cc
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit ce15ed4c5dfb3f7757e6611902aed5db253af977)

UPSTREAM: usb: of: fix build breakage on !OF

If OF is disabled, we will try to define a stub for
of_usb_get_dr_mode_by_phy(), however that missed a
static inline annotation which made us redefine the
stub over and over again. Fix that.

Change-Id: I0e3594d2beb29273343dacf0af73f159ad30a35d
Fixes: 98bfb3946695 ("usb: of: add an api to get
dr_mode by the phy node")
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit be99c84300950e876074916b215b511f69f83d3b)