arm64: dts: rockchip: correct usb-controler reference clk for rk3366

We found that the system on rk3366-sdk will crash at the first time
after updating the whole firmware, the root cause is the 480m clock
from usb-phy has some issues.

Since the new usb-phy driver have taken over the 480m clock's
maintenance, the clock tree have a bit changes, so related
reference clock for usb-controler also need to correct.

Change-Id: I54dcc6f416adf61c34df2b9b897e5b58f3b6fed8
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3366-tb.dts b/arch/arm64/boot/dts/rockchip/rk3366-tb.dts
index 420320c22656191b52226189be137edb9267e745..52553e95b64accf02b1171aecc819bdbb99eaf86 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3366-tb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3366-tb.dts
@@ -264,8 +264,8 @@
                             <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "otg_id", "otg_bvalid",
                                  "otg_linestate", "host0_linestate";
-               clocks = <&cru SCLK_USBPHY480M>;
-               clock-names = "usbphy_480m";
+               clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_OTG>;
+               clock-names = "sclk_otgphy0", "otg";
 
                usb_bc {
                        compatible = "inno,phy";
@@ -862,8 +862,8 @@
 };
 
 &usb_otg {
-       clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_OTG>;
-       clock-names = "sclk_otgphy0", "otg";
+       clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_OTG>;
+       clock-names = "usbphy_480m", "otg";
        resets = <&cru SRST_USBOTG_AHB>,
                 <&cru SRST_USBOTG_PHY>,
                 <&cru SRST_USBOTG_CON>;

diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index 3ae404c56cd4c17d47624c0d809e1eb94e50b45c..749cdf12e67b9f366cdb75b432eb0c704cc49395 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@ -479,8 +479,8 @@
                compatible = "generic-ehci";
                reg = <0x0 0xff480000 0x0 0x20000>;
                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
-               clock-names = "sclk_otgphy0", "hclk_host0";
+               clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
+               clock-names = "usbphy_480m", "hclk_host0";
                phys = <&u2phy_host>;
                phy-names = "usb";
                status = "disabled";
@@ -490,8 +490,8 @@
                compatible = "generic-ohci";
                reg = <0x0 0xff4a0000 0x0 0x20000>;
                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
-               clock-names = "sclk_otgphy0", "hclk_host0";
+               clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
+               clock-names = "usbphy_480m", "hclk_host0";
                status = "disabled";
        };