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R600: Non vector only instruction can be scheduled on trans unit
2013-09-04 Vincent LejeuneR600: Non vector only instruction can be scheduled...
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2013-09-04 Vincent LejeuneR600: Use SchedModel enum for is{Trans,Vector}Only...
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2013-09-04 Vincent LejeuneR600: Remove fmul.v4f32.ll test which is redundant...
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2013-09-03 Vincent LejeuneTableGen: Enumerate Schedule Model too.
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2013-07-31 Vincent LejeuneR600: Do not mergevector after a vector reg is used
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2013-07-31 Vincent LejeuneR600: Avoid more than 4 literals in the same instruction...
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2013-07-31 Vincent LejeuneR600: Non vector only instruction can be scheduled...
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2013-07-31 Vincent LejeuneR600: Don't mix LDS and non-LDS instructions in the...
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2013-07-31 Vincent LejeuneR600: Use SchedModel enum for is{Trans,Vector}Only...
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2013-07-31 Vincent LejeuneTableGen: Enumerate Schedule Model too.
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2013-07-31 Vincent LejeuneR600: Remove predicated_break inst
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2013-07-19 Vincent LejeuneR600: Don't emit empty then clause and use alu_pop_after
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2013-07-19 Vincent LejeuneR600: Simplify AMDILCFGStructurize by removing templates...
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2013-07-19 Vincent LejeuneR600: Replace legacy debug code in AMDILCFGStructurizer.cpp
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2013-07-09 Vincent LejeuneR600: Do not predicated basic block with multiple alu...
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2013-07-09 Vincent LejeuneR600: Fix a rare bug where swizzle optimization returns...
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2013-07-09 Vincent LejeuneR600: Fix wrong export reswizzling
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2013-07-09 Vincent LejeuneR600: Use DAG lowering pass to handle fcos/fsin
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2013-07-09 Vincent LejeuneR600: Print Export Swizzle
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2013-06-30 Vincent LejeuneR600: Fix an unitialized variable in R600InstrInfo.cpp
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2013-06-29 Vincent LejeuneR600: Support schedule and packetization of trans-only...
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2013-06-29 Vincent LejeuneR600: Bank Swizzle now display SCL equivalent
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2013-06-17 Vincent LejeuneR600: PV stores Reg id, not index
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2013-06-17 Vincent LejeuneR600: Properly set COUNT_3 bit in TEX clause initiating...
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2013-06-07 Vincent LejeuneR600: Use a refined heuristic to choose when switching...
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2013-06-07 Vincent LejeuneR600: Anti dep better handled in tex clause
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2013-06-07 Vincent LejeuneR600: Remove an extra break in R600OptimizeVectorRegisters.cpp
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2013-06-06 Vincent LejeuneR600: Rewrite an awkward loop in R600MachineScheduler
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2013-06-06 Vincent LejeuneR600: Remove leftover code in R600MachineScheduler.cpp
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2013-06-05 Vincent LejeuneR600: Add a pass that merge Vector Register
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2013-06-05 Vincent LejeuneR600: Schedule copy from phys register at beginning...
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2013-06-04 Vincent LejeuneR600: Add a pass that merge Vector Register
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2013-06-04 Vincent LejeuneR600: Const/Neg/Abs can be folded to dot4
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2013-06-04 Vincent LejeuneR600: Swizzle texture/export instructions
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2013-06-04 Vincent LejeuneR600: Add a test for r183108
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2013-06-03 Vincent LejeuneR600: 3 op instructions have no write bit but the result...
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2013-06-03 Vincent LejeuneR600: CALL_FS consumes a stack size entry
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2013-06-03 Vincent LejeuneR600: use capital letter for PV channel
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2013-06-03 Vincent LejeuneR600: Constraints input regs of interp_xy,_zw
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2013-05-17 Vincent LejeuneR600: Lower int_load_input to copyFromReg instead of...
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2013-05-17 Vincent LejeuneR600: Use bottom up scheduling algorithm
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2013-05-17 Vincent LejeuneR600: Use depth first scheduling algorithm
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2013-05-17 Vincent LejeuneR600: Replace big texture opcode switch in scheduler...
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2013-05-17 Vincent LejeuneR600: Relax some vector constraints on Dot4.
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2013-05-17 Vincent LejeuneR600: Improve texture handling
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2013-05-17 Vincent LejeuneR600: Rename 128 bit registers.
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2013-05-17 Vincent LejeuneR600: Some factorization
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2013-05-17 Vincent LejeuneR600: Factorize Fetch size limit inside AMDGPUSubTarget
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2013-05-17 Vincent LejeuneR600: prettier dump of clamp
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2013-05-02 Vincent LejeuneR600: Signed literals are 64bits wide
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2013-05-02 Vincent LejeuneR600: If previous bundle is dot4, PV valid chan is...
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2013-05-02 Vincent LejeuneR600: Add a test to check that use_kill is emitted
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2013-05-02 Vincent LejeuneR600: Improve asmPrint of ALU clause
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2013-05-02 Vincent LejeuneR600: Prettier asmPrint of Alu
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2013-04-30 Vincent LejeuneR600: fix loop-address.ll test
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2013-04-30 Vincent LejeuneR600: Always use texture cache for compute shaders
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2013-04-30 Vincent LejeuneR600: use native for alu
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2013-04-30 Vincent LejeuneR600: Packetize instructions
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2013-04-30 Vincent LejeuneR600: Rework Scheduling to handle difference between...
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2013-04-30 Vincent LejeuneR600: Add a Bank Swizzle operand
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2013-04-30 Vincent LejeuneR600: Take inner dependency into tex/vtx clauses
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2013-04-30 Vincent LejeuneR600: Turn TEX/VTX into native instructions
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2013-04-30 Vincent LejeuneR600: Add FetchInst bit to instruction defs to denote...
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2013-04-30 Vincent LejeuneR600: Add some new processor variants
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2013-04-30 Vincent LejeuneR600: Clean up instruction class definitions
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2013-04-30 Vincent LejeuneR600: config section now reports use of killgt
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2013-04-23 Vincent LejeuneR600: Use .AMDGPU.config section to emit stacksize
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2013-04-23 Vincent LejeuneR600: Add CF_END
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2013-04-17 Vincent LejeuneR600: Make Export Instruction not duplicable
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2013-04-17 Vincent LejeuneR600: Export is emitted as a CF_NATIVE inst
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2013-04-17 Vincent LejeuneR600: Emit used GPRs count
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2013-04-10 Vincent LejeuneR600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when...
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2013-04-08 Vincent LejeuneR600: Control Flow support for pre EG gen
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2013-04-04 Vincent LejeuneR600: Use a mask for offsets when encoding instructions
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2013-04-04 Vincent LejeuneR600: Fix wrong address when substituting ENDIF
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2013-04-04 Vincent LejeuneR600: Take export into account when computing cf address
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2013-04-03 Vincent LejeuneR600: Fix last ALU of a clause being emitted in a separate...
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2013-04-03 Vincent LejeuneR600: Factorize maximum alu per clause in a single...
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2013-04-03 Vincent LejeuneR600: Simplify data structure and add DEBUG to R600ControlFl...
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2013-04-03 Vincent LejeuneR600: Consider KILLGT as an ALU instruction
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2013-04-01 Vincent LejeuneR600: Add support for native control flow
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2013-04-01 Vincent LejeuneR600/SI: Share code recording ShaderTypeAttribute between...
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2013-04-01 Vincent LejeuneR600: Emit CF_ALU and use true kcache register.
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2013-03-31 Vincent LejeuneR600: Emit native instructions for tex
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2013-03-14 Vincent LejeuneR600: Factorize code handling Const Read Port limitation
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2013-03-13 Vincent LejeuneR600: Remove unused Outputs variable
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2013-03-11 Vincent LejeuneR600: Fix JUMP handling so that MachineInstr verification...
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2013-03-08 Vincent LejeuneR600: Change addresspace in fold-kcache.ll
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2013-03-05 Vincent LejeuneR600: Do not predicate vector op
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2013-03-05 Vincent LejeuneR600: initial scheduler code
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2013-03-05 Vincent LejeuneR600: Remove LowerConstCopyPass and lower CONST_COPY...
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2013-03-05 Vincent LejeuneR600: Turn BUILD_VECTOR into Reg_Sequence
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2013-03-05 Vincent LejeuneR600: CONST_ADDRESS node is not marked as mayLoad anymore
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2013-03-05 Vincent LejeuneR600: Use MUL_IEEE for trig/fdiv intrinsic
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2013-03-05 Vincent LejeuneR600: Add support for indirect addressing of non default...
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2013-02-18 Vincent LejeuneR600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for...
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2013-02-18 Vincent LejeuneR600: Support for TBO
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2013-02-18 Vincent LejeuneR600: Increase number of ArrayBase Reg to 32
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2013-02-14 Vincent LejeuneR600: Do not fold single instruction with more that...
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2013-02-14 Vincent LejeuneR600: Export instructions are no longer terminator
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C/C++ LLVM-based compilers that forbids OOTA behaviors