oota-llvm.git
10 years agoAdd the extracted constant offset using GEP
Jingyue Wu [Fri, 23 May 2014 18:39:40 +0000 (18:39 +0000)]
Add the extracted constant offset using GEP

Fixed a TODO in r207783.

Add the extracted constant offset using GEP instead of ugly
ptrtoint+add+inttoptr. Using GEP simplifies future optimizations and makes IR
easier to understand.

Updated all affected tests, and added a new test in split-gep.ll to cover a
corner case where emitting uglygep is necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209537 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[RuntimeDyld] Remove relocation bounds check introduced in r208375 (MachO only).
Lang Hames [Fri, 23 May 2014 18:35:44 +0000 (18:35 +0000)]
[RuntimeDyld] Remove relocation bounds check introduced in r208375 (MachO only).

We do all of our address arithmetic in 64-bit, and operations involving
logically negative 32-bit offsets (actually represented as unsigned 64 bit ints)
often overflow into higher bits. The overflow check could be preserved by
casting to uint32 at the callsite for applyRelocationValue, but this would
eliminate the value of the check.

The right way to handle overflow in relocations is to make relocation processing
target specific, and compute the values for RelocationEntry objects in the
appropriate types (32-bit for 32-bit targets, 64-bit for 64-bit targets). This
is coming as part of the cleanup I'm working on.

This fixes another i386 regression test.

<rdar://problem/16889891>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209536 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdd FIXME comment based on code review feedback by Hal Finkel on r209338
David Blaikie [Fri, 23 May 2014 16:53:14 +0000 (16:53 +0000)]
Add FIXME comment based on code review feedback by Hal Finkel on r209338

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209529 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoConvert test to use FileCheck.
Rafael Espindola [Fri, 23 May 2014 16:51:13 +0000 (16:51 +0000)]
Convert test to use FileCheck.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209528 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTeach the table generated emitPseudoExpansionLowering function to not emit a switch...
Aaron Ballman [Fri, 23 May 2014 15:33:39 +0000 (15:33 +0000)]
Teach the table generated emitPseudoExpansionLowering function to not emit a switch statement containing only a default statement (and no cases). Updated some of the code to use range-based for loops as well. No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209521 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAliases are always definition, delete dead code.
Rafael Espindola [Fri, 23 May 2014 15:18:06 +0000 (15:18 +0000)]
Aliases are always definition, delete dead code.

While at it, use a range loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209519 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoDelete dead code.
Rafael Espindola [Fri, 23 May 2014 15:07:51 +0000 (15:07 +0000)]
Delete dead code.

GV is never used past this point. This was probably a copy and paste error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209518 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[mips] Work around inconsistency in llvm-mc's placement of fixup markers
Daniel Sanders [Fri, 23 May 2014 13:35:24 +0000 (13:35 +0000)]
[mips] Work around inconsistency in llvm-mc's placement of fixup markers

Summary:
Add a second fixup table to MipsAsmBackend::getFixupKindInfo() to correctly
position llvm-mc's fixup placeholders for big-endian.

See PR19836 for full details of the issue. To summarize, the fixup placeholders
do not account for endianness properly and the implementations of
getFixupKindInfo() for each target are measuring MCFixupKindInfo.TargetOffset
from different ends of the instruction encoding to compensate.

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3889

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209514 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[mips][mips64r6] t(eq|ge|lt|ne)i and t(ge|lt)iu are not available in MIPS32r6/MIPS64r6
Daniel Sanders [Fri, 23 May 2014 13:24:08 +0000 (13:24 +0000)]
[mips][mips64r6] t(eq|ge|lt|ne)i and t(ge|lt)iu are not available in MIPS32r6/MIPS64r6

Summary: Depends on D3872

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3891

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209513 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6
Daniel Sanders [Fri, 23 May 2014 13:18:02 +0000 (13:18 +0000)]
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6

Summary:
Instead the system is required to provide some means of handling unaligned
load/store without special instructions. Options include full hardware
support, full trap-and-emulate, and hybrids such as hardware support within
a cache line and trap-and-emulate for multi-line accesses.

MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to
assume that unaligned accesses are 'fast' on the basis that I expect few
hardware implementations will opt for pure-software handling of unaligned
accesses. The ones that do handle it purely in software can override this.

mips64-load-store-left-right.ll has been merged into load-store-left-right.ll

The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has
been fixed and the variables renamed to clarify the units they hold.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3872

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209512 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[asan] properly instrument memory accesses that have small alignment (smaller than...
Kostya Serebryany [Fri, 23 May 2014 11:52:07 +0000 (11:52 +0000)]
[asan] properly instrument memory accesses that have small alignment (smaller than min(8,size)) by making two checks instead of one. This may slowdown some cases, e.g. long long on 32-bit or wide loads produced after loop unrolling. The benefit is higher sencitivity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209508 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoUpdated the llvm.mem.parallel_loop_access semantics to include the possibility
Pekka Jaaskelainen [Fri, 23 May 2014 11:35:46 +0000 (11:35 +0000)]
Updated the llvm.mem.parallel_loop_access semantics to include the possibility
to have only some of the loop's memory instructions be annotated and still _help_
the loop carried dependence analysis.

This was discussed in the llvmdev ML (topic: "parallel loop metadata question").

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209507 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFixup sys::getHostCPUFeatures crypto names so it doesn't clash with kernel headers
Bradley Smith [Fri, 23 May 2014 10:14:13 +0000 (10:14 +0000)]
Fixup sys::getHostCPUFeatures crypto names so it doesn't clash with kernel headers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209506 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[YAML] Add an optional argument `EnumMask` to the `yaml::IO::bitSetCase()`.
Simon Atanasyan [Fri, 23 May 2014 08:07:09 +0000 (08:07 +0000)]
[YAML] Add an optional argument `EnumMask` to the `yaml::IO::bitSetCase()`.

Some bit-set fields used in ELF file headers in fact contain two parts.
The first one is a regular bit-field. The second one is an enumeraion.
For example ELF header `e_flags` for MIPS target might contain the
following values:

Bit-set values:

  EF_MIPS_NOREORDER = 0x00000001
  EF_MIPS_PIC       = 0x00000002
  EF_MIPS_CPIC      = 0x00000004
  EF_MIPS_ABI2      = 0x00000020

Enumeration:

  EF_MIPS_ARCH_32   = 0x50000000
  EF_MIPS_ARCH_64   = 0x60000000
  EF_MIPS_ARCH_32R2 = 0x70000000
  EF_MIPS_ARCH_64R2 = 0x80000000

For printing bit-sets we use the `yaml::IO::bitSetCase()`. It does not
support bit-set/enumeration combinations and prints too many flags from
an enumeration part. This patch fixes this problem. New method
`yaml::IO::maskedBitSetCase()` handle "enumeration" part of bitset
defined by provided mask.

Patch reviewed by Nick Kledzik and Sean Silva.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209504 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTypedef NumeredTypesMapTy is not used anywhere.
Yaron Keren [Fri, 23 May 2014 07:31:25 +0000 (07:31 +0000)]
Typedef NumeredTypesMapTy is not used anywhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209502 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTest commit.
Jingyue Wu [Fri, 23 May 2014 06:30:12 +0000 (06:30 +0000)]
Test commit.

The keyword "virtual" is not necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209501 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agollvm-ar: Output the file we errored on.
Filipe Cabecinhas [Fri, 23 May 2014 05:52:12 +0000 (05:52 +0000)]
llvm-ar: Output the file we errored on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209500 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRename a couple of variables to be more accurate.
David Blaikie [Fri, 23 May 2014 05:03:23 +0000 (05:03 +0000)]
Rename a couple of variables to be more accurate.

It's not really a "ScopeDIE", as such - it's the abstract function
definition's DIE. And we usually use "SP" for subprograms, rather than
"Sub".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209499 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoDebugInfo: Fix cross-CU references for scopes (and variables within those scopes...
David Blaikie [Fri, 23 May 2014 04:23:06 +0000 (04:23 +0000)]
DebugInfo: Fix cross-CU references for scopes (and variables within those scopes) in abstract definitions of cross-CU inlined functions

Found by Adrian Prantl during post-commit review of r209335.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209498 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMC: remove unnecessary restriction on tests
Saleem Abdulrasool [Fri, 23 May 2014 02:56:51 +0000 (02:56 +0000)]
MC: remove unnecessary restriction on tests

Rafael correctly pointed out that the restriction is unnecessary.  Although the
tests are intended to ensure that we dont abort due to an assertion, running the
tests in all modes is better since it also ensures that we dont crash without
assertions.  Always run these tests to ensure that we can handle invalid input
correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209496 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[ARM64] Fix a bug in shuffle vector lowering to generate corect vext ISD with swapped...
Jiangning Liu [Fri, 23 May 2014 02:54:50 +0000 (02:54 +0000)]
[ARM64] Fix a bug in shuffle vector lowering to generate corect vext ISD with swapped input vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209495 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAttempt to placate compilers that warn on casts between pointer-to-object and
Richard Smith [Fri, 23 May 2014 01:22:46 +0000 (01:22 +0000)]
Attempt to placate compilers that warn on casts between pointer-to-object and
pointer-to-function types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209490 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoScalarEvolution: Fix handling of AddRecs in isKnownPredicate
Justin Bogner [Fri, 23 May 2014 00:06:56 +0000 (00:06 +0000)]
ScalarEvolution: Fix handling of AddRecs in isKnownPredicate

ScalarEvolution::isKnownPredicate() can wrongly reduce a comparison
when both the LHS and RHS are SCEVAddRecExprs. This checks that both
LHS and RHS are guarded in the case when both are SCEVAddRecExprs.

The test case is against indvars because I could not find a way to
directly test SCEV.

Patch by Sanjay Patel!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209487 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[Graph Writer] Limit the length of the graph name because Windows can't handle it.
Michael J. Spencer [Thu, 22 May 2014 23:32:18 +0000 (23:32 +0000)]
[Graph Writer] Limit the length of the graph name because Windows can't handle it.

Windows can't handle paths longer than 260 code points without \\?\. Even
with \\?\ it can't handle path components longer than 255 code points. So
limit graph names to the arbitrary length of 140. Random characters are still
added to the end, so it's ok if graph names collide.

Differential Revision: http://reviews.llvm.org/D3883

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209483 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMake these bool bitfields.
Eric Christopher [Thu, 22 May 2014 23:09:57 +0000 (23:09 +0000)]
Make these bool bitfields.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209481 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[RuntimeDyld] Teach RuntimeDyldMachO how to handle scattered VANILLA relocs on
Lang Hames [Thu, 22 May 2014 22:30:13 +0000 (22:30 +0000)]
[RuntimeDyld] Teach RuntimeDyldMachO how to handle scattered VANILLA relocs on
i386.

This fixes two more MCJIT regression tests on i386:

  ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll
  ExecutionEngine/MCJIT/2013-04-04-RelocAddend.ll

The implementation of processScatteredVANILLA is tasteless (*ba-dum-ching*),
but I'm working on a substantial tidy-up of RuntimeDyldMachO that should
improve things.

This patch also fixes a type-o in RuntimeDyldMachO::processSECTDIFFRelocation,
and teaches that method to skip over the PAIR reloc following the SECTDIFF.

<rdar://problem/16961886>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209478 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoUpdate some AliasAnalysis pass docs for getAdjustedAnalysisPointer.
Eric Christopher [Thu, 22 May 2014 19:38:25 +0000 (19:38 +0000)]
Update some AliasAnalysis pass docs for getAdjustedAnalysisPointer.

Patch by George Burgess.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209467 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600: Add definition for flat address space ID.
Matt Arsenault [Thu, 22 May 2014 18:27:07 +0000 (18:27 +0000)]
R600: Add definition for flat address space ID.

Use 4 since that's probably what it will be for spir.
Move ADDRESS_NONE to the end to keep the constant_buffer_* values
unchanged, since apparently a bunch of r600 tests use those directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209463 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600: Try to convert BFE back to standard bit ops when possible.
Matt Arsenault [Thu, 22 May 2014 18:09:12 +0000 (18:09 +0000)]
R600: Try to convert BFE back to standard bit ops when possible.

This allows existing DAG combines to work on them, and then
we can re-match to BFE if necessary during instruction selection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209462 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600: Add dag combine for BFE
Matt Arsenault [Thu, 22 May 2014 18:09:07 +0000 (18:09 +0000)]
R600: Add dag combine for BFE

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209461 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600: Implement ComputeNumSignBitsForTargetNode for BFE
Matt Arsenault [Thu, 22 May 2014 18:09:03 +0000 (18:09 +0000)]
R600: Implement ComputeNumSignBitsForTargetNode for BFE

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209460 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600: Implement computeMaskedBitsForTargetNode for BFE
Matt Arsenault [Thu, 22 May 2014 18:09:00 +0000 (18:09 +0000)]
R600: Implement computeMaskedBitsForTargetNode for BFE

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209459 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600: Expand mul24 for GPUs without it
Matt Arsenault [Thu, 22 May 2014 18:00:24 +0000 (18:00 +0000)]
R600: Expand mul24 for GPUs without it

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209458 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600: Expand mad24 for GPUs without it
Matt Arsenault [Thu, 22 May 2014 18:00:20 +0000 (18:00 +0000)]
R600: Expand mad24 for GPUs without it

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209457 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600: Add intrinsics for mad24
Matt Arsenault [Thu, 22 May 2014 18:00:15 +0000 (18:00 +0000)]
R600: Add intrinsics for mad24

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209456 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoReturn false if we're not going to do anything.
Eric Christopher [Thu, 22 May 2014 17:49:33 +0000 (17:49 +0000)]
Return false if we're not going to do anything.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209455 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600/SI: Move instruction pattern to instruction definition
Matt Arsenault [Thu, 22 May 2014 17:45:20 +0000 (17:45 +0000)]
R600/SI: Move instruction pattern to instruction definition

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209454 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove LLVMContextImpl::optimizationRemarkEnabledFor.
Diego Novillo [Thu, 22 May 2014 17:19:01 +0000 (17:19 +0000)]
Remove LLVMContextImpl::optimizationRemarkEnabledFor.

Summary:
This patch moves the handling of -pass-remarks* over to
lib/DiagnosticInfo.cpp. This allows the removal of the
optimizationRemarkEnabledFor functions from LLVMContextImpl, as they're
not needed anymore.

Reviewers: qcolombet

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3878

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209453 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[X86] Improve the lowering of BITCAST from MVT::f64 to MVT::v4i16/MVT::v8i8.
Andrea Di Biagio [Thu, 22 May 2014 16:21:39 +0000 (16:21 +0000)]
[X86] Improve the lowering of BITCAST from MVT::f64 to MVT::v4i16/MVT::v8i8.

This patch teaches the x86 backend how to efficiently lower ISD::BITCAST dag
nodes from MVT::f64 to MVT::v4i16 (and vice versa), and from MVT::f64 to
MVT::v8i8 (and vice versa).

This patch extends the logic from revision 208107 to also handle MVT::v4i16
and MVT::v8i8. Also, this patch correctly propagates Undef values when
performing the widening of a vector (example: when widening from v2i32 to
v4i32, the upper 64bits of the resulting vector are 'undef').

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209451 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoARM64: remove '#' from annotation of add/sub immediate
Tim Northover [Thu, 22 May 2014 14:20:05 +0000 (14:20 +0000)]
ARM64: remove '#' from annotation of add/sub immediate

The full string used to be "// =#12" for example, which looks too
busy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209443 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdd support for missed and analysis optimization remarks.
Diego Novillo [Thu, 22 May 2014 14:19:46 +0000 (14:19 +0000)]
Add support for missed and analysis optimization remarks.

Summary:
This adds two new diagnostics: -pass-remarks-missed and
-pass-remarks-analysis. They take the same values as -pass-remarks but
are intended to be triggered in different contexts.

-pass-remarks-missed is used by LLVMContext::emitOptimizationRemarkMissed,
which passes call when they tried to apply a transformation but
couldn't.

-pass-remarks-analysis is used by LLVMContext::emitOptimizationRemarkAnalysis,
which passes call when they want to inform the user about analysis
results.

The patch also:

1- Adds support in the inliner for the two new remarks and a
   test case.

2- Moves emitOptimizationRemark* functions to the llvm namespace.

3- Adds an LLVMContext argument instead of making them member functions
   of LLVMContext.

Reviewers: qcolombet

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3682

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209442 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoSegmented stacks: omit __morestack call when there's no frame.
Tim Northover [Thu, 22 May 2014 13:03:43 +0000 (13:03 +0000)]
Segmented stacks: omit __morestack call when there's no frame.

Patch by Florian Zeitz

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209436 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoARM64: these work too
Tim Northover [Thu, 22 May 2014 12:14:49 +0000 (12:14 +0000)]
ARM64: these work too

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209430 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoYes they do
Tim Northover [Thu, 22 May 2014 12:14:02 +0000 (12:14 +0000)]
Yes they do

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209429 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoARM64: model pre/post-indexed operations properly.
Tim Northover [Thu, 22 May 2014 11:56:20 +0000 (11:56 +0000)]
ARM64: model pre/post-indexed operations properly.

We should be keeping track of the writeback on these instructions,
otherwise we're relying on LLVM's stupidity for correct code.

Fortunately, the MC layer can now handle all required constraints,
which means we can get rid of the CodeGen only PseudoInsts too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209426 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoARM64: separate load/store operands to simplify assembler
Tim Northover [Thu, 22 May 2014 11:56:09 +0000 (11:56 +0000)]
ARM64: separate load/store operands to simplify assembler

This changes ARM64 to use separate operands for each component of an
address, and look for separate '[', '$Rn, ..., ']' tokens when
parsing.

This allows us to do away with quite a bit of special C++ code to
handle monolithic "addressing modes" in the MC components. The more
incremental matching of the assembler operands also allows for better
diagnostics when LLVM is presented with invalid input.

Most of the complexity here is with the register-offset instructions,
which were extremely dodgy beforehand: even when the instruction used
wM, LLVM's model had xM as an operand. We papered over this
discrepancy before, but that approach doesn't work now so I split them
into separate X and W variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209425 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6
Daniel Sanders [Thu, 22 May 2014 11:55:04 +0000 (11:55 +0000)]
[mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6

Summary:
* Split into two functions, one to test each struct.
* R0 and R2 must be defined by an lw with a %got reference to the correct
  symbol.
* Test for $4 (first argument) where appropriate instead of accepting any
  register.
* Test that the two lbu's are correctly combined into $4

Depends on D3844

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3845

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209424 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[mips] Change lwl and lwr in inlineasm_constraint.ll to lw
Daniel Sanders [Thu, 22 May 2014 11:51:06 +0000 (11:51 +0000)]
[mips] Change lwl and lwr in inlineasm_constraint.ll to lw

Summary:
lwl and lwr are not available in MIPS32r6/MIPS64r6. The purpose of the test
is to check that the '$1' expands to '0($x)' rather than to test something related
to the lwl or lwr instructions so we can simply switch to lw.

Depends on D3842

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3844

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209423 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[mips] Use addiu in inline assembly tests since addi is not available in all ISA's
Daniel Sanders [Thu, 22 May 2014 11:46:58 +0000 (11:46 +0000)]
[mips] Use addiu in inline assembly tests since addi is not available in all ISA's

Summary:
This patch is necessary so that they do not fail on MIPS32r6/MIPS64r6 when
-integrated-as is enabled by default and we correctly detect the host CPU.

No functional change since these tests are testing the behaviour of the
constraint used for the third operand rather than the mnemonic.

Depends on D3842

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3843

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209421 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoExtend sys::getHostCPUFeatures to work on AArch64 platforms
Bradley Smith [Thu, 22 May 2014 11:44:34 +0000 (11:44 +0000)]
Extend sys::getHostCPUFeatures to work on AArch64 platforms

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209420 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[mips][mips64r6] addi is not available on MIPS32r6/MIPS64r6
Daniel Sanders [Thu, 22 May 2014 11:42:31 +0000 (11:42 +0000)]
[mips][mips64r6] addi is not available on MIPS32r6/MIPS64r6

Summary: Depends on D3787. Tablegen will raise an assertion without it.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3842

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209419 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[mips][mips64r6] Test that paired single instructions are invalid
Daniel Sanders [Thu, 22 May 2014 11:37:38 +0000 (11:37 +0000)]
[mips][mips64r6] Test that paired single instructions are invalid

Summary:
These emit the 'unknown instruction' instead of the correct error
because they have not been implemented in LLVM for any MIPS ISA.

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3841

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209418 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[mips][mips64r6] Add b[on]vc
Daniel Sanders [Thu, 22 May 2014 11:23:21 +0000 (11:23 +0000)]
[mips][mips64r6] Add b[on]vc

Summary:
This required me to implement the disassembler for MIPS64r6 since the encodings
are ambiguous with other instructions. This in turn revealed a few
assembly/disassembly bugs which I have fixed.

* da[ht]i only take two operands according to the spec, not three.
* DecodeBranchTarget2[16] correctly handles wider immediates than simm16
  * Also made non-functional change to DecodeBranchTarget and
    DecodeBranchTargetMM to keep implementation style consistent between
    them.
* Difficult encodings are handled by a custom decode method on the most
  general encoding in the group. This method will convert the MCInst to a
  different opcode if necessary.

DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue
so disassembling some branch instructions emit incorrect output. This seems
to affect branches with delay slots on all MIPS ISA's. I've left this bug
for now and temporarily removed the check for the immediate on
bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests.

jialc and jic crash the disassembler for some reason. I've left these
instructions commented out for the moment.

Depends on D3760

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3761

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209415 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoARM64: assert if we see i64 -> i64 extend in the DAG.
Tim Northover [Thu, 22 May 2014 07:41:37 +0000 (07:41 +0000)]
ARM64: assert if we see i64 -> i64 extend in the DAG.

Should be no change in behaviour, but it makes the intended
functionality a bit clearer and means we only have to reason about
real extend operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209409 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAArch64/ARM64: enable more AArch64 tests.
Tim Northover [Thu, 22 May 2014 07:40:55 +0000 (07:40 +0000)]
AArch64/ARM64: enable more AArch64 tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209408 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMC: initialise MCAsmParser variable
Saleem Abdulrasool [Thu, 22 May 2014 06:02:59 +0000 (06:02 +0000)]
MC: initialise MCAsmParser variable

Properly initialise HadError to false during construction.  Detected as
use-of-uninitialised variable by MSan!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209393 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove unused variable.
Eric Christopher [Thu, 22 May 2014 05:33:03 +0000 (05:33 +0000)]
Remove unused variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209391 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoARM: introduce llvm.arm.undefined intrinsic
Saleem Abdulrasool [Thu, 22 May 2014 04:46:46 +0000 (04:46 +0000)]
ARM: introduce llvm.arm.undefined intrinsic

This intrinsic permits the emission of platform specific undefined sequences.
ARM has reserved the 0xde opcode which takes a single integer parameter (ignored
by the CPU).  This permits the operating system to implement custom behaviour on
this trap.  The llvm.arm.undefined intrinsic is meant to provide a means for
generating the target specific behaviour from the frontend.  This is
particularly useful for Windows on ARM which has made use of a series of these
special opcodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209390 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600/SI: Match fp_to_uint / uint_to_fp for f64
Matt Arsenault [Thu, 22 May 2014 03:20:30 +0000 (03:20 +0000)]
R600/SI: Match fp_to_uint / uint_to_fp for f64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209388 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMC: formalise some assertions into proper errors
Saleem Abdulrasool [Thu, 22 May 2014 02:18:10 +0000 (02:18 +0000)]
MC: formalise some assertions into proper errors

Now that clang can be used as an assembler via the IAS, invalid assembler inputs
would cause the assertions to trigger.  Although we cannot recover from the
errors here, nor provide caret diagnostics, attempt to handle them slightly more
gracefully by reporting a fatal error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209387 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoOverride runOnMachineFunction for ARMISelDAGToDAG so that we can
Eric Christopher [Thu, 22 May 2014 02:00:27 +0000 (02:00 +0000)]
Override runOnMachineFunction for ARMISelDAGToDAG so that we can
reset the subtarget on each function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209386 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoOverride runOnMachineFunction for X86ISelDAGToDAG so that we can
Eric Christopher [Thu, 22 May 2014 01:53:26 +0000 (01:53 +0000)]
Override runOnMachineFunction for X86ISelDAGToDAG so that we can
reset the subtarget on each function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209384 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAvoid using subtarget features when adding X86 specific passes to
Eric Christopher [Thu, 22 May 2014 01:46:02 +0000 (01:46 +0000)]
Avoid using subtarget features when adding X86 specific passes to
the pass pipeline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209382 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove extra local variable.
Eric Christopher [Thu, 22 May 2014 01:45:59 +0000 (01:45 +0000)]
Remove extra local variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209381 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRename createGlobalBaseRegPass -> createX86GlobalBaseRegPass to make
Eric Christopher [Thu, 22 May 2014 01:45:57 +0000 (01:45 +0000)]
Rename createGlobalBaseRegPass -> createX86GlobalBaseRegPass to make
it obvious that it's a target specific pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209380 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix typo.
Eric Christopher [Thu, 22 May 2014 01:21:44 +0000 (01:21 +0000)]
Fix typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209377 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAvoid using subtarget features when initializing the pass pipeline
Eric Christopher [Thu, 22 May 2014 01:21:35 +0000 (01:21 +0000)]
Avoid using subtarget features when initializing the pass pipeline
on PPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209376 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoReset the subtarget for DAGToDAG on every iteration of runOnMachineFunction.
Eric Christopher [Thu, 22 May 2014 01:07:24 +0000 (01:07 +0000)]
Reset the subtarget for DAGToDAG on every iteration of runOnMachineFunction.
This required updating the generated functions and TD file accordingly
to be pointers rather than const references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209375 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoReset the subtarget for DAGToDAG on every iteration of runOnMachineFunction.
Eric Christopher [Thu, 22 May 2014 01:07:21 +0000 (01:07 +0000)]
Reset the subtarget for DAGToDAG on every iteration of runOnMachineFunction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209374 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoSort includes.
Eric Christopher [Thu, 22 May 2014 01:07:18 +0000 (01:07 +0000)]
Sort includes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209373 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoDebugInfo: Simplify dead variable collection slightly.
David Blaikie [Thu, 22 May 2014 00:48:36 +0000 (00:48 +0000)]
DebugInfo: Simplify dead variable collection slightly.

constructSubprogramDIE was already called for every subprogram in every
CU when the module was started - there's no need to call it again at
module finalization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209372 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix a bug in SCEV's backedge taken count computation from my prior fix in Jan.
Andrew Trick [Thu, 22 May 2014 00:37:03 +0000 (00:37 +0000)]
Fix a bug in SCEV's backedge taken count computation from my prior fix in Jan.

This has to do with the trip count computation for loops with multiple
exits, which is quite subtle. Most passes just ask for a single trip
count number, so we must be conservative assuming any exit could be
taken.  Normally, we rely on the "exact" trip count, which was
correctly given as "unknown". However, SCEV also gives a "max"
back-edge taken count. The loops max BE taken count is conservatively
a maximum over the max of each exit's non-exiting iterations
count. Note that some exit tests can be skipped so the max loop
back-edge taken count can actually exceed the max non-exiting
iterations for some exits. However, when we know the loop *latch*
cannot be skipped, we can directly use its max taken count
disregarding other exits. I previously took the minimum here without
checking whether the other exit could be skipped. The correct, and
simpler thing to do here is just to directly use the loop latch's max
non-exiting iterations as the loops max back-edge count.

In the problematic test case, the first loop exit had a max of zero
non-exiting iterations, but could be skipped. The loop latch was known
not to be skipped but had max of one non-exiting iteration. We
incorrectly claimed the loop back-edge could be taken zero times, when
it is actually taken one time.

Fixes Loop %for.body.i: <multiple exits> Unpredictable backedge-taken count.
Loop %for.body.i: max backedge-taken count is 1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209358 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoSimilar to bitcast, treat addrspacecast as a foldable operand.
Eli Bendersky [Thu, 22 May 2014 00:02:52 +0000 (00:02 +0000)]
Similar to bitcast, treat addrspacecast as a foldable operand.

Added a test sink-addrspacecast.ll to verify this change.

Patch by Jingyue Wu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209343 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix compilation issues.
Eric Christopher [Wed, 21 May 2014 23:51:57 +0000 (23:51 +0000)]
Fix compilation issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209342 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMake early if conversion dependent upon the subtarget and add
Eric Christopher [Wed, 21 May 2014 23:40:26 +0000 (23:40 +0000)]
Make early if conversion dependent upon the subtarget and add
a subtarget hook to enable. Unconditionally add to the pass pipeline
for targets that might want to use it. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209340 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoGroup the scheduling functions together.
Eric Christopher [Wed, 21 May 2014 23:40:18 +0000 (23:40 +0000)]
Group the scheduling functions together.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209339 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert "DebugInfo: Don't put fission type units in comdat sections."
David Blaikie [Wed, 21 May 2014 23:27:41 +0000 (23:27 +0000)]
Revert "DebugInfo: Don't put fission type units in comdat sections."

This reverts commit r208930, r208933, and r208975.

It seems not all fission consumers are ready to handle this behavior.
Reverting until tools are brought up to spec.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209338 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMC: correct IMAGE_REL_ARM_MOV32T relocation emission
Saleem Abdulrasool [Wed, 21 May 2014 23:17:56 +0000 (23:17 +0000)]
MC: correct IMAGE_REL_ARM_MOV32T relocation emission

This corrects the emission of IMAGE_REL_ARM_MOV32T relocations.  Previously, we
were avoiding the high portion of the relocation too early.  If there was a
section-relative relocation with an offset greater than 16-bits (65535), you
would end up truncating the high order bits of the offset.  Allow the current
relocation representation to flow through out the MC layer to the object writer.
Use the new ability to restrict recorded relocations to avoid emitting the
relocation into the final object.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209337 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMC: introduce ability to restrict recorded relocations
Saleem Abdulrasool [Wed, 21 May 2014 23:17:50 +0000 (23:17 +0000)]
MC: introduce ability to restrict recorded relocations

Add support to allow a target specific COFF object writer to restrict the
recorded resolutions in the emitted object files.  This is motivated by the need
in Windows on ARM, where an intermediate relocation needs to be prevented from
being emitted in the object file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209336 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoDebugInfo: Use the SPMap to find the parent CU of inlined functions as they may not...
David Blaikie [Wed, 21 May 2014 23:14:12 +0000 (23:14 +0000)]
DebugInfo: Use the SPMap to find the parent CU of inlined functions as they may not be in the current CU

Committed in r209178 then reverted in r209251 due to LTO breakage,
here's a proper fix for the case of the missing subprogram DIE. The DIEs
were there, just in other compile units. Using the SPMap we can find the
right compile unit to search for and produce cross-unit references to
describe this kind of inlining.

One existing test case needed to be updated because it had a function
that wasn't in the CU's subprogram list, so it didn't appear in the
SPMap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209335 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600: Add comment describing problems with LowerConstantInitializer
Matt Arsenault [Wed, 21 May 2014 22:59:17 +0000 (22:59 +0000)]
R600: Add comment describing problems with LowerConstantInitializer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209333 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600: Partially fix constant initializers for structs and vectors.
Matt Arsenault [Wed, 21 May 2014 22:42:42 +0000 (22:42 +0000)]
R600: Partially fix constant initializers for structs and vectors.

This should extend the current workaround to work with structs
that only contain legal, scalar types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209331 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600: Add failing testcases for constant initializers.
Matt Arsenault [Wed, 21 May 2014 22:42:38 +0000 (22:42 +0000)]
R600: Add failing testcases for constant initializers.

Constant initializers involving illegal types hit an assertion.

Patch by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209330 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove getTargetLowering from TargetPassConfig as the target lowering
Eric Christopher [Wed, 21 May 2014 22:42:07 +0000 (22:42 +0000)]
Remove getTargetLowering from TargetPassConfig as the target lowering
can change depending upon subtarget/subtarget features for a function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209329 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove unused member variable from hexagon pass.
Eric Christopher [Wed, 21 May 2014 22:42:02 +0000 (22:42 +0000)]
Remove unused member variable from hexagon pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209328 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoDebugInfo: Ensure concrete out of line variables from inlined functions reference...
David Blaikie [Wed, 21 May 2014 22:41:17 +0000 (22:41 +0000)]
DebugInfo: Ensure concrete out of line variables from inlined functions reference their abstract origins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209327 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[X86] Fix a bug in the lowering of BLENDI introduced in r209043.
Quentin Colombet [Wed, 21 May 2014 22:00:39 +0000 (22:00 +0000)]
[X86] Fix a bug in the lowering of BLENDI introduced in r209043.
ISD::VSELECT mask uses 1 to identify the first argument and 0 to identify the
second argument.
On the other hand, BLENDI uses 0 to identify the first argument and 1 to
identify the second argument.
Fix the generation of the blend mask to account for this difference.

The bug did not show up with r209043, because we were not checking for the
actual arguments of the blend instruction!
This commit also fixes the test cases.

Note: The same mask works for the BLENDr variant because the arguments are
swapped during instruction selection (see the BLENDXXrr patterns).

<rdar://problem/16975435>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209324 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMove MCOptions that aren't shared between programs into their specific
Eric Christopher [Wed, 21 May 2014 21:05:09 +0000 (21:05 +0000)]
Move MCOptions that aren't shared between programs into their specific
program and have them initialize the MCOptions struct explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209321 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMake a couple of command lines static and remove an unnecessary
Eric Christopher [Wed, 21 May 2014 21:05:05 +0000 (21:05 +0000)]
Make a couple of command lines static and remove an unnecessary
initialization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209320 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoDebugInfo: Simplify subprogram declaration creation/references and accidentally refix...
David Blaikie [Wed, 21 May 2014 18:04:33 +0000 (18:04 +0000)]
DebugInfo: Simplify subprogram declaration creation/references and accidentally refix PR11300.

Also simplifies the linkage name handling a little too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209311 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoUse cast<> instead of unchecked dyn_cast
Matt Arsenault [Wed, 21 May 2014 18:03:59 +0000 (18:03 +0000)]
Use cast<> instead of unchecked dyn_cast

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209310 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMC: loosen an overzealous assertion
Saleem Abdulrasool [Wed, 21 May 2014 17:53:18 +0000 (17:53 +0000)]
MC: loosen an overzealous assertion

Permit active macro expansions when terminating the assembler if there were
errors during the expansion.  This would only trigger on invalid input when
built with assertions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209309 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoUse llvm-lit if LLVM source tree is unavailable.
Greg Fitzgerald [Wed, 21 May 2014 16:44:03 +0000 (16:44 +0000)]
Use llvm-lit if LLVM source tree is unavailable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209308 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTest comment commit.
Dave Estes [Wed, 21 May 2014 16:19:51 +0000 (16:19 +0000)]
Test comment commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209306 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[mips][mips64r6] Add bc[12](eq|ne)z
Daniel Sanders [Wed, 21 May 2014 12:56:39 +0000 (12:56 +0000)]
[mips][mips64r6] Add bc[12](eq|ne)z

Summary: Depends on D3691

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3760

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209292 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[asm matcher] Fix incorrect assertion when there are exactly 32 SubtargetFeatures
Daniel Sanders [Wed, 21 May 2014 10:11:24 +0000 (10:11 +0000)]
[asm matcher] Fix incorrect assertion when there are exactly 32 SubtargetFeatures

Summary:
The minimal type needs to hold a value of '1ULL << 31' but
getMinimalTypeForRange() is called with a value of '1ULL << 32'.

This patch will also reduce the size of the matcher table when there are 8
or 16 SubtargetFeatures.

Also added a dump of the SubtargetFeatures to the -debug output and corrected getMinimalTypeInRange() to consider 0xffffffffull to be a 32-bit value.

The testcase is that no existing code is broken and that LLVM still successfully
compiles after adding MIPS64r6 CodeGen support.

Reviewers: rafael

Reviewed By: rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3787

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209288 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[asan] Fix x86-32 asm instrumentation to preserve flags.
Evgeniy Stepanov [Wed, 21 May 2014 08:14:24 +0000 (08:14 +0000)]
[asan] Fix x86-32 asm instrumentation to preserve flags.

Patch by Yuri Gorshenin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209280 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMC: mark COFF .drectve section as REMOVE
Saleem Abdulrasool [Wed, 21 May 2014 05:15:01 +0000 (05:15 +0000)]
MC: mark COFF .drectve section as REMOVE

The .drectve section should be marked as IMAGE_SCN_LNK_REMOVE.  This matches what
the MSVC toolchain does and accurately reflects that this section should not be
emitted into the final binary.  This section is merely information for the
linker, comprising of additional linker directives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209273 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[modules] Add module maps for LLVM. These are not quite ready for prime-time
Richard Smith [Wed, 21 May 2014 02:46:14 +0000 (02:46 +0000)]
[modules] Add module maps for LLVM. These are not quite ready for prime-time
yet, but only a few more Clang patches need to land. (I have 'ninja check'
passing locally.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209269 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoARM: correct bundle generation for MOV32T relocations
Saleem Abdulrasool [Wed, 21 May 2014 01:25:24 +0000 (01:25 +0000)]
ARM: correct bundle generation for MOV32T relocations

Although the previous code would construct a bundle and add the correct elements
to it, it would not finalise the bundle.  This resulted in the InternalRead
markers not being added to the MachineOperands nor, more importantly, the
externally visible defs to the bundle itself.  So, although the bundle was not
exposing the def, the generated code would be correct because there was no
optimisations being performed.  When optimisations were enabled, the post
register allocator would kick in, and the hazard recognizer would reorder
operations around the load which would define the value being operated upon.

Rather than manually constructing the bundle, simply construct and finalise the
bundle via the finaliseBundle call after both MIs have been emitted.  This
improves the code generation with optimisations where IMAGE_REL_ARM_MOV32T
relocations are emitted.

The changes to the other tests are the result of the bundle generation
preventing the scheduler from hoisting the moves across the loads.  The net
effect of the generated code is equivalent, but, is much more identical to what
is actually being lowered.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209267 91177308-0d34-0410-b5e6-96231b3b80d8