[mips] Use addiu in inline assembly tests since addi is not available in all ISA's
authorDaniel Sanders <daniel.sanders@imgtec.com>
Thu, 22 May 2014 11:46:58 +0000 (11:46 +0000)
committerDaniel Sanders <daniel.sanders@imgtec.com>
Thu, 22 May 2014 11:46:58 +0000 (11:46 +0000)
commit8afb08e5b5536a76bf359c0a75ffc1738d2ad1dc
treeaf094fa4b1abcd48b3d7f1830821b5f623bc66d3
parent00011c71f92328253102032abdb3acbd97fc9d4b
[mips] Use addiu in inline assembly tests since addi is not available in all ISA's

Summary:
This patch is necessary so that they do not fail on MIPS32r6/MIPS64r6 when
-integrated-as is enabled by default and we correctly detect the host CPU.

No functional change since these tests are testing the behaviour of the
constraint used for the third operand rather than the mnemonic.

Depends on D3842

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3843

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209421 91177308-0d34-0410-b5e6-96231b3b80d8
test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll
test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll
test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll
test/CodeGen/Mips/inlineasm-cnstrnt-bad-N.ll
test/CodeGen/Mips/inlineasm-cnstrnt-bad-O.ll
test/CodeGen/Mips/inlineasm-cnstrnt-bad-P.ll
test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll
test/CodeGen/Mips/inlineasm-operand-code.ll
test/CodeGen/Mips/inlineasm_constraint.ll