ARM64: assert if we see i64 -> i64 extend in the DAG.

Should be no change in behaviour, but it makes the intended
functionality a bit clearer and means we only have to reason about
real extend operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209409 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp b/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
index 45a837e69f666d154909b3af6b010ab52462e2e4..ce4203f321cd122fabf91e5561d63110a2e367d0 100644 (file)
--- a/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
+++ b/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
@@ -369,8 +369,7 @@ getExtendTypeForNode(SDValue N, bool IsLoadStore = false) {
       return ARM64_AM::SXTH;
     else if (SrcVT == MVT::i32)
       return ARM64_AM::SXTW;
-    else if (SrcVT == MVT::i64)
-      return ARM64_AM::SXTX;
+    assert(SrcVT != MVT::i64 && "extend from 64-bits?");
 
     return ARM64_AM::InvalidShiftExtend;
   } else if (N.getOpcode() == ISD::ZERO_EXTEND ||
@@ -382,8 +381,7 @@ getExtendTypeForNode(SDValue N, bool IsLoadStore = false) {
       return ARM64_AM::UXTH;
     else if (SrcVT == MVT::i32)
       return ARM64_AM::UXTW;
-    else if (SrcVT == MVT::i64)
-      return ARM64_AM::UXTX;
+    assert(SrcVT != MVT::i64 && "extend from 64-bits?");
 
     return ARM64_AM::InvalidShiftExtend;
   } else if (N.getOpcode() == ISD::AND) {