/// scheduling, DAGCombine, etc.).
virtual bool useAA() const;
+ /// \brief Enable the use of the early if conversion pass.
+ virtual bool enableEarlyIfConversion() const { return false; }
+
/// \brief Reset the features for the subtarget.
virtual void resetSubtargetFeatures(const MachineFunction *MF) { }
};
bool EarlyIfConverter::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "********** EARLY IF-CONVERSION **********\n"
<< "********** Function: " << MF.getName() << '\n');
+ // Only run if conversion if the target wants it.
+ if (!MF.getTarget().getSubtarget().enableEarlyIfConversion())
+ return true;
+
TII = MF.getTarget().getInstrInfo();
TRI = MF.getTarget().getRegisterInfo();
SchedModel =
#define GET_SUBTARGETINFO_TARGET_DESC
#include "ARM64GenSubtargetInfo.inc"
+static cl::opt<bool>
+EnableEarlyIfConvert("arm64-early-ifcvt", cl::desc("Enable the early if "
+ "converter pass"), cl::init(true), cl::Hidden);
+
ARM64Subtarget::ARM64Subtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool LittleEndian)
: ARM64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
Policy.OnlyTopDown = false;
Policy.OnlyBottomUp = false;
}
+
+bool ARM64Subtarget::enableEarlyIfConversion() const override {
+ return EnableEarlyIfConvert;
+}
void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin,
MachineInstr *end,
unsigned NumRegionInstrs) const override;
+
+ bool enableEarlyIfConversion() const override;
};
} // End llvm namespace
EnableCCMP("arm64-ccmp", cl::desc("Enable the CCMP formation pass"),
cl::init(true), cl::Hidden);
-static cl::opt<bool>
-EnableEarlyIfConvert("arm64-early-ifcvt", cl::desc("Enable the early if "
- "converter pass"), cl::init(true), cl::Hidden);
-
static cl::opt<bool>
EnableStPairSuppress("arm64-stp-suppress", cl::desc("Suppress STP for ARM64"),
cl::init(true), cl::Hidden);
bool ARM64PassConfig::addILPOpts() {
if (EnableCCMP)
addPass(createARM64ConditionalCompares());
- if (EnableEarlyIfConvert)
- addPass(&EarlyIfConverterID);
+ addPass(&EarlyIfConverterID);
if (EnableStPairSuppress)
addPass(createARM64StorePairSuppressPass());
return true;
TargetSubtargetInfo::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const override;
+ bool enableEarlyIfConversion() const override { return hasISEL(); }
+
// Scheduling customization.
bool enableMachineScheduler() const override;
void overrideSchedPolicy(MachineSchedPolicy &Policy,
}
bool PPCPassConfig::addILPOpts() {
- if (getPPCSubtarget().hasISEL()) {
- addPass(&EarlyIfConverterID);
- return true;
- }
-
- return false;
+ addPass(&EarlyIfConverterID);
+ return true;
}
bool PPCPassConfig::addInstSelector() {
#define GET_SUBTARGETINFO_CTOR
#include "X86GenSubtargetInfo.inc"
+// Temporary option to control early if-conversion for x86 while adding machine
+// models.
+static cl::opt<bool>
+X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
+ cl::desc("Enable early if-conversion on X86"));
+
+
/// ClassifyBlockAddressReference - Classify a blockaddress reference for the
/// current subtarget according to how we should reference it in a non-pcrel
/// context.
CriticalPathRCs.clear();
return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
}
+
+bool
+X86Subtarget::enableEarlyIfConversion() const override {
+ return hasCMOV() && X86EarlyIfConv;
+}
bool postRAScheduler() const { return PostRAScheduler; }
+ bool enableEarlyIfConversion() const override;
+
/// getInstrItins = Return the instruction itineraries based on the
/// subtarget selection.
const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
cl::desc("Minimize AVX to SSE transition penalty"),
cl::init(true));
-// Temporary option to control early if-conversion for x86 while adding machine
-// models.
-static cl::opt<bool>
-X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
- cl::desc("Enable early if-conversion on X86"));
-
//===----------------------------------------------------------------------===//
// X86 Analysis Pass Setup
//===----------------------------------------------------------------------===//
}
bool X86PassConfig::addILPOpts() {
- if (X86EarlyIfConv && getX86Subtarget().hasCMov()) {
- addPass(&EarlyIfConverterID);
- return true;
- }
- return false;
+ addPass(&EarlyIfConverterID);
+ return true;
}
bool X86PassConfig::addPreRegAlloc() {