oota-llvm.git
12 years agoFix test case.
Benjamin Kramer [Thu, 30 Aug 2012 15:42:45 +0000 (15:42 +0000)]
Fix test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162913 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoLoopRotate: Also rotate loops with multiple exits.
Benjamin Kramer [Thu, 30 Aug 2012 15:39:42 +0000 (15:39 +0000)]
LoopRotate: Also rotate loops with multiple exits.

The old PHI updating code in loop-rotate was replaced with SSAUpdater a while
ago, it has no problems with comples PHIs. What had to be fixed is detecting
whether a loop was already rotated and updating dominators when multiple exits
were present.

This change increases overall code size a bit, mostly due to additional loop
unrolling opportunities. Passes test-suite and selfhost with -verify-dom-info.
Fixes PR7447.

Thanks to Andy for the input on the domtree updating code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162912 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoInstCombine: Fix comment to reflect the code.
Benjamin Kramer [Thu, 30 Aug 2012 15:07:40 +0000 (15:07 +0000)]
InstCombine: Fix comment to reflect the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162911 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoDon't use MCInstrDesc flags for implicit operands.
Jakob Stoklund Olesen [Thu, 30 Aug 2012 14:39:06 +0000 (14:39 +0000)]
Don't use MCInstrDesc flags for implicit operands.

When a MachineInstr is constructed, its implicit operands are added
first, then the explicit operands are inserted before the implicits.

MCInstrDesc has oprand flags like early clobber and operand ties that
apply to the explicit operands.

Don't look at those flags when the implicit operands are first added in
the explicit operands's positions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162910 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoWhitespace
Alexey Samsonov [Thu, 30 Aug 2012 13:47:13 +0000 (13:47 +0000)]
Whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162907 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoIt is illegal to transform (sdiv (ashr X c1) c2) -> (sdiv x (2^c1 * c2)),
Nadav Rotem [Thu, 30 Aug 2012 11:23:20 +0000 (11:23 +0000)]
It is illegal to transform (sdiv (ashr X c1) c2)  -> (sdiv x (2^c1 * c2)),
because C always rounds towards zero.

Thanks Dirk and Ben.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162899 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd support for moving pure S-register to NEON pipeline if desired
Tim Northover [Thu, 30 Aug 2012 10:17:45 +0000 (10:17 +0000)]
Add support for moving pure S-register to NEON pipeline if desired

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162898 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoremove old docs
Nadav Rotem [Thu, 30 Aug 2012 09:23:13 +0000 (09:23 +0000)]
remove old docs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162896 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRefactor fetching file/line info from DWARFContext to simplify the
Alexey Samsonov [Thu, 30 Aug 2012 07:49:50 +0000 (07:49 +0000)]
Refactor fetching file/line info from DWARFContext to simplify the
code and allow better code reuse. Make the code a bit more conforming
to LLVM code style.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162895 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd FMA to switch statement in VectorLegalizer::LegalizeOp so that it can be expanded...
Craig Topper [Thu, 30 Aug 2012 07:34:22 +0000 (07:34 +0000)]
Add FMA to switch statement in VectorLegalizer::LegalizeOp so that it can be expanded when it isn't legal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162894 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd support for FMA to WidenVectorResult.
Craig Topper [Thu, 30 Aug 2012 07:13:41 +0000 (07:13 +0000)]
Add support for FMA to WidenVectorResult.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162893 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoOnly perform DAG combine on FMAs of legal types.
Craig Topper [Thu, 30 Aug 2012 06:56:15 +0000 (06:56 +0000)]
Only perform DAG combine on FMAs of legal types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162892 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoPass by pointer and not std::string.
Bill Wendling [Thu, 30 Aug 2012 01:32:31 +0000 (01:32 +0000)]
Pass by pointer and not std::string.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162888 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoShould put test case under test/ExecutionEngine/MCJIT/
Michael Liao [Thu, 30 Aug 2012 00:43:57 +0000 (00:43 +0000)]
Should put test case under test/ExecutionEngine/MCJIT/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162885 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRevert r162855 in favor of changing clang to emit the absolute coverage file path.
Bill Wendling [Thu, 30 Aug 2012 00:34:21 +0000 (00:34 +0000)]
Revert r162855 in favor of changing clang to emit the absolute coverage file path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162883 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix HashString's Bernstein hash to use unsigned chars, as is usually done.
Will Dietz [Thu, 30 Aug 2012 00:30:21 +0000 (00:30 +0000)]
Fix HashString's Bernstein hash to use unsigned chars, as is usually done.

Changes the hash result for strings containing characters
with values >= 128, such as UTF8 strings (not normal ASCII).

Changed mostly so we match other implementations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162882 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix PR13727
Michael Liao [Thu, 30 Aug 2012 00:30:16 +0000 (00:30 +0000)]
Fix PR13727

- The root cause is that target constant materialization in X86 fast-isel
  creates a PC-rel addressing which may overflow 32-bit range in non-Small code
  model if .rodata section is allocated too far away from code segment in
  MCJIT, which uses Large code model so far.
- Follow the similar logic to fix non-Small code model in fast-isel by skipping
  non-Small code model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162881 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd a bit of documentation to copyPhysReg.
Jakob Stoklund Olesen [Wed, 29 Aug 2012 23:52:55 +0000 (23:52 +0000)]
Add a bit of documentation to copyPhysReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162879 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoVerify the order of tied operands in inline asm.
Jakob Stoklund Olesen [Wed, 29 Aug 2012 23:52:52 +0000 (23:52 +0000)]
Verify the order of tied operands in inline asm.

When there are multiple tied use-def pairs on an inline asm instruction,
the tied uses must appear in the same order as the defs.

It is possible to write an LLVM IR inline asm instruction that breaks
this constraint, but there is no reason for a front end to emit the
operands out of order.

The gnu inline asm syntax specifies tied operands as a single read/write
constraint "+r", so ouf of order operands are not possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162878 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoExplicitly cast an expression to bool before handing it off to __builtin_expect.
Benjamin Kramer [Wed, 29 Aug 2012 23:28:45 +0000 (23:28 +0000)]
Explicitly cast an expression to bool before handing it off to __builtin_expect.

Avoids surprises when someone uses LLVM_(UN)LIKELY with an integer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162877 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd some __builtin_expect magic to StringMap.
Benjamin Kramer [Wed, 29 Aug 2012 22:57:04 +0000 (22:57 +0000)]
Add some __builtin_expect magic to StringMap.

Tombstones and full hash collisions are rare, mark the "empty"
and "no collision" paths as likely. The bug in simplifycfg
that prevented the hints from being picked during selfhost
up was fixed recently :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162874 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoReplace the BUILTIN_EXPECT macro with a less horrible LLVM_LIKELY/LLVM_UNLIKELY inter...
Benjamin Kramer [Wed, 29 Aug 2012 22:57:00 +0000 (22:57 +0000)]
Replace the BUILTIN_EXPECT macro with a less horrible LLVM_LIKELY/LLVM_UNLIKELY interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162873 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAllow targets to specify a minimum supported NOP size when performing NOP padding...
Owen Anderson [Wed, 29 Aug 2012 22:18:56 +0000 (22:18 +0000)]
Allow targets to specify a minimum supported NOP size when performing NOP padding.  If the desired padding is smaller than the supported NOP size,
we will enlarge the padding to make it work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162870 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSet the isTied flags when building INLINEASM MachineInstrs.
Jakob Stoklund Olesen [Wed, 29 Aug 2012 22:02:00 +0000 (22:02 +0000)]
Set the isTied flags when building INLINEASM MachineInstrs.

For normal instructions, isTied() is set automatically by addOperand(),
based on MCInstrDesc, but inline asm has tied operands outside the
descriptor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162869 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoPreserve branch profile metadata during switch formation.
Andrew Trick [Wed, 29 Aug 2012 21:46:38 +0000 (21:46 +0000)]
Preserve branch profile metadata during switch formation.

Patch by Michael Ilseman!
This fixes SimplifyCFGOpt::FoldValueComparisonIntoPredecessors to preserve metata when folding conditional branches into switches.

void foo(int x) {
  if (x == 0)
    bar(1);
  else if (__builtin_expect(x == 10, 1))
    bar(2);
  else if (x == 20)
    bar(3);
}

CFG:

B0
|  \
|   X0
B10
|  \
|   X10
B20
|  \
E   X20

Merge B0-B10:
w(B0-X0) = w(B0-X0)*sum-weights(B10) = w(B0-X0) * (w(B10-X10) + w(B10-B20))
w(B0-X10) = w(B0-B10) * w(B10-X10)
w(B0-B20) = w(B0-B10) * w(B10-B20)

B0 __
| \  \
| X10 X0
B20
|  \
E  X20

Merge B0-B20:
w(B0-X0) = w(B0-X0) * sum-weights(B20) = w(B0-X0) * (w(B20-E) + w(B20-X20))
w(B0-X10) = w(B0-X10) * sum-weights(B20) = ...
w(B0-X20) = w(B0-B20) * w(B20-X20)
w(B0-E) = w(B0-B20) * w(B20-E)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162868 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agowhitespace
Andrew Trick [Wed, 29 Aug 2012 21:46:36 +0000 (21:46 +0000)]
whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162867 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRename hasVolatileMemoryRef() to hasOrderedMemoryRef().
Jakob Stoklund Olesen [Wed, 29 Aug 2012 21:19:21 +0000 (21:19 +0000)]
Rename hasVolatileMemoryRef() to hasOrderedMemoryRef().

Ordered memory operations are more constrained than volatile loads and
stores because they must be ordered with respect to all other memory
operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162861 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd MachineMemOperand::isUnordered().
Jakob Stoklund Olesen [Wed, 29 Aug 2012 21:08:52 +0000 (21:08 +0000)]
Add MachineMemOperand::isUnordered().

This means the same as LoadInst/StoreInst::isUnordered(), and implies
!isVolatile().

Atomic loads and stored are also ordered, and this is the right method
to check if it is safe to reorder memory operations. Ordered atomics
can't be reordered wrt normal loads and stores, which is a stronger
constraint than volatile.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162859 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoDon't move normal loads across volatile/atomic loads.
Jakob Stoklund Olesen [Wed, 29 Aug 2012 20:48:45 +0000 (20:48 +0000)]
Don't move normal loads across volatile/atomic loads.

It is technically allowed to move a normal load across a volatile load,
but probably not a good idea.

It is not allowed to move a load across an atomic load with
Ordering > Monotonic, and we model those with MOVolatile as well.

I recently removed the mayStore flag from atomic load instructions, so
they don't need a pseudo-opcode. This patch makes up for the difference.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162857 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agofix C++ comment in C header
Michael Liao [Wed, 29 Aug 2012 20:32:13 +0000 (20:32 +0000)]
fix C++ comment in C header

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162856 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse the full path to output the .gcda file.
Bill Wendling [Wed, 29 Aug 2012 20:30:44 +0000 (20:30 +0000)]
Use the full path to output the .gcda file.

This lets the user run the program from a different directory and still have the
.gcda files show up in the correct place.
<rdar://problem/12179524>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162855 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoReserve space for the mandatory traceback fields on PPC64.
Hal Finkel [Wed, 29 Aug 2012 20:22:24 +0000 (20:22 +0000)]
Reserve space for the mandatory traceback fields on PPC64.

We need to reserve space for the mandatory traceback fields,
though leaving them as zero is appropriate for now.

Although the ABI calls for these fields to be filled in fully, no
compiler on Linux currently does this, and GDB does not read these
fields.  GDB uses the first word of zeroes during exception handling to
find the end of the function and the size field, allowing it to compute
the beginning of the function.  DWARF information is used for everything
else.  We need the extra 8 bytes of pad so the size field is found in
the right place.

As a comparison, GCC fills in a few of the fields -- language, number
of saved registers -- but ignores the rest.  IBM's proprietary OSes do
make use of the full traceback table facility.

Patch by Bill Schmidt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162854 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse ArrayRef instead of SmallVector when passing vector into function.
Bill Wendling [Wed, 29 Aug 2012 18:45:41 +0000 (18:45 +0000)]
Use ArrayRef instead of SmallVector when passing vector into function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162851 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoVerify the consistency of inline asm operands.
Jakob Stoklund Olesen [Wed, 29 Aug 2012 18:11:05 +0000 (18:11 +0000)]
Verify the consistency of inline asm operands.

The operands on an INLINEASM machine instruction are divided into groups
headed by immediate flag operands. Verify this structure.

Extract verifyTiedOperands(), and only call it for non-inlineasm
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162849 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoClean this up slightly, doesn't really fall through.
Eric Christopher [Wed, 29 Aug 2012 17:59:32 +0000 (17:59 +0000)]
Clean this up slightly, doesn't really fall through.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162848 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRefactor setExecutionDomain to be clearer about what it's doing and more robust.
Tim Northover [Wed, 29 Aug 2012 16:36:07 +0000 (16:36 +0000)]
Refactor setExecutionDomain to be clearer about what it's doing and more robust.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162844 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMake helper function static.
Benjamin Kramer [Wed, 29 Aug 2012 16:17:01 +0000 (16:17 +0000)]
Make helper function static.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162843 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMake MemoryBuiltins aware of TargetLibraryInfo.
Benjamin Kramer [Wed, 29 Aug 2012 15:32:21 +0000 (15:32 +0000)]
Make MemoryBuiltins aware of TargetLibraryInfo.

This disables malloc-specific optimization when -fno-builtin (or -ffreestanding)
is specified. This has been a problem for a long time but became more severe
with the recent memory builtin improvements.

Since the memory builtin functions are used everywhere, this required passing
TLI in many places. This means that functions that now have an optional TLI
argument, like RecursivelyDeleteTriviallyDeadFunctions, won't remove dead
mallocs anymore if the TLI argument is missing. I've updated most passes to do
the right thing.

Fixes PR13694 and probably others.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162841 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoConvert FMA4 patterns to use target specific nodes instead of intrinsics to align...
Craig Topper [Wed, 29 Aug 2012 07:18:25 +0000 (07:18 +0000)]
Convert FMA4 patterns to use target specific nodes instead of intrinsics to align with FMA3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162829 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMake use of the LLVM_DELETED_FUNCTION macro.
Craig Topper [Wed, 29 Aug 2012 06:28:46 +0000 (06:28 +0000)]
Make use of the LLVM_DELETED_FUNCTION macro.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162828 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd virtual keywords for methods that override the base class.
Craig Topper [Wed, 29 Aug 2012 05:48:09 +0000 (05:48 +0000)]
Add virtual keywords for methods that override the base class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162826 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCleanup sloppy code. Jakob's review.
Andrew Trick [Wed, 29 Aug 2012 04:41:37 +0000 (04:41 +0000)]
Cleanup sloppy code. Jakob's review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162825 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix a nondeterminism in the ARM assembler.
Andrew Trick [Wed, 29 Aug 2012 03:52:57 +0000 (03:52 +0000)]
Fix a nondeterminism in the ARM assembler.

Adding arbitrary records to ARM.td would break
basic-arm-instructions.s because selection of nop vs mov r0,r0 was
ambiguous (this will be tested by a subsequent addition to ARM.td).
An imperfect but sensible fix is to give precedence to match rules
that have more constraints.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162824 91177308-0d34-0410-b5e6-96231b3b80d8

12 years ago[arm-fast-isel] Add support for ARM PIC.
Jush Lu [Wed, 29 Aug 2012 02:41:21 +0000 (02:41 +0000)]
[arm-fast-isel] Add support for ARM PIC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162823 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix ARM vector copies of overlapping register tuples.
Andrew Trick [Wed, 29 Aug 2012 01:58:55 +0000 (01:58 +0000)]
Fix ARM vector copies of overlapping register tuples.

I have tested the fix, but have not been successfull in generating
a robust unit test. This can only be exposed through particular
register assignments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162821 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agocleanup
Andrew Trick [Wed, 29 Aug 2012 01:58:52 +0000 (01:58 +0000)]
cleanup

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162820 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCreate llvm/test/Object/Mips/lit.local.cfg to check Mips in targets_to_build.
NAKAMURA Takumi [Wed, 29 Aug 2012 01:37:57 +0000 (01:37 +0000)]
Create llvm/test/Object/Mips/lit.local.cfg to check Mips in targets_to_build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162819 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoVerify the tied operand flags.
Jakob Stoklund Olesen [Wed, 29 Aug 2012 00:38:03 +0000 (00:38 +0000)]
Verify the tied operand flags.

WHen running with -verify-machineinstrs, check that tied operands come
in matching use/def pairs, and that they are consistent with MCInstrDesc
when it applies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162816 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEnable recursing into the compiler-rt projcet with the CMake build.
Chandler Carruth [Wed, 29 Aug 2012 00:38:02 +0000 (00:38 +0000)]
Enable recursing into the compiler-rt projcet with the CMake build.

This only fires if using a recent enough CMake -- compiler-rt uses a few
of the more advanced features that not everyone needs.

Please let me know if anyone sees issues with this. I'll be updating
documentation and other stuff to tell people about this.

Many thanks to Alexey for doing a ton of work to get ASan's CMake build
into a really fantastic shape. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162815 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMaintain a vaild isTied bit as operands are added and removed.
Jakob Stoklund Olesen [Wed, 29 Aug 2012 00:37:58 +0000 (00:37 +0000)]
Maintain a vaild isTied bit as operands are added and removed.

The isTied bit is set automatically when a tied use is added and
MCInstrDesc indicates a tied operand. The tie is broken when one of the
tied operands is removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162814 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agollvm/test: [CMake] Add profile_rt-shared to deps.
NAKAMURA Takumi [Wed, 29 Aug 2012 00:37:56 +0000 (00:37 +0000)]
llvm/test: [CMake] Add profile_rt-shared to deps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162813 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agolibprofile: [CMake] Let libprofile_rt be not loadable_module but shared library....
NAKAMURA Takumi [Wed, 29 Aug 2012 00:37:51 +0000 (00:37 +0000)]
libprofile: [CMake] Let libprofile_rt be not loadable_module but shared library. Autoconf's one does so.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162812 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agollvm/test/Analysis/Profiling: Mark 3 of them as REQUIRES: loadable_module.
NAKAMURA Takumi [Wed, 29 Aug 2012 00:37:46 +0000 (00:37 +0000)]
llvm/test/Analysis/Profiling: Mark 3 of them as REQUIRES: loadable_module.

FIXME: profile_rt.dll could be built on win32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162811 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMoved input for objdump test from Mips to Inputs.
Jack Carter [Wed, 29 Aug 2012 00:10:48 +0000 (00:10 +0000)]
Moved input for objdump test from Mips to Inputs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162808 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTypo.
Chad Rosier [Tue, 28 Aug 2012 23:57:47 +0000 (23:57 +0000)]
Typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162807 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd comments on the literal value used.
Michael Liao [Tue, 28 Aug 2012 23:42:17 +0000 (23:42 +0000)]
Add comments on the literal value used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162805 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoLLI: move instruction cache tweaks.
Jim Grosbach [Tue, 28 Aug 2012 23:22:30 +0000 (23:22 +0000)]
LLI: move instruction cache tweaks.

Invalidate the instruction cache right before we start actually executing code, otherwise
we can miss some that came later. This is still not quite right for a truly lazilly
compiled environment, but it's closer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162803 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoProfile: set branch weight metadata with data generated from profiling.
Manman Ren [Tue, 28 Aug 2012 22:21:25 +0000 (22:21 +0000)]
Profile: set branch weight metadata with data generated from profiling.

This patch implements ProfileDataLoader which loads profile data generated by
-insert-edge-profiling and updates branch weight metadata accordingly.

Patch by Alastair Murray.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162799 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoThe instruction DEXT may be transformed into DEXTU or DEXTM depending
Jack Carter [Tue, 28 Aug 2012 20:07:41 +0000 (20:07 +0000)]
The instruction DEXT may be transformed into DEXTU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.

This patch allows support of the dext transformations with mips64 direct
object output.

0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword

32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword

32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162782 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSome of the instructions in the Mips instruction set are revision
Jack Carter [Tue, 28 Aug 2012 19:24:49 +0000 (19:24 +0000)]
Some of the instructions in the Mips instruction set are revision
delimited. llvm-mc -disassemble access these through the -mattr
option.

llvm-objdump -disassemble had no such way to set the attribute so
some instructions were just not recognized for disassembly.

This patch accepts llvm-mc mechanism for specifying the attributes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162781 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoExplicitly update the number of nodes to be traversed
Michael Liao [Tue, 28 Aug 2012 19:20:29 +0000 (19:20 +0000)]
Explicitly update the number of nodes to be traversed

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162780 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSome instructions are passed to the assembler to be
Jack Carter [Tue, 28 Aug 2012 19:07:39 +0000 (19:07 +0000)]
Some instructions are passed to the assembler to be
transformed to the final instruction variant. An
example would be dsrll which is transformed into
dsll32 if the shift value is greater than 32.

For direct object output we need to do this transformation
in the codegen. If the instruction was inside branch
delay slot, it was being missed. This patch corrects this
oversight.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162779 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEmit word of zeroes after the last instruction as a start of the mandatory
Roman Divacky [Tue, 28 Aug 2012 19:06:55 +0000 (19:06 +0000)]
Emit word of zeroes after the last instruction as a start of the mandatory
traceback table on PowerPC64. This helps gdb handle exceptions. The other
mandatory fields are ignored by gdb and harder to implement so just add
there a FIXME.

Patch by Bill Schmidt. PR13641.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162778 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFollow-up patch to r162731.
Akira Hatanaka [Tue, 28 Aug 2012 18:58:57 +0000 (18:58 +0000)]
Follow-up patch to r162731.

Fix a couple of bugs in mips' long branch pass.
This patch was supposed to be committed along with r162731, so I don't have a
new test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162777 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd a MachineOperand::isTied() flag.
Jakob Stoklund Olesen [Tue, 28 Aug 2012 18:34:41 +0000 (18:34 +0000)]
Add a MachineOperand::isTied() flag.

While in SSA form, a MachineInstr can have pairs of tied defs and uses.
The tied operands are used to represent read-modify-write operands that
must be assigned the same physical register.

Previously, tied operand pairs were computed from fixed MCInstrDesc
fields, or by using black magic on inline assembly instructions.

The isTied flag makes it possible to add tied operands to any
instruction while getting rid of (some of) the inlineasm magic.

Tied operands on normal instructions are needed to represent predicated
individual instructions in SSA form. An extra <tied,imp-use> operand is
required to represent the output value when the instruction predicate is
false.

Adding a predicate to:

  %vreg0<def> = ADD %vreg1, %vreg2

Will look like:

  %vreg0<tied,def> = ADD %vreg1, %vreg2, pred:3, %vreg7<tied,imp-use>

The virtual register %vreg7 is the value given to %vreg0 when the
predicate is false. It will be assigned the same physreg as %vreg0.

This commit adds the isTied flag and sets it based on MCInstrDesc when
building an instruction. The flag is not used for anything yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162774 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoDon't allow TargetFlags on MO_Register MachineOperands.
Jakob Stoklund Olesen [Tue, 28 Aug 2012 18:05:48 +0000 (18:05 +0000)]
Don't allow TargetFlags on MO_Register MachineOperands.

Register operands are manipulated by a lot of target-independent code,
and it is not always possible to preserve target flags. That means it is
not safe to use target flags on register operands.

None of the targets in the tree are using register operand target flags.
External targets should be using immediate operands to annotate
instructions with operand modifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162770 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoPatch by Sean Silva to un-barf his computer by explicitly removing the '\n'
Bill Wendling [Tue, 28 Aug 2012 17:18:27 +0000 (17:18 +0000)]
Patch by Sean Silva to un-barf his computer by explicitly removing the '\n'
character instead of always the last character.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162767 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd PPC Freescale e500mc and e5500 subtargets.
Hal Finkel [Tue, 28 Aug 2012 16:12:39 +0000 (16:12 +0000)]
Add PPC Freescale e500mc and e5500 subtargets.

Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to
the PowerPC backend.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162764 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoInstCombine: Defensively avoid undefined shifts by limiting the amount to the bit...
Benjamin Kramer [Tue, 28 Aug 2012 13:59:23 +0000 (13:59 +0000)]
InstCombine: Defensively avoid undefined shifts by limiting the amount to the bit width.

No test case, undefined shifts get folded early, but can occur when other
transforms generate a constant. Thanks to Duncan for bringing this up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162755 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoInstCombine: Guard the transform introduced in r162743 against large ints and non...
Benjamin Kramer [Tue, 28 Aug 2012 13:08:13 +0000 (13:08 +0000)]
InstCombine: Guard the transform introduced in r162743 against large ints and non-const shifts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162751 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMake sure that we don't call getZExtValue on values > 64 bits.
Nadav Rotem [Tue, 28 Aug 2012 12:23:22 +0000 (12:23 +0000)]
Make sure that we don't call getZExtValue on values > 64 bits.
Thanks Benjamin for noticing this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162749 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTeach InstCombine to canonicalize [SU]div+[AL]shl patterns.
Nadav Rotem [Tue, 28 Aug 2012 10:01:43 +0000 (10:01 +0000)]
Teach InstCombine to canonicalize  [SU]div+[AL]shl patterns.

For example:
  %1 = lshr i32 %x, 2
  %2 = udiv i32 %1, 100

rdar://12182093

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162743 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoThe commutative flag is already correctly set within the multiclass. If we set
Bill Wendling [Tue, 28 Aug 2012 07:36:46 +0000 (07:36 +0000)]
The commutative flag is already correctly set within the multiclass. If we set
it here, then a 'register-memory' version would wrongly get the commutative
flag.
<rdar://problem/12180135>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162741 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoConvert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.
Craig Topper [Tue, 28 Aug 2012 07:30:47 +0000 (07:30 +0000)]
Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162740 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMerge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.
Craig Topper [Tue, 28 Aug 2012 07:05:28 +0000 (07:05 +0000)]
Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162738 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agollvm/test/CodeGen/X86/pr12312.ll: Add -mtriple=x86_64-unknown-unknown.
NAKAMURA Takumi [Tue, 28 Aug 2012 04:04:29 +0000 (04:04 +0000)]
llvm/test/CodeGen/X86/pr12312.ll: Add -mtriple=x86_64-unknown-unknown.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162736 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix PR12312
Michael Liao [Tue, 28 Aug 2012 03:34:40 +0000 (03:34 +0000)]
Fix PR12312

- Add a target-specific DAG optimization to recognize a pattern PTEST-able.
  Such a pattern is a OR'd tree with X86ISD::OR as the root node. When
  X86ISD::OR node has only its flag result being used as a boolean value and
  all its leaves are extracted from the same vector, it could be folded into an
  X86ISD::PTEST node.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162735 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCheck all patterns for missing instruction flags.
Jakob Stoklund Olesen [Tue, 28 Aug 2012 03:26:49 +0000 (03:26 +0000)]
Check all patterns for missing instruction flags.

Both single-instruction and multi-instruction patterns can be checked
for missing mayLoad / mayStore, and hasSideEffects flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162734 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRemove extra MayLoad/MayStore flags from atomic_load/store.
Jakob Stoklund Olesen [Tue, 28 Aug 2012 03:11:32 +0000 (03:11 +0000)]
Remove extra MayLoad/MayStore flags from atomic_load/store.

These extra flags are not required to properly order the atomic
load/store instructions. SelectionDAGBuilder chains atomics as if they
were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on
the memory operands of all atomic operations.

The volatile bit is enough to order atomic loads and stores during and
after SelectionDAG.

This means we set mayLoad on atomic_load, mayStore on atomic_store, and
mayLoad+mayStore on the remaining atomic read-modify-write operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162733 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRevert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM."
Jakob Stoklund Olesen [Tue, 28 Aug 2012 03:11:27 +0000 (03:11 +0000)]
Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM."

This wasn't the right way to enforce ordering of atomics.

We are already setting the isVolatile bit on memory operands of atomic
operations which is good enough to enforce the correct ordering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162732 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix mips' long branch pass.
Akira Hatanaka [Tue, 28 Aug 2012 03:03:05 +0000 (03:03 +0000)]
Fix mips' long branch pass.

Instructions emitted to compute branch offsets now use immediate operands
instead of symbolic labels. This change was needed because there were problems
when R_MIPS_HI16/LO16 relocations were used to make shared objects.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162731 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSplit several PPC instruction classes.
Hal Finkel [Tue, 28 Aug 2012 02:49:14 +0000 (02:49 +0000)]
Split several PPC instruction classes.

Slight reorganisation of PPC instruction classes for scheduling. No
functionality change for existing subtargets.
 - Clearly separate load/store-with-update instructions from regular loads and stores.
 - Split IntRotateD -> IntRotateD and IntRotateDI
 - Split out fsub and fadd from FPGeneral -> FPAddSub
 - Update existing itineraries

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162729 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix bug 13532.
Akira Hatanaka [Tue, 28 Aug 2012 02:12:42 +0000 (02:12 +0000)]
Fix bug 13532.

In SelectionDAGLegalize::ExpandLegalINT_TO_FP, expand INT_TO_FP nodes without
using any f64 operations if f64 is not a legal type.

Patch by Stefan Kristiansson.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162728 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAllow remat of LI on PPC.
Hal Finkel [Tue, 28 Aug 2012 02:10:33 +0000 (02:10 +0000)]
Allow remat of LI on PPC.

Allow load-immediates to be rematerialised in the register coalescer for
PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail,
because it relies on a register move getting emitted. The immediate load is
equivalent, so change this test case.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162727 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd the Freescale vendor to Triple.
Hal Finkel [Tue, 28 Aug 2012 02:10:30 +0000 (02:10 +0000)]
Add the Freescale vendor to Triple.

Adds the vendor 'fsl' (used by Freescale SDK) to Triple. This will allow
clang support for Freescale cross-compile configurations.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162726 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEliminate redundant CR moves on PPC32.
Hal Finkel [Tue, 28 Aug 2012 02:10:27 +0000 (02:10 +0000)]
Eliminate redundant CR moves on PPC32.

The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and
unset if it doesn't. The solution up to now was to insert a MachineNode to
set/unset the CR bit, which produces a CR vreg. This vreg was then copied
into CR bit 6. When the register allocator saw a bunch of these in the same
function, it allocated the set/unset CR bit in some random CR register (1
extra instruction) and then emitted CR moves before every vararg function
call, rather than just setting and unsetting CR bit 6 directly before every
vararg function call. This patch instead inserts a PPCcrset/PPCcrunset
instruction which are then matched by a dedicated instruction pattern.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162725 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoOptimize zext on PPC64.
Hal Finkel [Tue, 28 Aug 2012 02:10:15 +0000 (02:10 +0000)]
Optimize zext on PPC64.

The zeroextend IR instruction is lowered to an 'and' node with an immediate
mask operand, which in turn gets legalised to a sequence of ori's & ands.
This can be done more efficiently using the rldicl instruction.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162724 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTemporarily revert this to bring back the bots.
Eric Christopher [Tue, 28 Aug 2012 01:17:46 +0000 (01:17 +0000)]
Temporarily revert this to bring back the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162722 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMore missing mayLoad flags on AVX multiclasses.
Jakob Stoklund Olesen [Tue, 28 Aug 2012 00:02:01 +0000 (00:02 +0000)]
More missing mayLoad flags on AVX multiclasses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162714 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.
Jakob Stoklund Olesen [Mon, 27 Aug 2012 23:58:52 +0000 (23:58 +0000)]
Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.

It is not safe to use normal LDR instructions because they may be
reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag
that prevents reordering.

Atomic loads are also prevented from participating in rematerialization
and load folding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162713 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd --program-prefix support to build.
Sebastian Pop [Mon, 27 Aug 2012 23:05:06 +0000 (23:05 +0000)]
Add --program-prefix support to build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162707 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix compile error when building with C++11 - clang thinks that PRIx64 is a user-defin...
Marshall Clow [Mon, 27 Aug 2012 22:53:35 +0000 (22:53 +0000)]
Fix compile error when building with C++11 - clang thinks that PRIx64 is a user-defined suffix or something

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162704 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMake sure we add the predicate after all of the registers are added.
Bill Wendling [Mon, 27 Aug 2012 22:12:44 +0000 (22:12 +0000)]
Make sure we add the predicate after all of the registers are added.
<rdar://problem/12183003>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162703 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoDon't use for loops for code that is only intended to execute once. No
Dan Gohman [Mon, 27 Aug 2012 18:31:36 +0000 (18:31 +0000)]
Don't use for loops for code that is only intended to execute once. No
intended functionality change. Thanks to Ahmed Charles for spotting it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162686 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix comment.
Rafael Espindola [Mon, 27 Aug 2012 16:04:24 +0000 (16:04 +0000)]
Fix comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162678 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix comment for function RuntimeDyldImpl.resolveRelocation()
Danil Malyshev [Mon, 27 Aug 2012 15:34:01 +0000 (15:34 +0000)]
Fix comment for function RuntimeDyldImpl.resolveRelocation()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162677 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRemove the the block_node_iterator of Region, replace it by the block_iterator.
Hongbin Zheng [Mon, 27 Aug 2012 13:49:24 +0000 (13:49 +0000)]
Remove the the block_node_iterator of Region, replace it by the block_iterator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162672 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSupport MIPS DSP Rev2 intrinsics.
Simon Atanasyan [Mon, 27 Aug 2012 12:29:01 +0000 (12:29 +0000)]
Support MIPS DSP Rev2 intrinsics.
The patch reviewed by Akira Hatanaka.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162668 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agollvm/test/CodeGen/X86/fma.ll: Add -march=x86, or two tests would fail on non-x86...
NAKAMURA Takumi [Mon, 27 Aug 2012 11:50:26 +0000 (11:50 +0000)]
llvm/test/CodeGen/X86/fma.ll: Add -march=x86, or two tests would fail on non-x86 hosts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162667 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoDWARFDebugRangeList.cpp: Use PRIx64 for uint64_t as format string.
NAKAMURA Takumi [Mon, 27 Aug 2012 10:10:10 +0000 (10:10 +0000)]
DWARFDebugRangeList.cpp: Use PRIx64 for uint64_t as format string.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162665 91177308-0d34-0410-b5e6-96231b3b80d8