[X86] Never hoist the shift value of a shift instruction.
[oota-llvm.git] / test / CodeGen / R600 /
2014-04-30 Tom StellardR600/SI: Use VALU instructions for copying i1 values
2014-04-30 Tom StellardR600/SI: Teach moveToVALU how to handle some SMRD instr...
2014-04-29 Tom StellardR600/SI: Custom lower SI_IF and SI_ELSE to avoid machin...
2014-04-29 Tom StellardR600/SI: Only select SALU instructions in the entry...
2014-04-29 Tom StellardR600: optimize the UDIVREM 64 algorithm
2014-04-23 Matt ArsenaultR600: Add a test that used to be broken that I forgot...
2014-04-22 Matt ArsenaultR600: Emit error instead of unreachable on function...
2014-04-22 Matt ArsenaultR600: Make sign_extend_inreg legal.
2014-04-18 Matt ArsenaultR600/SI: Try to use scalar BFE.
2014-04-18 Matt ArsenaultR600/SI: Match sign_extend_inreg to s_sext_i32_i8 and...
2014-04-18 Tom StellardR600/SI: Use SReg_64 instead of VSrc_64 when selecting...
2014-04-17 Tom StellardR600/SI: Stop using i128 as the resource descriptor...
2014-04-17 Matt ArsenaultR600/SI: f64 frint is legal on CI
2014-04-17 Matt ArsenaultR600/SI: Fix zext from i1 to i64
2014-04-16 Matt ArsenaultR600: Extend r600 sign_extend_inreg tests for EG
2014-04-15 Matt ArsenaultR600/SI: Print more immediates in hex format
2014-04-15 Matt ArsenaultR600/SI: Fix loads of i1
2014-04-11 Tom StellardSelectionDAG: Use helper function to improve legalizati...
2014-04-09 Matt ArsenaultR600/SI: Match not instruction.
2014-04-07 Tom StellardR600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies
2014-04-07 Tom StellardR600: Match 24-bit arithmetic patterns in a Target...
2014-04-03 Tom StellardR600: Correct opcode for BFE_INT
2014-04-03 Tom StellardR600/SI: Lower 64-bit immediates using REG_SEQUENCE
2014-04-02 Tom StellardTargetLibraryInfo: Disable memcpy and memset on R600
2014-04-01 Matt ArsenaultFix missing RUN line in test
2014-04-01 Matt ArsenaultMake isSetCCEquivalent respect the TargetBooleanContents
2014-03-31 Matt ArsenaultR600: Compute masked bits for min and max
2014-03-31 Matt ArsenaultR600: Add BFE, BFI, and BFM intrinsics to help with...
2014-03-31 Tom StellardR600/SI: Lower i64 SELECT by bitcasting to a vector...
2014-03-27 Matt ArsenaultR600: Implement isZExtFree.
2014-03-27 Matt ArsenaultR600/SI: Fix unreachable with a sext_in_reg to an illeg...
2014-03-26 Matt ArsenaultR600: Add a testcase for sext_in_reg I missed.
2014-03-25 Matt ArsenaultR600: Add failing testcase for <3 x i32> stores.
2014-03-24 Matt ArsenaultR600/SI: Fix extra mov from legalizing 64-bit SALU...
2014-03-24 Matt ArsenaultR600/SI: Sub-optimial fix for 64-bit immediates with...
2014-03-24 Matt ArsenaultR600/SI: Fix 64-bit bit ops that require the VALU.
2014-03-24 Matt ArsenaultR600: Implement isNarrowingProfitable.
2014-03-24 Matt ArsenaultR600/SI: Fix 64-bit private loads.
2014-03-21 Matt ArsenaultR600/SI: Move instruction patterns to scalar versions.
2014-03-21 Tom StellardR600/SI: Handle MUBUF instructions in SIInstrInfo:...
2014-03-21 Tom StellardR600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU()
2014-03-19 Matt ArsenaultR600/SI: Add support for 64-bit LDS writes
2014-03-19 Matt ArsenaultR600/SI: Add support for 64-bit LDS loads.
2014-03-19 Matt ArsenaultR600/SI: Match i16 immediate offset of LDS instructions.
2014-03-19 Matt ArsenaultR600/SI: Fix test checking wrong instruction operand.
2014-03-19 Matt ArsenaultR600/SI: Don't display the GDS bit.
2014-03-18 NAKAMURA TakumiCodeGen/R600/v_cndmask.ll: Relax an expression to unbre...
2014-03-17 Kevin EnderbyMaking a guess to fix the test case with r204056 to...
2014-03-17 Matt ArsenaultR600: Match sign_extend_inreg to BFE instructions
2014-03-17 Tom StellardR600/SI: Fix implementation of isInlineConstant() used...
2014-03-17 Tom StellardR600/SI: Use correct dest register class for V_READFIRS...
2014-03-13 Tom StellardR600: LDS instructions shouldn't implicitly define...
2014-03-12 Matt ArsenaultR600: Fix trunc store from i64 to i1
2014-03-07 Tom StellardR600/SI: Using SGPRs is illegal for instructions that...
2014-03-07 Tom StellardR600/SI: Custom lower i1 stores
2014-03-06 Matt ArsenaultR600: Fix extloads from i8 / i16 to i64.
2014-03-06 Matt ArsenaultR600/SI: Expand selects on vectors.
2014-03-01 Matt ArsenaultR600: Add failing control flow tests.
2014-02-28 Tom StellardR600/SI: Expand all v16[if]32 operations
2014-02-27 Michel DanzerR600/SI: Optimize SI_KILL for constant operands
2014-02-27 Michel DanzerR600/SI: Allow SI_KILL for geometry shaders
2014-02-25 Tom StellardR600/SI: Custom select 64-bit ADD
2014-02-24 Matt ArsenaultR600/SI - Add new CI arithmetic instructions.
2014-02-22 Quentin Colombet[CodeGenPrepare] Fix the check of the legality of an...
2014-02-16 Nico RieckFix more broken CHECK lines
2014-02-14 Quentin Colombet[CodeGenPrepare][AddressingModeMatcher] Give up on...
2014-02-14 Tom StellardTargetLowering: n * r where n > 2 should be an illegal...
2014-02-13 Tom StellardR600/SI: Expand all v8[if]32 operations
2014-02-13 Tom StellardR600/SI: Add a pattern for i32 anyext
2014-02-13 Tom StellardR600/SI: Completely Disable TypeRewriter on compute
2014-02-13 Tom StellardR600/SI: Split global vector loads with more than 4...
2014-02-13 Tom StellardR600/SI: Add ShaderType attribute to some tests
2014-02-11 Matt ArsenaultR600/SI: Fix assertion on infinite loops.
2014-02-10 Tom StellardR600/SI: Initialize M0 and emit S_WQM_B64 whenever...
2014-02-07 Matt ArsenaultR600/SI: Add failing test for 3 x i64 vectors.
2014-02-06 Tom StellardR600/SI: Add a MUBUF store pattern for Reg+Imm offsets
2014-02-06 Tom StellardR600/SI: Add a MUBUF store pattern for Imm offsets
2014-02-06 Tom StellardR600/SI: Add a MUBUF load pattern for Reg+Imm offsets
2014-02-06 Tom StellardR600/SI: Use immediates offsets for SMRD instructions...
2014-02-05 Michel DanzerR600/SI: Add pattern for zero-extending i1 to i32
2014-02-04 Tom StellardR600/SI: Custom lower i64 ISD::SELECT
2014-02-04 Tom StellardR600: Enable vector fpow.
2014-02-04 Michel DanzerR600/SI: Fix fneg for 0.0
2014-02-02 Matt ArsenaultAdd some xfailed R600 tests for 64-bit private accesses.
2014-02-02 Matt ArsenaultR600/SI: Fix insertelement with dynamic indices.
2014-01-28 Michel DanzerR600/SI: Add pattern for truncating i32 to i1
2014-01-27 Michel DanzerR600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions
2014-01-27 Michel DanzerR600/SI: Add intrinsic for S_SENDMSG instruction
2014-01-23 Tom StellardR600: Disable the BFE pattern
2014-01-23 Tom StellardR600: Correctly handle vertex fetch clauses the precede...
2014-01-23 Tom StellardR600: Unconditionally unroll loops that contain GEPs...
2014-01-23 Tom StellardR600: Recommit 199842: Add work-around for the CF stack...
2014-01-22 Tom StellardRevert "R600: Add work-around for the CF stack entry...
2014-01-22 Tom StellardR600: Add work-around for the CF stack entry HW bug
2014-01-22 Tom StellardR600: Refactor stack size calculation
2014-01-22 Tom StellardR600: MOVA is vector only
2014-01-22 Tom StellardR600: Take alignment into account when calculating...
2014-01-22 Tom StellardR600: Add support for global addresses with constant...
2014-01-22 Tom StellardR600: Begin private memory at the second GPR.
2014-01-22 Tom StellardR600/SI: Add support for i8 and i16 private loads/stores
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