R600/SI: Don't display the GDS bit.

It isn't actually used now, and probably never will be, plus it makes
tests less annoying. I also think SC prints GDS instructions as a
separate instruction name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204270 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
index 57b36b3298aa6cbc1f7d052e3793071cadcfe808..8973f2898c9367d4ff4dc59b5d15b00b08bd7fd0 100644 (file)
--- a/lib/Target/R600/SIInstrInfo.td
+++ b/lib/Target/R600/SIInstrInfo.td
@@ -395,7 +395,7 @@ class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
   op,
   (outs regClass:$vdst),
   (ins i1imm:$gds, VReg_32:$addr, i16imm:$offset),
-  asm#" $gds, $vdst, $addr, $offset, [M0]",
+  asm#" $vdst, $addr, $offset, [M0]",
   []> {
   let data0 = 0;
   let data1 = 0;
@@ -407,7 +407,7 @@ class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
   op,
   (outs),
   (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, i16imm:$offset),
-  asm#" $gds, $addr, $data0, $offset [M0]",
+  asm#" $addr, $data0, $offset [M0]",
   []> {
   let data1 = 0;
   let mayStore = 1;
@@ -419,7 +419,7 @@ class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
   op,
   (outs rc:$vdst),
   (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, i16imm:$offset),
-  asm#" $gds, $vdst, $addr, $data0, $offset, [M0]",
+  asm#" $vdst, $addr, $data0, $offset, [M0]",
   []> {
 
   let data1 = 0;

diff --git a/test/CodeGen/R600/32-bit-local-address-space.ll b/test/CodeGen/R600/32-bit-local-address-space.ll
index 25ad97e2ea26c7f41a00107603246814ed2af870..362cc825dff5d092e70e0a45307054689e705b09 100644 (file)
--- a/test/CodeGen/R600/32-bit-local-address-space.ll
+++ b/test/CodeGen/R600/32-bit-local-address-space.ll
@@ -69,7 +69,7 @@ define void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] addrspace(3)* %
 
 ; CHECK-LABEL: @infer_ptr_alignment_global_offset:
 ; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0
-; CHECK: DS_READ_B32 v{{[0-9]+}}, 0, [[REG]]
+; CHECK: DS_READ_B32 v{{[0-9]+}}, [[REG]]
 define void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %tid) {
   %val = load float addrspace(3)* @g_lds
   store float %val, float addrspace(1)* %out

diff --git a/test/CodeGen/R600/atomic_load_add.ll b/test/CodeGen/R600/atomic_load_add.ll
index 0bc48a3590b225a0db3f9c29f7e2200ccd789ff6..cb0242cd0c91a65ffeee91d7f1f9d2f6506883ae 100644 (file)
--- a/test/CodeGen/R600/atomic_load_add.ll
+++ b/test/CodeGen/R600/atomic_load_add.ll
@@ -4,7 +4,7 @@
 ; R600-CHECK-LABEL: @atomic_add_local
 ; R600-CHECK: LDS_ADD *
 ; SI-CHECK-LABEL: @atomic_add_local
-; SI-CHECK: DS_ADD_U32_RTN 0
+; SI-CHECK: DS_ADD_U32_RTN
 define void @atomic_add_local(i32 addrspace(3)* %local) {
 entry:
    %0 = atomicrmw volatile add i32 addrspace(3)* %local, i32 5 seq_cst
@@ -14,7 +14,7 @@ entry:
 ; R600-CHECK-LABEL: @atomic_add_ret_local
 ; R600-CHECK: LDS_ADD_RET *
 ; SI-CHECK-LABEL: @atomic_add_ret_local
-; SI-CHECK: DS_ADD_U32_RTN 0
+; SI-CHECK: DS_ADD_U32_RTN
 define void @atomic_add_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %local) {
 entry:
   %0 = atomicrmw volatile add i32 addrspace(3)* %local, i32 5 seq_cst

diff --git a/test/CodeGen/R600/atomic_load_sub.ll b/test/CodeGen/R600/atomic_load_sub.ll
index e4a682932c82b714c217a41d5696bdc7a9a71852..7c26e529a360f1f2b74e2ddbda346b14b80c7a24 100644 (file)
--- a/test/CodeGen/R600/atomic_load_sub.ll
+++ b/test/CodeGen/R600/atomic_load_sub.ll
@@ -4,7 +4,7 @@
 ; R600-CHECK-LABEL: @atomic_sub_local
 ; R600-CHECK: LDS_SUB *
 ; SI-CHECK-LABEL: @atomic_sub_local
-; SI-CHECK: DS_SUB_U32_RTN 0
+; SI-CHECK: DS_SUB_U32_RTN
 define void @atomic_sub_local(i32 addrspace(3)* %local) {
 entry:
    %0 = atomicrmw volatile sub i32 addrspace(3)* %local, i32 5 seq_cst
@@ -14,7 +14,7 @@ entry:
 ; R600-CHECK-LABEL: @atomic_sub_ret_local
 ; R600-CHECK: LDS_SUB_RET *
 ; SI-CHECK-LABEL: @atomic_sub_ret_local
-; SI-CHECK: DS_SUB_U32_RTN 0
+; SI-CHECK: DS_SUB_U32_RTN
 define void @atomic_sub_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %local) {
 entry:
   %0 = atomicrmw volatile sub i32 addrspace(3)* %local, i32 5 seq_cst

diff --git a/test/CodeGen/R600/local-memory-two-objects.ll b/test/CodeGen/R600/local-memory-two-objects.ll
index e2d840645d011ea968f2bcc4b18c846aa380575c..fdb2a5d292d4ca6d3fc1d9c4a77cff02bf2d87e2 100644 (file)
--- a/test/CodeGen/R600/local-memory-two-objects.ll
+++ b/test/CodeGen/R600/local-memory-two-objects.ll
@@ -17,8 +17,8 @@
 ; this consistently on evergreen GPUs.
 ; EG-CHECK: LDS_WRITE
 ; EG-CHECK: LDS_WRITE
-; SI-CHECK: DS_WRITE_B32 0, {{v[0-9]*}}, v[[ADDRW:[0-9]*]]
-; SI-CHECK-NOT: DS_WRITE_B32 0, {{v[0-9]*}}, v[[ADDRW]]
+; SI-CHECK: DS_WRITE_B32 {{v[0-9]*}}, v[[ADDRW:[0-9]*]]
+; SI-CHECK-NOT: DS_WRITE_B32 {{v[0-9]*}}, v[[ADDRW]]
 
 ; GROUP_BARRIER must be the last instruction in a clause
 ; EG-CHECK: GROUP_BARRIER
@@ -27,8 +27,8 @@
 ; Make sure the lds reads are using different addresses.
 ; EG-CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
 ; EG-CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
-; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, 0, [[ADDRR:v[0-9]+]]
-; SI-CHECK-NOT: DS_READ_B32 {{v[0-9]+}}, 0, [[ADDRR]]
+; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]]
+; SI-CHECK-NOT: DS_READ_B32 {{v[0-9]+}}, [[ADDRR]]
 
 define void @local_memory_two_objects(i32 addrspace(1)* %out) {
 entry:

diff --git a/test/CodeGen/R600/local-memory.ll b/test/CodeGen/R600/local-memory.ll
index 8db78ad46a6146918f1437f724a03c8a2847676e..6ebe41d0a8fd7011a5deb717c5974e3f83bbf540 100644 (file)
--- a/test/CodeGen/R600/local-memory.ll
+++ b/test/CodeGen/R600/local-memory.ll
@@ -18,7 +18,7 @@
 
 ; EG-CHECK: LDS_WRITE
 ; SI-CHECK-NOT: S_WQM_B64
-; SI-CHECK: DS_WRITE_B32 0
+; SI-CHECK: DS_WRITE_B32
 
 ; GROUP_BARRIER must be the last instruction in a clause
 ; EG-CHECK: GROUP_BARRIER
@@ -26,7 +26,7 @@
 ; SI-CHECK: S_BARRIER
 
 ; EG-CHECK: LDS_READ_RET
-; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, 0
+; SI-CHECK: DS_READ_B32 {{v[0-9]+}},
 
 define void @local_memory(i32 addrspace(1)* %out) {
 entry: