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Taints the non-acquire RMW's store address with the load part
[oota-llvm.git]
/
test
/
CodeGen
/
R600
/ sub.ll
2015-06-13
Tom Stellard
R600 -> AMDGPU rename
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2015-04-30
Jan Vesely
Reinstate revisions r234755, r234759, r234760
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2015-04-13
Jan Vesely
Revert revisions r234755, r234759, r234760
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2015-04-13
Jan Vesely
R600: Add carry and borrow instructions. Use them to...
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2015-04-13
Jan Vesely
LegalizeDAG: Try to use Overflow operations when expand...
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2015-02-27
David Blaikie
[opaque pointer type] Add textual IR support for explic...
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2015-02-27
David Blaikie
[opaque pointer type] Add textual IR support for explic...
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2015-01-12
Tom Stellard
R600/SI: Use RegisterOperands to specify which operands...
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2015-01-06
Tom Stellard
R600/SI: Add a stub GCNTargetMachine
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2014-12-02
Matt Arsenault
R600: Cleanup some tests and add missing testcases
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2014-11-05
Tom Stellard
R600/SI: Change all instruction assembly names to lower...
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2014-10-01
Tom Stellard
R600: Call EmitFunctionHeader() in the AsmPrinter to...
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2014-09-05
Tom Stellard
R600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of...
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2014-06-23
Matt Arsenault
R600/SI: Handle i64 sub.
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2014-06-09
Matt Arsenault
R600/SI: Keep 64-bit not on SALU
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2014-05-05
Tom Stellard
R600: Expand i64 ISD:SUB
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2013-11-12
Matt Arsenault
R600/SI: Change formatting of printed registers.
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2013-10-10
Tom Stellard
R600/SI: Use -verify-machineinstrs for most tests
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2013-09-04
Vincent Lejeune
R600: Non vector only instruction can be scheduled...
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2013-08-12
Tom Stellard
R600: Set scheduling preference to Sched::Source
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2013-08-01
Tom Stellard
R600: Add 64-bit float load/store support
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2013-07-31
Tom Stellard
Revert "R600: Non vector only instruction can be schedu...
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2013-07-31
Vincent Lejeune
R600: Non vector only instruction can be scheduled...
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2013-06-20
Tom Stellard
R600/SI: Expand sub for v2i32 and v4i32 for SI
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2013-05-10
Tom Stellard
R600: Expand SUB for v2i32/v4i32
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