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Taints the non-acquire RMW's store address with the load part
[oota-llvm.git]
/
test
/
CodeGen
/
R600
/ setcc.ll
2015-06-13
Tom Stellard
R600 -> AMDGPU rename
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commitdiff
2015-02-27
David Blaikie
[opaque pointer type] Add textual IR support for explic...
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commitdiff
2015-02-27
David Blaikie
[opaque pointer type] Add textual IR support for explic...
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commitdiff
2015-01-06
Tom Stellard
R600/SI: Add a stub GCNTargetMachine
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commitdiff
2014-12-11
Matt Arsenault
R600/SI: Use unordered equal instructions
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commitdiff
2014-12-11
Matt Arsenault
R600/SI: Make more unordered comparisons legal
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commitdiff
2014-12-11
Matt Arsenault
R600/SI: Use unordered not equal instructions
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commitdiff
2014-12-03
Matt Arsenault
R600/SI: Remove i1 pseudo VALU ops
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commitdiff
2014-11-28
Matt Arsenault
R600/SI: Fix assertion on sign extend of 3 vectors
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commitdiff
2014-11-05
Tom Stellard
R600/SI: Change all instruction assembly names to lower...
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2014-10-01
Tom Stellard
R600: Call EmitFunctionHeader() in the AsmPrinter to...
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commitdiff
2014-05-15
Tom Stellard
R600/SI: Use VALU instructions for i1 ops
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commitdiff
2014-04-29
Tom Stellard
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machin...
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2013-11-22
Tom Stellard
R600/SI: Fixing handling of condition codes
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2013-08-12
Tom Stellard
R600: Set scheduling preference to Sched::Source
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commitdiff
2013-08-01
Tom Stellard
R600: Add 64-bit float load/store support
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commitdiff
2013-06-25
Aaron Watry
R600: Add v2i32 test for setcc on evergreen
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commitdiff
2013-04-19
Tom Stellard
R600: Reorganize lit tests and document how they should...
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