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Taints the non-acquire RMW's store address with the load part
[oota-llvm.git]
/
test
/
CodeGen
/
R600
/ fdiv.ll
2015-06-13
Tom Stellard
R600 -> AMDGPU rename
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commitdiff
2015-02-27
David Blaikie
[opaque pointer type] Add textual IR support for explic...
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2015-02-27
David Blaikie
[opaque pointer type] Add textual IR support for explic...
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2015-01-27
Marek Olsak
R600/SI: Enable all tests that pass on VI without changes
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2015-01-06
Tom Stellard
R600/SI: Add a stub GCNTargetMachine
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2014-11-05
Tom Stellard
R600/SI: Change all instruction assembly names to lower...
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2014-10-01
Tom Stellard
R600: Call EmitFunctionHeader() in the AsmPrinter to...
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2014-07-15
Matt Arsenault
R600/SI: Implement less wrong f32 fdiv
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2013-10-10
Tom Stellard
R600/SI: Use -verify-machineinstrs for most tests
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2013-09-04
Vincent Lejeune
R600: Non vector only instruction can be scheduled...
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2013-08-16
Tom Stellard
R600: Expand vector float operations for both SI and...
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2013-08-01
Tom Stellard
R600: Add 64-bit float load/store support
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2013-07-31
Tom Stellard
Revert "R600: Non vector only instruction can be schedu...
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2013-07-31
Vincent Lejeune
R600: Non vector only instruction can be scheduled...
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2013-07-23
Tom Stellard
R600: Use KCache for kernel arguments
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2013-06-29
Vincent Lejeune
R600: Support schedule and packetization of trans-only...
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2013-05-17
Vincent Lejeune
R600: Use bottom up scheduling algorithm
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2013-05-02
Vincent Lejeune
R600: Prettier asmPrint of Alu
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2013-04-19
Tom Stellard
R600: Reorganize lit tests and document how they should...
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