2014-12-30 |
Peter Collingbourne | x86_64: Fix calls to __morestack under the large code... |
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2014-12-30 |
Colin LeMahieu | [Hexagon] Adding reg-reg indexed load forms. |
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2014-12-30 |
Colin LeMahieu | [Hexagon] Dropping old combine instructions without... |
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2014-12-30 |
Colin LeMahieu | [Hexagon] Adding compare byte/halfword reg-reg/reg... |
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2014-12-30 |
Colin LeMahieu | [Hexagon] Updating constant extender def, adding alu... |
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2014-12-30 |
Rafael Espindola | Remove doesSectionRequireSymbols. |
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2014-12-29 |
Colin LeMahieu | [Hexagon] Adding allocframe, post-increment circular... |
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2014-12-29 |
Colin LeMahieu | [Hexagon] Fixing 224952 where an addressing mode update... |
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2014-12-29 |
Colin LeMahieu | [Hexagon] Adding post-increment register form stores... |
tree | commitdiff |
2014-12-29 |
Colin LeMahieu | [Hexagon] Replacing the remaining postincrement stores... |
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2014-12-29 |
Colin LeMahieu | [Hexagon] Renaming old multiclass for removal. Adding... |
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2014-12-29 |
Craig Topper | [X86] Fix some cases where some 8-bit instructions... |
tree | commitdiff |
2014-12-29 |
Craig Topper | [X86] Add the 0x82 instructions to the disassebmler... |
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2014-12-29 |
Craig Topper | [x86] Refactor some tablegen instruction info classes... |
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2014-12-29 |
Craig Topper | [x86] Remove unused classes from tablegen instruction... |
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2014-12-29 |
Rafael Espindola | Add segmented stack support for DragonFlyBSD. |
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2014-12-29 |
Rafael Espindola | Refactor duplicated code. |
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2014-12-28 |
Keno Fischer | [X86][ISel] Fix a regression I introduced in r224884 |
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2014-12-28 |
Michael Kuperstein | [X86] Add missing memory variants to AVX false dependen... |
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2014-12-28 |
Andrea Di Biagio | [CodeGenPrepare] Teach when it is profitable to specula... |
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2014-12-27 |
Craig Topper | [x86] Prevent instruction selection of AVX512 cmp.ps... |
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2014-12-27 |
David Majnemer | PowerPC: CTR shouldn't fire if a TLS call is in the... |
tree | commitdiff |
2014-12-27 |
Aaron Ballman | Fixing another -Wunused-variable warning, this time... |
tree | commitdiff |
2014-12-27 |
Aaron Ballman | Removing a variable that is set but never used, to... |
tree | commitdiff |
2014-12-27 |
Craig Topper | [x86] Prevent instruction selection of AVX512 cmp.ps... |
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2014-12-27 |
Craig Topper | [x86] Assert on invalid immediates in the instruction... |
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2014-12-27 |
Craig Topper | [x86] Prevent llvm.x86.cmp.ps/pd/ss/sd from being selec... |
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2014-12-27 |
Keno Fischer | [FastIsel][X86] Fix invalid register replacement for... |
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2014-12-26 |
Colin LeMahieu | [Hexagon] Adding auto-incrementing loads with and witho... |
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2014-12-26 |
Colin LeMahieu | [Hexagon] Adding locked loads. |
tree | commitdiff |
2014-12-26 |
Colin LeMahieu | [Hexagon] Adding deallocframe and circular addressing... |
tree | commitdiff |
2014-12-26 |
Colin LeMahieu | [Hexagon] Adding remaining post-increment instruction... |
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2014-12-26 |
Colin LeMahieu | [Hexagon] Adding post-increment unsigned byte loads. |
tree | commitdiff |
2014-12-26 |
Colin LeMahieu | [Hexagon] Adding post-increment signed byte loads with... |
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2014-12-26 |
Craig Topper | [X86] Add the debug registers DR8-DR15 so we can assemb... |
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2014-12-26 |
Craig Topper | [X86] Don't fail disassembly if REX.R/REX.B is used... |
tree | commitdiff |
2014-12-26 |
Craig Topper | Teach disassembler to handle illegal immediates on... |
tree | commitdiff |
2014-12-26 |
Craig Topper | Use MCPhysReg for table of register encodings. |
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2014-12-25 |
Hal Finkel | [PowerPC] [FastISel] i1 constants must be zero extended |
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2014-12-25 |
Elena Demikhovsky | Masked Load/Store - Changed the order of parameters... |
tree | commitdiff |
2014-12-24 |
Saleem Abdulrasool | MC: address some comments in deprecation checks |
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2014-12-24 |
Craig Topper | [X86] Remove the single AdSize indicator and replace... |
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2014-12-24 |
Colin LeMahieu | [Hexagon] Removing old classes. |
tree | commitdiff |
2014-12-23 |
Hal Finkel | [PowerPC] Ensure that the TOC reload directly follows... |
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2014-12-23 |
Colin LeMahieu | [Hexagon] Adding doubleword load. |
tree | commitdiff |
2014-12-23 |
Colin LeMahieu | [Hexagon] Reapplying 224775 load words. |
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2014-12-23 |
Jozef Kolek | [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB... |
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2014-12-23 |
Colin LeMahieu | Reverting 224775 until mayLoad flag is addressed. |
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2014-12-23 |
Colin LeMahieu | [Hexagon] Adding word loads. |
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2014-12-23 |
Colin LeMahieu | [Hexagon] Adding signed halfword loads. |
tree | commitdiff |
2014-12-23 |
Colin LeMahieu | [Hexagon] Adding unsigned halfword load. |
tree | commitdiff |
2014-12-23 |
Jozef Kolek | [mips][microMIPS] Implement LWSP and SWSP instructions |
tree | commitdiff |
2014-12-23 |
Elena Demikhovsky | AVX-512: Added FMA instructions, intrinsics an tests... |
tree | commitdiff |
2014-12-23 |
Hal Finkel | [PowerPC] Don't mark the return-address slot as immutable |
tree | commitdiff |
2014-12-23 |
Elena Demikhovsky | AVX-512: BLENDM - fixed encoding of the broadcast version |
tree | commitdiff |
2014-12-23 |
Hal Finkel | [PowerPC] Don't attempt a 64-bit pow2 division on PPC32 |
tree | commitdiff |
2014-12-23 |
Ahmed Bougacha | [ARM] Don't break alignment when combining base updates... |
tree | commitdiff |
2014-12-23 |
Alexey Samsonov | Fix UBSan bootstrap: replace shift of negative value... |
tree | commitdiff |
2014-12-23 |
Jim Grosbach | X86: Don't over-align combined loads. |
tree | commitdiff |
2014-12-22 |
Reid Kleckner | Make musttail more robust for vector types on x86 |
tree | commitdiff |
2014-12-22 |
Adrian Prantl | Thumb1 frame lowering: Mark CFI instructions with the... |
tree | commitdiff |
2014-12-22 |
Colin LeMahieu | [Hexagon] Adding memb instruction. Fixing whitespace... |
tree | commitdiff |
2014-12-22 |
Colin LeMahieu | [Hexagon] Adding classes and load unsigned byte instruc... |
tree | commitdiff |
2014-12-22 |
Bruno Cardoso Lopes | [x86] Add vector @llvm.ctpop intrinsic custom lowering |
tree | commitdiff |
2014-12-22 |
Elena Demikhovsky | AVX-512: Added all forms of BLENDM instructions, |
tree | commitdiff |
2014-12-22 |
Karthik Bhat | Lower multiply-negate operation to mneg on AArch64 |
tree | commitdiff |
2014-12-21 |
Craig Topper | [X86] Add hasSideEffects = 0 to CALLpcrel16. This match... |
tree | commitdiff |
2014-12-21 |
Matt Arsenault | Enable (sext x) == C --> x == (trunc C) combine |
tree | commitdiff |
2014-12-20 |
Craig Topper | [X86] Swap operand order in Intel syntax on a bunch... |
tree | commitdiff |
2014-12-20 |
Craig Topper | [X86] Swap operand order of imul aliases in Intel synta... |
tree | commitdiff |
2014-12-20 |
Craig Topper | [X86] Remove '*' from asm strings in far call/jump... |
tree | commitdiff |
2014-12-20 |
Craig Topper | [X86] Don't swap the order of segment and offset in... |
tree | commitdiff |
2014-12-20 |
Saleem Abdulrasool | ARM: further improve deprecated diagnosis (LDM) |
tree | commitdiff |
2014-12-20 |
Craig Topper | [X86] Immediate forms of far call/jump are not valid... |
tree | commitdiff |
2014-12-20 |
Eric Christopher | Remove unused variable and initialization. |
tree | commitdiff |
2014-12-19 |
Eric Christopher | Remove unused variable, initializer, and accessor. |
tree | commitdiff |
2014-12-19 |
Matt Arsenault | R600: Remove outdated comment |
tree | commitdiff |
2014-12-19 |
Elena Demikhovsky | Masked load and store codegen - fixed 128-bit vectors |
tree | commitdiff |
2014-12-19 |
Matt Arsenault | R600/SI: Only form min/max with 1 use. |
tree | commitdiff |
2014-12-19 |
Reid Kleckner | Add the ExceptionHandling::MSVC enumeration |
tree | commitdiff |
2014-12-19 |
Sanjay Patel | Model sqrtss as a binary operation with one source... |
tree | commitdiff |
2014-12-19 |
Tom Stellard | R600/SI: isLegalOperand() shouldn't check constant... |
tree | commitdiff |
2014-12-19 |
Tom Stellard | R600/SI: Make sure non-inline constants aren't folded... |
tree | commitdiff |
2014-12-19 |
Colin LeMahieu | [Hexagon] Removing old variants of instructions and... |
tree | commitdiff |
2014-12-19 |
Colin LeMahieu | [Hexagon] Adding bit extraction and table indexing... |
tree | commitdiff |
2014-12-19 |
Colin LeMahieu | [Hexagon] Adding bit insertion instructions. |
tree | commitdiff |
2014-12-19 |
Colin LeMahieu | [Hexagon] Adding more xtype shift instructions. |
tree | commitdiff |
2014-12-19 |
Colin LeMahieu | [Hexagon] Adding xtype shift instructions. |
tree | commitdiff |
2014-12-19 |
Colin LeMahieu | [Hexagon] Adding transfers to and from control registers. |
tree | commitdiff |
2014-12-19 |
Colin LeMahieu | [Hexagon] Adding doubleregs for control registers.... |
tree | commitdiff |
2014-12-19 |
Tilmann Scheller | [ARM] Remove dead assignment. |
tree | commitdiff |
2014-12-19 |
Colin LeMahieu | [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. |
tree | commitdiff |
2014-12-18 |
Colin LeMahieu | Reverting 224550, was not ready for commit. |
tree | commitdiff |
2014-12-18 |
Colin LeMahieu | [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. |
tree | commitdiff |
2014-12-18 |
Jozef Kolek | [mips][microMIPS] Fix bugs related to atomic SC/LL... |
tree | commitdiff |
2014-12-18 |
Saleem Abdulrasool | ARM: fix an off-by-one in the register list access |
tree | commitdiff |
2014-12-18 |
Robert Khasanov | [AVX512] Enable FP arithmetic lowering for AVX512VL... |
tree | commitdiff |
2014-12-18 |
Saleem Abdulrasool | ARM: improve instruction validation for thumb mode |
tree | commitdiff |
2014-12-18 |
Craig Topper | [PowerPC] Use MCPhysReg for tables of registers. Const... |
tree | commitdiff |
2014-12-18 |
Craig Topper | [X86] Use correct opsize on indirect call and jump... |
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