[ARM] Don't break alignment when combining base updates into load/stores.
authorAhmed Bougacha <ahmed.bougacha@gmail.com>
Tue, 23 Dec 2014 06:07:31 +0000 (06:07 +0000)
committerAhmed Bougacha <ahmed.bougacha@gmail.com>
Tue, 23 Dec 2014 06:07:31 +0000 (06:07 +0000)
commitbc47ceef4361068e8f49cc26b95d3f343e1db611
tree05ffeac309e6bd8f0204883b9c04f31eb9d59c5c
parent2f6ad0c00f2506cc4c4e550be10a2a81ef24ca82
[ARM] Don't break alignment when combining base updates into load/stores.

r223862/r224203 tried to also combine base-updating load/stores.
There was a mistake there: the alignment was added as is as an operand to
the ARMISD::VLD/VST node.  However, the VLD/VST selection logic doesn't care
about less-than-standard alignment attributes.
For example, no matter the alignment of a v2i64 load (say 1), SelectVLD picks
VLD1q64 (because of the memory type).  But VLD1q64 ("vld1.64 {dXX, dYY}") is
8-aligned, per ARMARMv7a 3.2.1.
For the 1-aligned load, what we really want is VLD1q8.

This commit introduces bitcasts if necessary, and changes the vld/vst type to
one whose standard alignment matches the original load/store alignment.

Differential Revision: http://reviews.llvm.org/D6759

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224754 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMISelLowering.cpp
test/CodeGen/ARM/memcpy-inline.ll
test/CodeGen/ARM/vector-load.ll
test/CodeGen/ARM/vector-store.ll