ARM: fix an off-by-one in the register list access

Fix an off-by-one access introduced in 224502 for push.w and pop.w with single
register operands.  Add test cases for both scenarios.

Thanks to Asiri Rathnayake for pointing out the failure!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224521 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index e9860764962b3ce9f31f0f3737e05b449d18f28f..72b4fda3d073c24ded3adef21871c2b62523d309 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -6282,10 +6282,10 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
                    "writeback register not allowed in register list");
 
     if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
-      if (validatetLDMRegList(Inst, Operands, 4))
+      if (validatetLDMRegList(Inst, Operands, 3))
         return true;
     } else {
-      if (validatetSTMRegList(Inst, Operands, 4))
+      if (validatetSTMRegList(Inst, Operands, 3))
         return true;
     }
     break;

diff --git a/test/MC/ARM/thumb-load-store-multiple.s b/test/MC/ARM/thumb-load-store-multiple.s
index e00fc66e8f914fcd219f54071521ba7c7ab23f59..60d2ec3f733f37cbf71cf0a8730839f8af0f0060 100644 (file)
--- a/test/MC/ARM/thumb-load-store-multiple.s
+++ b/test/MC/ARM/thumb-load-store-multiple.s
@@ -1,4 +1,4 @@
-@ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null %s 2>&1 \
+@ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o - %s 2>&1 \
 @ RUN:     | FileCheck %s
 
        .syntax unified
@@ -69,10 +69,6 @@ push:
        .global pop
        .type pop,%function
 pop:
-       pop {sp}
-@ CHECK-NOT: error: SP may not be in the register list
-       pop {sp, pc}
-@ CHECK-NOT: error: SP may not be in the register list
        pop {lr, pc}
 @ CHECK: error: PC and LR may not be in the register list simultaneously
 @ CHECK: pop {lr, pc}
@@ -84,3 +80,15 @@ pop:
 @ CHECK: popeq {r1, pc}
 @ CHECK:     ^
 
+       .global valid
+       .type valid,%function
+valid:
+       pop {sp}
+@ CHECK: ldr sp, [sp], #4
+       pop {sp, pc}
+@ CHECK: pop.w {sp, pc}
+       push.w {r0}
+@ CHECK: str r0, [sp, #-4]
+       pop.w {r0}
+@ CHECK: ldr r0, [sp], #4
+