oota-llvm.git
9 years ago[x86] Prevent instruction selection of AVX512 cmp.ps/pd/ss/sd intrinsics with illegal...
Craig Topper [Sat, 27 Dec 2014 18:51:06 +0000 (18:51 +0000)]
[x86] Prevent instruction selection of AVX512 cmp.ps/pd/ss/sd intrinsics with illegal immediates. Forgot to do this when I did SSE/SSE2/AVX/AVX2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224887 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[x86] Assert on invalid immediates in the instruction printer for cmp.ps/pd/ss/sd...
Craig Topper [Sat, 27 Dec 2014 18:11:00 +0000 (18:11 +0000)]
[x86] Assert on invalid immediates in the instruction printer for cmp.ps/pd/ss/sd instead of truncating the immediate. The assembly parser and instruction selection shouldn't generate invalid immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224886 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[x86] Prevent llvm.x86.cmp.ps/pd/ss/sd from being selected with bad immediates. The...
Craig Topper [Sat, 27 Dec 2014 18:10:56 +0000 (18:10 +0000)]
[x86] Prevent llvm.x86.cmp.ps/pd/ss/sd from being selected with bad immediates. The frontend now checks this when the builtin is used. This will allow the instruction printer to not have to deal with invalid immediates on these instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224885 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[FastIsel][X86] Fix invalid register replacement for bool args
Keno Fischer [Sat, 27 Dec 2014 13:10:15 +0000 (13:10 +0000)]
[FastIsel][X86] Fix invalid register replacement for bool args

Summary:
Consider the following IR:

  %3 = load i8* undef
  %4 = trunc i8 %3 to i1
  %5 = call %jl_value_t.0* @foo(..., i1 %4, ...)
  ret %jl_value_t.0* %5

Bools (that are the result of direct truncs) are lowered as whatever
the argument to the trunc was and a "and 1", causing the part of the
MBB responsible for this argument to look something like this:

  %vreg8<def,tied1> = AND8ri %vreg7<kill,tied0>, 1, %EFLAGS<imp-def>; GR8:%vreg8,%vreg7

Later, when the load is lowered, it will insert

  %vreg15<def> = MOV8rm %vreg14, 1, %noreg, 0, %noreg; mem:LD1[undef] GR8:%vreg15 GR64:%vreg14

but remember to (at the end of isel) replace vreg7 by vreg15. Now for
the bug. In fast isel lowering, we mistakenly mark vreg8 as the result
of the load instead of the trunc. This adds a fixup to have
vreg8 replaced by whatever the result of the load is as well, so
we end up with

  %vreg15<def,tied1> = AND8ri %vreg15<kill,tied0>, 1, %EFLAGS<imp-def>; GR8:%vreg15

which is an SSA violation and causes problems later down the road.

This fixes PR21557.

Test Plan: Test test case from PR21557 is added to the test suite.

Reviewers: ributzka

Reviewed By: ributzka

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6245

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224884 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoConvert test to llvm-readobj. NFC.
Rafael Espindola [Fri, 26 Dec 2014 22:47:39 +0000 (22:47 +0000)]
Convert test to llvm-readobj. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224872 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding auto-incrementing loads with and without byte reversal.
Colin LeMahieu [Fri, 26 Dec 2014 21:09:25 +0000 (21:09 +0000)]
[Hexagon] Adding auto-incrementing loads with and without byte reversal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224871 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding locked loads.
Colin LeMahieu [Fri, 26 Dec 2014 20:42:27 +0000 (20:42 +0000)]
[Hexagon] Adding locked loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224870 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding deallocframe and circular addressing loads.
Colin LeMahieu [Fri, 26 Dec 2014 20:30:58 +0000 (20:30 +0000)]
[Hexagon] Adding deallocframe and circular addressing loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224869 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding remaining post-increment instruction variants. Removing unused...
Colin LeMahieu [Fri, 26 Dec 2014 19:31:46 +0000 (19:31 +0000)]
[Hexagon] Adding remaining post-increment instruction variants.  Removing unused classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224868 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding post-increment unsigned byte loads.
Colin LeMahieu [Fri, 26 Dec 2014 19:12:11 +0000 (19:12 +0000)]
[Hexagon] Adding post-increment unsigned byte loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224867 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding post-increment signed byte loads with tests.
Colin LeMahieu [Fri, 26 Dec 2014 18:57:13 +0000 (18:57 +0000)]
[Hexagon] Adding post-increment signed byte loads with tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224866 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse llvm-readobj. NFC.
Rafael Espindola [Fri, 26 Dec 2014 18:22:05 +0000 (18:22 +0000)]
Use llvm-readobj. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224864 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Add the debug registers DR8-DR15 so we can assemble and disassemble references...
Craig Topper [Fri, 26 Dec 2014 18:20:05 +0000 (18:20 +0000)]
[X86] Add the debug registers DR8-DR15 so we can assemble and disassemble references to them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224862 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. Similar fix...
Craig Topper [Fri, 26 Dec 2014 18:19:44 +0000 (18:19 +0000)]
[X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. Similar fix to not fail to disassembler CR9-CR15 references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224861 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoBand-aid fix for PR22032: don't emit DWARF debug info if AddressSanitizer is enabled...
Timur Iskhodzhanov [Fri, 26 Dec 2014 17:00:51 +0000 (17:00 +0000)]
Band-aid fix for PR22032: don't emit DWARF debug info if AddressSanitizer is enabled on Windows

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224860 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoNo need to run llvm-as. NFC.
Rafael Espindola [Fri, 26 Dec 2014 16:42:47 +0000 (16:42 +0000)]
No need to run llvm-as. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224859 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoInstCombine: Infer nuw for multiplies
David Majnemer [Fri, 26 Dec 2014 09:50:35 +0000 (09:50 +0000)]
InstCombine: Infer nuw for multiplies

A multiply cannot unsigned wrap if there are bitwidth, or more, leading
zero bits between the two operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224849 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoValueTracking: Small cleanup in ComputeNumSignBits
David Majnemer [Fri, 26 Dec 2014 09:20:17 +0000 (09:20 +0000)]
ValueTracking: Small cleanup in ComputeNumSignBits

Constant contains the isAllOnesValue and isNullValue predicates, not
ConstantInt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224848 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoInstCombe: Infer nsw for multiplies
David Majnemer [Fri, 26 Dec 2014 09:10:14 +0000 (09:10 +0000)]
InstCombe: Infer nsw for multiplies

We already utilize this logic for reducing overflow intrinsics, it makes
sense to reuse it for normal multiplies as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224847 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTeach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd instructions...
Craig Topper [Fri, 26 Dec 2014 06:36:28 +0000 (06:36 +0000)]
Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224846 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse MCPhysReg for table of register encodings.
Craig Topper [Fri, 26 Dec 2014 06:36:23 +0000 (06:36 +0000)]
Use MCPhysReg for table of register encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224845 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] [FastISel] i1 constants must be zero extended
Hal Finkel [Thu, 25 Dec 2014 23:08:25 +0000 (23:08 +0000)]
[PowerPC] [FastISel] i1 constants must be zero extended

When materializing constant i1 values, they must be zero extended. We represent
i1 values as [0, 1], not [0, -1], in i32 registers. As it turns out, this code
path was dead for i1 values prior to r216006 (which is why this did not manifest in
miscompiles until recently).

Fixes -O0 self-hosting on PPC64/Linux.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224842 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSilence GCC's -Wparentheses warning
David Majnemer [Thu, 25 Dec 2014 10:03:23 +0000 (10:03 +0000)]
Silence GCC's -Wparentheses warning

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224833 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDocumentation for Masked Load and Store intrinsics.
Elena Demikhovsky [Thu, 25 Dec 2014 09:29:13 +0000 (09:29 +0000)]
Documentation for Masked Load and Store intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224832 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMasked Load/Store - Changed the order of parameters in intrinsics.
Elena Demikhovsky [Thu, 25 Dec 2014 07:49:20 +0000 (07:49 +0000)]
Masked Load/Store - Changed the order of parameters in intrinsics.
No functional changes.
The documentation is coming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224829 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoCodeGen: Error on redefinitions instead of asserting
David Majnemer [Wed, 24 Dec 2014 23:06:55 +0000 (23:06 +0000)]
CodeGen: Error on redefinitions instead of asserting

It's possible to have a prior definition of a symbol in module asm.
Raise an error instead of crashing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224828 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoCodeGen: Allow aliases to be overridden by variables
David Majnemer [Wed, 24 Dec 2014 22:44:29 +0000 (22:44 +0000)]
CodeGen: Allow aliases to be overridden by variables

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224827 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMC: address some comments in deprecation checks
Saleem Abdulrasool [Wed, 24 Dec 2014 18:40:42 +0000 (18:40 +0000)]
MC: address some comments in deprecation checks

Bob Wilson pointed out the unnecessary checks that had been committed to the
instruction check predicates.  The check was meant to ensure that the check was
not accidentally applied to non-ARM instructions.  This is better served as an
assertion rather than a condition check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224825 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMC: Label definitions are permitted after .set directives
David Majnemer [Wed, 24 Dec 2014 10:27:50 +0000 (10:27 +0000)]
MC: Label definitions are permitted after .set directives

.set directives may be overridden by other .set directives as well as
label definitions.

This fixes PR22019.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224811 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoIAS: correct debug line info for asm macros
Saleem Abdulrasool [Wed, 24 Dec 2014 06:32:43 +0000 (06:32 +0000)]
IAS: correct debug line info for asm macros

Correct the line information generation for preprocessed assembly.  Although we
tracked the source information for the macro instantiation, we failed to account
for the fact that we were instantiating a macro, which is populated into a new
buffer and that the line information would be relative to the definition rather
than the actual instantiation location.  This could cause the line number
associated with the statement to be very high due to wrapping of the difference
calculated for the preprocessor line information emitted into the stream.
Properly calculate the line for the macro instantiation, referencing the line
where the macro is actually used as GCC/gas do.

The test case uses x86, though the same problem exists on any other target using
the LLVM IAS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224810 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Remove the single AdSize indicator and replace it with separate AdSize16/32...
Craig Topper [Wed, 24 Dec 2014 06:05:22 +0000 (06:05 +0000)]
[X86] Remove the single AdSize indicator and replace it with separate AdSize16/32/64 flags.

This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224809 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMC: Don't emit .no_dead_strip on targets which don't support it
David Majnemer [Wed, 24 Dec 2014 04:11:42 +0000 (04:11 +0000)]
MC: Don't emit .no_dead_strip on targets which don't support it

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224808 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoLiveInterval: Remove accidentally committed debug code.
Matthias Braun [Wed, 24 Dec 2014 02:35:07 +0000 (02:35 +0000)]
LiveInterval: Remove accidentally committed debug code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224807 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoLiveInterval: Introduce createMainRangeFromSubranges().
Matthias Braun [Wed, 24 Dec 2014 02:11:51 +0000 (02:11 +0000)]
LiveInterval: Introduce createMainRangeFromSubranges().

This function constructs the main liverange by merging all subranges if
subregister liveness tracking is available. This should be slightly
faster to compute instead of performing the liveness calculation again
for the main range. More importantly it avoids cases where the main
liverange would cover positions where no subrange was live. These cases
happened for partial definitions where the actual defined part was dead
and only the undefined parts used later.

The register coalescing requires that every part covered by the main
live range has at least one subrange live.

I also expect this function to become usefull later for places where the
subranges are modified in a way that it is hard to correctly fix the
main liverange in the machine scheduler, we can simply reconstruct it
from subranges then.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224806 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRegisterCoalescer: With subrange liveness there may be no RedefVNI for unused lanes.
Matthias Braun [Wed, 24 Dec 2014 02:11:48 +0000 (02:11 +0000)]
RegisterCoalescer: With subrange liveness there may be no RedefVNI for unused lanes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224805 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoLiveRangeEdit: Check for completely empy subranges after removing ValNos.
Matthias Braun [Wed, 24 Dec 2014 02:11:46 +0000 (02:11 +0000)]
LiveRangeEdit: Check for completely empy subranges after removing ValNos.

Completely empty subranges are not allowed and must be removed when
subreg liveness is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224804 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoLiveIntervalAnalysis: Fix performance bug that I introduced in r224663.
Matthias Braun [Wed, 24 Dec 2014 02:11:43 +0000 (02:11 +0000)]
LiveIntervalAnalysis: Fix performance bug that I introduced in r224663.

Without a reference the code did not remember when moving the iterators
of the subranges/registerunit ranges forward and instead would scan from
the beginning again at the next position.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224803 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[OCaml] PR21901: Update tests.
Peter Zotov [Wed, 24 Dec 2014 01:58:45 +0000 (01:58 +0000)]
[OCaml] PR21901: Update tests.

This finishes the fix partially applied by r224782.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224802 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[OCaml] Expose Llvm_executionengine.get_{global_value,function}_address.
Peter Zotov [Wed, 24 Dec 2014 01:52:51 +0000 (01:52 +0000)]
[OCaml] Expose Llvm_executionengine.get_{global_value,function}_address.

Patch by Ramkumar Ramachandra <artagnon@gmail.com>.

Also remove Llvm_executionengine.get_pointer_to_global, as it
is actually deprecated and didn't appear in a stable release.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224801 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SROA] Update the documentation and names for accessing the slices
Chandler Carruth [Wed, 24 Dec 2014 01:48:09 +0000 (01:48 +0000)]
[SROA] Update the documentation and names for accessing the slices
within a partition of an alloca in SROA.

This reflects the fact that the organization of the slices isn't really
ideal for analysis, but is the naive way in which the slices are
available while we're processing them in the core partitioning
algorithm.

It is possible we could improve matters, and I've left a FIXME with
one of my ideas for how to do this, but it is a lot of work, the benefit
is somewhat minor, and it isn't clear that it would be strictly better.
=/ Not really satisfying, but I'm out of really good ideas.

This also improves one place where the debug logging failed to mark some
split partitions. Now we log in one place, slightly later, and with
accurate information about whether the slice is split by the partition
being rewritten.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224800 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDebug Info: In symmetry to DW_TAG_pointer_type, do not emit the byte size
Adrian Prantl [Wed, 24 Dec 2014 01:17:51 +0000 (01:17 +0000)]
Debug Info: In symmetry to DW_TAG_pointer_type, do not emit the byte size
of a DW_TAG_ptr_to_member_type.
This restores the behavior from before r224780-r224781.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224799 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SROA] Refactor the integer and vector promotion testing logic to
Chandler Carruth [Wed, 24 Dec 2014 01:05:14 +0000 (01:05 +0000)]
[SROA] Refactor the integer and vector promotion testing logic to
operate in terms of the new Partition class, and generally have a more
clear set of arguments. No functionality changed.

The most notable improvements here are consistently using the
terminology of 'partition' for a collection of slices that will be
rewritten together and 'slice' for a region of an alloca that is used by
a particular instruction.

This also makes it more clear that the split things are actually slices
as well, just ones that will be split by the proposed partition.

This doesn't yet address the confusing aspects of the partition's
interface where slices that will be split by the partition and start
prior to the partition are accesssed via Partition::splitSlices() while
the core range of slices exposed by a Partition includes both unsplit
slices and slices which will be split by the end, but started within the
offset range of the partition. This is particularly hard to address
because the algorithm which computes partitions quite literally doesn't
know which slices these will end up being until too late. I'm looking at
whether I can fix that or not, but I'm not optimistic. I'll update the
comments and/or names to further explain this either way. I've also
added one FIXME in this patch relating to this confusion so that I don't
forget about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224798 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Removing old classes.
Colin LeMahieu [Wed, 24 Dec 2014 00:43:00 +0000 (00:43 +0000)]
[Hexagon] Removing old classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224795 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAnother attempt to fix the LLVM Windows build bot lld-x86_64-win7, one last place...
Kevin Enderby [Wed, 24 Dec 2014 00:16:51 +0000 (00:16 +0000)]
Another attempt to fix the LLVM Windows build bot lld-x86_64-win7, one last place to fix I think.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224794 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAttempt to fix the LLVM Windows build bot lld-x86_64-win7.
Kevin Enderby [Tue, 23 Dec 2014 23:43:59 +0000 (23:43 +0000)]
Attempt to fix the LLVM Windows build bot lld-x86_64-win7.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224793 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd printing the LC_THREAD load commands with llvm-objdump’s -private-headers.
Kevin Enderby [Tue, 23 Dec 2014 22:56:39 +0000 (22:56 +0000)]
Add printing the LC_THREAD load commands with llvm-objdump’s -private-headers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224792 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[asan] change the coverage collection scheme so that we can easily emit coverage...
Kostya Serebryany [Tue, 23 Dec 2014 22:32:17 +0000 (22:32 +0000)]
[asan] change the coverage collection scheme so that we can easily emit coverage for the entire process as a single bit set, and if coverage_bitset=1 actually emit that bitset

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224789 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Ensure that the TOC reload directly follows bctrl on PPC64
Hal Finkel [Tue, 23 Dec 2014 22:29:40 +0000 (22:29 +0000)]
[PowerPC] Ensure that the TOC reload directly follows bctrl on PPC64

On non-Darwin PPC64, the TOC reload needs to come directly after the bctrl
instruction (for indirect calls) because the 'bctrl/ld 2, 40(1)' instruction
sequence is interpreted by the unwinding code in libgcc. To make sure these
occur as a pair, as with other pairings interpreted by the linker, fuse the two
instructions into one instruction (for code generation only).

In the future, we might wish to do this by emitting CFI directives instead,
but this solution is simpler, and mirrors what GCC does. Additional discussion
on this point is contained in the PR.

Fixes PR22015.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224788 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding doubleword load.
Colin LeMahieu [Tue, 23 Dec 2014 20:44:59 +0000 (20:44 +0000)]
[Hexagon] Adding doubleword load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224787 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Reapplying 224775 load words.
Colin LeMahieu [Tue, 23 Dec 2014 20:02:16 +0000 (20:02 +0000)]
[Hexagon] Reapplying 224775 load words.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224786 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions
Jozef Kolek [Tue, 23 Dec 2014 19:55:34 +0000 (19:55 +0000)]
[mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions

Differential Revision: http://reviews.llvm.org/D5204

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224785 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoReverting 224775 until mayLoad flag is addressed.
Colin LeMahieu [Tue, 23 Dec 2014 19:22:59 +0000 (19:22 +0000)]
Reverting 224775 until mayLoad flag is addressed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224783 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFinish removing DestroySource.
Rafael Espindola [Tue, 23 Dec 2014 19:16:45 +0000 (19:16 +0000)]
Finish removing DestroySource.

Fixes pr21901.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224782 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDIBuilder: Similar to createPointerType, make createMemberPointerType take
Adrian Prantl [Tue, 23 Dec 2014 19:11:47 +0000 (19:11 +0000)]
DIBuilder: Similar to createPointerType, make createMemberPointerType take
a size and alignment. Several assertions in DwarfDebug rely on all variable
types to report back a size, or to be derived from a type with a size.

Tested in CFE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224780 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAlways assert in DAGCombine and not only when -debug is enabled
Mehdi Amini [Tue, 23 Dec 2014 18:59:02 +0000 (18:59 +0000)]
Always assert in DAGCombine and not only when -debug is enabled

Right now in DAG Combine check the validity of the returned type
only when -debug is given on the command line. However usually
the test cases in the validation does not use -debug.
An Assert build should always check this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224779 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoPass LSAN_OPTIONS down so that it is possible to add suppressions.
Rafael Espindola [Tue, 23 Dec 2014 18:39:02 +0000 (18:39 +0000)]
Pass LSAN_OPTIONS down so that it is possible to add suppressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224777 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix a leak found by asan.
Rafael Espindola [Tue, 23 Dec 2014 18:18:37 +0000 (18:18 +0000)]
Fix a leak found by asan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224776 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding word loads.
Colin LeMahieu [Tue, 23 Dec 2014 18:06:56 +0000 (18:06 +0000)]
[Hexagon] Adding word loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224775 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding signed halfword loads.
Colin LeMahieu [Tue, 23 Dec 2014 17:25:57 +0000 (17:25 +0000)]
[Hexagon] Adding signed halfword loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224774 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix a leak found by asan.
Rafael Espindola [Tue, 23 Dec 2014 17:20:23 +0000 (17:20 +0000)]
Fix a leak found by asan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224773 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding unsigned halfword load.
Colin LeMahieu [Tue, 23 Dec 2014 16:42:57 +0000 (16:42 +0000)]
[Hexagon] Adding unsigned halfword load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224772 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips][microMIPS] Implement LWSP and SWSP instructions
Jozef Kolek [Tue, 23 Dec 2014 16:16:33 +0000 (16:16 +0000)]
[mips][microMIPS] Implement LWSP and SWSP instructions

Differential Revision: http://reviews.llvm.org/D6416

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224771 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[OCaml] PR22014: OCaml bindings didn't link to libLLVM-*.so with -Wl,--as-needed
Peter Zotov [Tue, 23 Dec 2014 13:09:59 +0000 (13:09 +0000)]
[OCaml] PR22014: OCaml bindings didn't link to libLLVM-*.so with -Wl,--as-needed

Patch by Evangelos Foutras <evangelos@foutrelis.com>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224766 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ValueTracking] Move GlobalAlias handling to be after the max depth check in computeK...
Michael Kuperstein [Tue, 23 Dec 2014 11:33:41 +0000 (11:33 +0000)]
[ValueTracking] Move GlobalAlias handling to be after the max depth check in computeKnownBits()

GlobalAlias handling used to be after GlobalValue handling, which meant it was, in practice, dead code. r220165 moved GlobalAlias handling to be before GlobalValue handling, but also moved it to be before the max depth check, causing an assert due to a recursion depth limit violation.

This moves GlobalAlias handling forward to where it's safe, and changes the GlobalValue handling to only look at GlobalObjects.

Differential Revision: http://reviews.llvm.org/D6758

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224765 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAVX-512: Added FMA instructions, intrinsics an tests for KNL and SKX targets
Elena Demikhovsky [Tue, 23 Dec 2014 10:30:39 +0000 (10:30 +0000)]
AVX-512: Added FMA instructions, intrinsics an tests for KNL and SKX targets

by Asaf Badouh

http://reviews.llvm.org/D6456

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224764 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Don't mark the return-address slot as immutable
Hal Finkel [Tue, 23 Dec 2014 09:45:06 +0000 (09:45 +0000)]
[PowerPC] Don't mark the return-address slot as immutable

It is tempting to mark the fixed stack slot used to store the return address as
immutable when lowering @llvm.returnaddress(i32 0). Unfortunately, within the
function, it is not completely immutable: it is written during the function
prologue. When using post-RA instruction scheduling, the prologue instructions
are available for scheduling, and we're not free to interchange the order of a
particular store in the prologue with loads from that stack location.

Fixes PR21976.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224761 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAVX-512: BLENDM - fixed encoding of the broadcast version
Elena Demikhovsky [Tue, 23 Dec 2014 09:36:28 +0000 (09:36 +0000)]
AVX-512: BLENDM - fixed encoding of the broadcast version
Added more intrinsics and encoding tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224760 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[DagCombine] Improve DAGCombiner BUILD_VECTOR when it has two sources of elements
Michael Kuperstein [Tue, 23 Dec 2014 08:59:45 +0000 (08:59 +0000)]
[DagCombine] Improve DAGCombiner BUILD_VECTOR when it has two sources of elements

This partially fixes PR21943.

For AVX, we go from:

vmovq   (%rsi), %xmm0
vmovq   (%rdi), %xmm1
vpermilps       $-27, %xmm1, %xmm2 ## xmm2 = xmm1[1,1,2,3]
vinsertps       $16, %xmm2, %xmm1, %xmm1 ## xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
vinsertps       $32, %xmm0, %xmm1, %xmm1 ## xmm1 = xmm1[0,1],xmm0[0],xmm1[3]
vpermilps       $-27, %xmm0, %xmm0 ## xmm0 = xmm0[1,1,2,3]
vinsertps       $48, %xmm0, %xmm1, %xmm0 ## xmm0 = xmm1[0,1,2],xmm0[0]

To the expected:

vmovq   (%rdi), %xmm0
vmovhpd (%rsi), %xmm0, %xmm0
retq

Fixing this for AVX2 is still open.

Differential Revision: http://reviews.llvm.org/D6749

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224759 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Don't attempt a 64-bit pow2 division on PPC32
Hal Finkel [Tue, 23 Dec 2014 08:38:50 +0000 (08:38 +0000)]
[PowerPC] Don't attempt a 64-bit pow2 division on PPC32

In r224033, in moving the signed power-of-2 division expansion into
BuildSDIVPow2, I accidentally made it possible to attempt the lowering for a
64-bit division on PPC32. This later asserts.

Fixes PR21928.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224758 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SimplifyCFG] Revise common code sinking
Michael Liao [Tue, 23 Dec 2014 08:26:55 +0000 (08:26 +0000)]
[SimplifyCFG] Revise common code sinking

- Fix the case where more than 1 common instructions derived from the same
  operand cannot be sunk. When a pair of value has more than 1 derived values
  in both branches, only 1 derived value could be sunk.
- Replace BB1 -> (BB2, PN) map with joint value map, i.e.
  map of (BB1, BB2) -> PN, which is more accurate to track common ops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224757 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove a bad cast in CloneModule()
Michael Kuperstein [Tue, 23 Dec 2014 08:23:45 +0000 (08:23 +0000)]
Remove a bad cast in CloneModule()

A cast that was introduced in r209007 was accidentally left in after the changes made to GlobalAlias rules in r210062. This crashes if the aliasee is a now-leggal ConstantExpr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224756 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ARM] Don't break alignment when combining base updates into load/stores.
Ahmed Bougacha [Tue, 23 Dec 2014 06:07:31 +0000 (06:07 +0000)]
[ARM] Don't break alignment when combining base updates into load/stores.

r223862/r224203 tried to also combine base-updating load/stores.
There was a mistake there: the alignment was added as is as an operand to
the ARMISD::VLD/VST node.  However, the VLD/VST selection logic doesn't care
about less-than-standard alignment attributes.
For example, no matter the alignment of a v2i64 load (say 1), SelectVLD picks
VLD1q64 (because of the memory type).  But VLD1q64 ("vld1.64 {dXX, dYY}") is
8-aligned, per ARMARMv7a 3.2.1.
For the 1-aligned load, what we really want is VLD1q8.

This commit introduces bitcasts if necessary, and changes the vld/vst type to
one whose standard alignment matches the original load/store alignment.

Differential Revision: http://reviews.llvm.org/D6759

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224754 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix UBSan bootstrap: replace shift of negative value with multiplication.
Alexey Samsonov [Tue, 23 Dec 2014 04:15:53 +0000 (04:15 +0000)]
Fix UBSan bootstrap: replace shift of negative value with multiplication.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224752 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix UBSan bootstrap: don't bind reference to nullptr.
Alexey Samsonov [Tue, 23 Dec 2014 04:15:47 +0000 (04:15 +0000)]
Fix UBSan bootstrap: don't bind reference to nullptr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224751 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert r224739: Debug info: Teach SROA how to update debug info for
Chandler Carruth [Tue, 23 Dec 2014 02:58:14 +0000 (02:58 +0000)]
Revert r224739: Debug info: Teach SROA how to update debug info for
fragmented variables.

This caused codegen to start crashing when we built somewhat large
programs with debug info and optimizations. 'check-msan' hit in, and
I suspect a bootstrap would as well. I mailed a test case to the
review thread.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224750 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoX86: Don't over-align combined loads.
Jim Grosbach [Tue, 23 Dec 2014 00:35:23 +0000 (00:35 +0000)]
X86: Don't over-align combined loads.

When combining consecutive loads+inserts into a single vector load,
we should keep the alignment of the base load. Doing otherwise can, and does,
lead to using overly aligned instructions. In the included test case, for
example, using a 32-byte vmovaps on a 16-byte aligned value. Oops.

rdar://19190968

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224746 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMake musttail more robust for vector types on x86
Reid Kleckner [Mon, 22 Dec 2014 23:58:37 +0000 (23:58 +0000)]
Make musttail more robust for vector types on x86

Previously I tried to plug musttail into the existing vararg lowering
code. That turned out to be a mistake, because non-vararg calls use
significantly different register lowering, even on x86. For example, AVX
vectors are usually passed in registers to normal functions and memory
to vararg functions.  Now musttail uses a completely separate lowering.

Hopefully this can be used as the basis for non-x86 perfect forwarding.

Reviewers: majnemer

Differential Revision: http://reviews.llvm.org/D6156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224745 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove dynamic allocation/indirection from GCOVBlocks owned by GCOVFunction
David Blaikie [Mon, 22 Dec 2014 23:12:42 +0000 (23:12 +0000)]
Remove dynamic allocation/indirection from GCOVBlocks owned by GCOVFunction

Since these are all created in the DenseMap before they are referenced,
there's no problem with pointer validity by the time it's required. This
removes another use of DeleteContainerSeconds/manual memory management
which I'm cleaning up from time to time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224744 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoThumb1 frame lowering: Mark CFI instructions with the FrameSetup flag.
Adrian Prantl [Mon, 22 Dec 2014 23:09:14 +0000 (23:09 +0000)]
Thumb1 frame lowering: Mark CFI instructions with the FrameSetup flag.

Followup to r224294:

ARM/AArch64: Attach the FrameSetup MIFlag to CFI instructions.
Debug info marks the first instruction without the FrameSetup flag
as being the end of the function prologue. Any CFI instructions in the
middle of the function prologue would cause debug info to end the prologue
too early and worse, attach the line number of the CFI instruction, which
incidentally is often 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224743 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SROA] Lift the logic for traversing the alloca slices one partition at
Chandler Carruth [Mon, 22 Dec 2014 22:46:00 +0000 (22:46 +0000)]
[SROA] Lift the logic for traversing the alloca slices one partition at
a time into a partition iterator and a Partition class.

There is a lot of knock-on simplification that this enables, largely
stemming from having a Partition object to refer to in lots of helpers.
I've only done a minimal amount of that because enoguh stuff is changing
as-is in this commit.

This shouldn't change any observable behavior. I've worked hard to
preserve the *exact* traversal semantics which were originally present
even though some of them make no sense. I'll be changing some of this in
subsequent commits now that the logic is carefully factored into
a reusable place.

The primary motivation for this change is to break the rewriting into
phases in order to support more intelligent rewriting. For example, I'm
planning to change how split loads and stores are rewritten to remove
the significant overuse of integer bit packing in the resulting code and
allow more effective secondary splitting of aggregates. For any of this
to work, they have to share the exact traversal logic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224742 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LCSSA] Handle PHI insertion in disjoint loops
Bruno Cardoso Lopes [Mon, 22 Dec 2014 22:35:46 +0000 (22:35 +0000)]
[LCSSA] Handle PHI insertion in disjoint loops

Take two disjoint Loops L1 and L2.

LoopSimplify fails to simplify some loops (e.g. when indirect branches
are involved). In such situations, it can happen that an exit for L1 is
the header of L2. Thus, when we create PHIs in one of such exits we are
also inserting PHIs in L2 header.

This could break LCSSA form for L2 because these inserted PHIs can also
have uses in L2 exits, which are never handled in the current
implementation. Provide a fix for this corner case and test that we
don't assert/crash on that.

Differential Revision: http://reviews.llvm.org/D6624

rdar://problem/19166231

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224740 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDebug info: Teach SROA how to update debug info for fragmented variables.
Adrian Prantl [Mon, 22 Dec 2014 22:26:00 +0000 (22:26 +0000)]
Debug info: Teach SROA how to update debug info for fragmented variables.
This allows us to generate debug info for extremely advanced code such as

  typedef struct { long int a; int b;} S;

  int foo(S s) {
    return s.b;
  }

which at -O1 on x86_64 is codegen'd into

  define i32 @foo(i64 %s.coerce0, i32 %s.coerce1) #0 {
    ret i32 %s.coerce1, !dbg !24
  }

with this patch we emit the following debug info for this

  TAG_formal_parameter [3]
    AT_location( 0x00000000
                 0x0000000000000000 - 0x0000000000000006: rdi, piece 0x00000008, rsi, piece 0x00000004
                 0x0000000000000006 - 0x0000000000000008: rdi, piece 0x00000008, rax, piece 0x00000004 )
                 AT_name( "s" )
                 AT_decl_file( "/Volumes/Data/llvm/_build.ninja.release/test.c" )

Thanks to chandlerc, dblaikie, and echristo for their feedback on all
previous iterations of this patch!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224739 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix Windows unwind info for functions in sections other than .text
Reid Kleckner [Mon, 22 Dec 2014 22:10:08 +0000 (22:10 +0000)]
Fix Windows unwind info for functions in sections other than .text

Previously we assumed the section name had the form .text$foo, which is
what we used to do for inline functions. If the dollar wasn't present,
we'd put unwind data in the .pdata and .xdata sections for the main
.text section, which is incorrect.

Fixes PR22001.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224738 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding memb instruction. Fixing whitespace in test from 224730.
Colin LeMahieu [Mon, 22 Dec 2014 21:40:43 +0000 (21:40 +0000)]
[Hexagon] Adding memb instruction.  Fixing whitespace in test from 224730.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224735 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse iterators rather than indices to make this forwards-compatible with a change...
David Blaikie [Mon, 22 Dec 2014 21:26:38 +0000 (21:26 +0000)]
Use iterators rather than indices to make this forwards-compatible with a change to the underlying container (to std::list)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224734 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agounique_ptrify MatchableInfo(const CodeGenInstAlias *Alias)'s parameter
David Blaikie [Mon, 22 Dec 2014 21:26:26 +0000 (21:26 +0000)]
unique_ptrify MatchableInfo(const CodeGenInstAlias *Alias)'s parameter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224733 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding classes and load unsigned byte instruction, updating usages.
Colin LeMahieu [Mon, 22 Dec 2014 21:20:03 +0000 (21:20 +0000)]
[Hexagon] Adding classes and load unsigned byte instruction, updating usages.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224730 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[x86] Add vector @llvm.ctpop intrinsic custom lowering
Bruno Cardoso Lopes [Mon, 22 Dec 2014 19:45:43 +0000 (19:45 +0000)]
[x86] Add vector @llvm.ctpop intrinsic custom lowering

Currently, when ctpop is supported for scalar types, the expansion of
@llvm.ctpop.vXiY uses vector element extractions, insertions and individual
calls to @llvm.ctpop.iY. When not, expansion with bit-math operations is used
for the scalar calls.

Local haswell measurements show that we can improve vector @llvm.ctpop.vXiY
expansion in some cases by using a using a vector parallel bit twiddling
approach, based on:

v = v - ((v >> 1) & 0x55555555);
v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
v = ((v + (v >> 4) & 0xF0F0F0F)
v = v + (v >> 8)
v = v + (v >> 16)
v = v & 0x0000003F
(from http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel)

When scalar ctpop isn't supported, the approach above performs better for
v2i64, v4i32, v4i64 and v8i32 (see numbers below). And even when scalar ctpop
is supported, this approach performs ~2x better for v8i32.

Here, x86_64 implies -march=corei7-avx without ctpop and x86_64h includes ctpop
support with -march=core-avx2.

== [x86_64h - new]
v8i32: 0.661685
v4i32: 0.514678
v4i64: 0.652009
v2i64: 0.324289
== [x86_64h - old]
v8i32: 1.29578
v4i32: 0.528807
v4i64: 0.65981
v2i64: 0.330707

== [x86_64 - new]
v8i32: 1.003
v4i32: 0.656273
v4i64: 1.11711
v2i64: 0.754064
== [x86_64 - old]
v8i32: 2.34886
v4i32: 1.72053
v4i64: 1.41086
v2i64: 1.0244

More work for other vector types will come next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224725 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove unused header. NFC.
Juergen Ributzka [Mon, 22 Dec 2014 19:09:15 +0000 (19:09 +0000)]
Remove unused header. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224722 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd a C++ marker to this header file.
Adrian Prantl [Mon, 22 Dec 2014 19:07:45 +0000 (19:07 +0000)]
Add a C++ marker to this header file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224721 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[C API] Expose LLVMGetGlobalValueAddress and LLVMGetFunctionAddress.
Peter Zotov [Mon, 22 Dec 2014 18:53:11 +0000 (18:53 +0000)]
[C API] Expose LLVMGetGlobalValueAddress and LLVMGetFunctionAddress.

Patch by Ramkumar Ramachandra <artagnon@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224720 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[CodeGenPrepare] Handle properly the promotion of operands when this does not
Quentin Colombet [Mon, 22 Dec 2014 18:11:52 +0000 (18:11 +0000)]
[CodeGenPrepare] Handle properly the promotion of operands when this does not
generate instructions.

Fixes PR21978.
Related to <rdar://problem/18310086>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224717 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAVX-512: Added all forms of BLENDM instructions,
Elena Demikhovsky [Mon, 22 Dec 2014 13:52:48 +0000 (13:52 +0000)]
AVX-512: Added all forms of BLENDM instructions,
intrinsics, encoding tests for AVX-512F and skx instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224707 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoLower multiply-negate operation to mneg on AArch64
Karthik Bhat [Mon, 22 Dec 2014 13:38:58 +0000 (13:38 +0000)]
Lower multiply-negate operation to mneg on AArch64

This patch pattern matches code such as-
neg  w8, w8
mul  w8, w9, w8
to
mneg  w8, w8, w9

Review: http://reviews.llvm.org/D6754

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224706 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoConvert a few tests to FileCheck. NFC.
Rafael Espindola [Mon, 22 Dec 2014 13:29:46 +0000 (13:29 +0000)]
Convert a few tests to FileCheck. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224705 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoThe leak detector is dead, long live asan and valgrind.
Rafael Espindola [Mon, 22 Dec 2014 13:00:36 +0000 (13:00 +0000)]
The leak detector is dead, long live asan and valgrind.

In resent times asan and valgrind have found way more memory management bugs
in llvm than the special purpose leak detector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224703 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoCodeGen: minor style tweaks to SSP
Saleem Abdulrasool [Sun, 21 Dec 2014 21:52:38 +0000 (21:52 +0000)]
CodeGen: minor style tweaks to SSP

Clean up some style related things in the StackProtector CodeGen.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224693 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Add hasSideEffects = 0 to CALLpcrel16. This matches what is inferred from patte...
Craig Topper [Sun, 21 Dec 2014 20:05:06 +0000 (20:05 +0000)]
[X86] Add hasSideEffects = 0 to CALLpcrel16. This matches what is inferred from patterns for the 32-bit version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224692 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoEnable (sext x) == C --> x == (trunc C) combine
Matt Arsenault [Sun, 21 Dec 2014 16:48:42 +0000 (16:48 +0000)]
Enable (sext x) == C --> x == (trunc C) combine

Extend the existing code which handles this for zext. This makes this
more useful for targets with ZeroOrNegativeOne BooleanContent and
obsoletes a custom combine SI uses for i1 setcc (sext(i1), 0, setne)
since the constant will now be shrunk to i1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224691 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Swap operand order in Intel syntax on a bunch of aliases.
Craig Topper [Sat, 20 Dec 2014 23:05:59 +0000 (23:05 +0000)]
[X86] Swap operand order in Intel syntax on a bunch of aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224687 91177308-0d34-0410-b5e6-96231b3b80d8