oota-llvm.git
7 years ago[libFuzzer] minimal documentation on data-flow-guided fuzzing
Kostya Serebryany [Fri, 31 Jul 2015 21:48:10 +0000 (21:48 +0000)]
[libFuzzer] minimal documentation on data-flow-guided fuzzing

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243793 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix an MSVC build break since it can't synthesize move ctors.
David Blaikie [Fri, 31 Jul 2015 21:47:07 +0000 (21:47 +0000)]
Fix an MSVC build break since it can't synthesize move ctors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243792 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix a GCC buildbot that seemed to be having trouble producing the implicit move ctor
David Blaikie [Fri, 31 Jul 2015 21:47:04 +0000 (21:47 +0000)]
Fix a GCC buildbot that seemed to be having trouble producing the implicit move ctor

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243791 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[NVPTX] convert pointers in byval kernel arguments to global
Jingyue Wu [Fri, 31 Jul 2015 21:44:14 +0000 (21:44 +0000)]
[NVPTX] convert pointers in byval kernel arguments to global

Summary:
For example, in

  struct S {
    int *x;
    int *y;
  };
  __global__ void foo(S s) {
    int *b = s.y;
    // use b
  }

"b" is guaranteed to point to global. NVPTX should emit ld.global/st.global for
accessing "b".

Reviewers: jholewinski

Subscribers: llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11505

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243790 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix some formatting from a recent commit.
David Blaikie [Fri, 31 Jul 2015 21:37:58 +0000 (21:37 +0000)]
Fix some formatting from a recent commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243789 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago-Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are deprecated...
David Blaikie [Fri, 31 Jul 2015 21:37:09 +0000 (21:37 +0000)]
-Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are deprecated in C++11

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243788 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago-Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are deprecated...
David Blaikie [Fri, 31 Jul 2015 21:26:16 +0000 (21:26 +0000)]
-Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are deprecated in C++11

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243786 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoWebAssembly: handle `ret void`.
JF Bastien [Fri, 31 Jul 2015 21:04:18 +0000 (21:04 +0000)]
WebAssembly: handle `ret void`.

Summary:
Use -1 as numoperands for the return SDTypeProfile, denoting that return is variadic. Note that the patterns in InstrControl.td still need to match the inputs, so this ins't an "anything goes" variadic on ret!

The next step will be to handle other local types (not just int32).

Reviewers: sunfish

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11692

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243783 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] make sure that 2-byte arguments of switch() are handled properly
Kostya Serebryany [Fri, 31 Jul 2015 20:58:55 +0000 (20:58 +0000)]
[libFuzzer] make sure that 2-byte arguments of switch() are handled properly

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243781 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Serialization: Serialize the floating point immediate machine operands.
Alex Lorenz [Fri, 31 Jul 2015 20:49:21 +0000 (20:49 +0000)]
MIR Serialization: Serialize the floating point immediate machine operands.

Reviewers: Duncan P. N. Exon Smith

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243780 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIR: Add a broad bitcode compatibility test
Duncan P. N. Exon Smith [Fri, 31 Jul 2015 20:44:32 +0000 (20:44 +0000)]
IR: Add a broad bitcode compatibility test

Successive versions of LLVM should retain the ability to parse bitcode
generated by old releases of the compiler.  This adds a bitcode format
compatibility test, which is intended to provide good (albeit not
entirely exhaustive) coverage of the current LangRef.

This also includes compatibility tests for LLVM 3.6.  After every 3.X.0
release, the compatibility.ll file from the 3.X branch should be copied
to compatibility-3.X.ll on trunk, and the 3.X.0 release used to generate
a corresponding bitcode file.

Patch by Vedant Kumar!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243779 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[dwarfdump] Ignore scattered relocations for mach-o.
Frederic Riss [Fri, 31 Jul 2015 20:22:50 +0000 (20:22 +0000)]
[dwarfdump] Ignore scattered relocations for mach-o.

When encountering a scattered relocation, the code would assert trying to
access an unexisting section. I couldn't find a way to expose the result
of the processing of a scattered reloc, and I'm really unsure what the
right thing to do is. This patch just skips them during the processing in
DwarfContext and adds a mach-o file to the tests that exposed the asserting
behavior.
(This is a new failure that is being exposed by Rafael's recent work on
the libObject interfaces. I think the wrong behavior has always happened,
but now it's asserting)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243778 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[dsymutil] Support multiple input files on the command line
Frederic Riss [Fri, 31 Jul 2015 20:22:20 +0000 (20:22 +0000)]
[dsymutil] Support multiple input files on the command line

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243777 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDI: Remove DW_TAG_arg_variable and DW_TAG_auto_variable
Duncan P. N. Exon Smith [Fri, 31 Jul 2015 18:58:39 +0000 (18:58 +0000)]
DI: Remove DW_TAG_arg_variable and DW_TAG_auto_variable

Remove the fake `DW_TAG_auto_variable` and `DW_TAG_arg_variable` tags,
using `DW_TAG_variable` in their place Stop exposing the `tag:` field at
all in the assembly format for `DILocalVariable`.

Most of the testcase updates were generated by the following sed script:

    find test/ -name "*.ll" -o -name "*.mir" |
    xargs grep -l 'DILocalVariable' |
    xargs sed -i '' \
      -e 's/tag: DW_TAG_arg_variable, //' \
      -e 's/tag: DW_TAG_auto_variable, //'

There were only a handful of tests in `test/Assembly` that I needed to
update by hand.

(Note: a follow-up could change `DILocalVariable::DILocalVariable()` to
set the tag to `DW_TAG_formal_parameter` instead of `DW_TAG_variable`
(as appropriate), instead of having that logic magically in the backend
in `DbgVariable`.  I've added a FIXME to that effect.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243774 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agox86: check hasOpaqueSPAdjustment in canRealignStack
JF Bastien [Fri, 31 Jul 2015 18:28:09 +0000 (18:28 +0000)]
x86: check hasOpaqueSPAdjustment in canRealignStack

Summary:
@rnk pointed out in [1] that x86's canRealignStack logic should match that in CantUseSP from hasBasePointer.

  [1]: http://reviews.llvm.org/D11160?id=29713#inline-89350

Reviewers: rnk

Subscribers: rnk, llvm-commits

Differential Revision: http://reviews.llvm.org/D11377

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243772 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoWebAssembly: handle unused function arguments.
JF Bastien [Fri, 31 Jul 2015 18:13:27 +0000 (18:13 +0000)]
WebAssembly: handle unused function arguments.

Subscribers: llvm-commits, sunfish, jfb

Differential Revision: http://reviews.llvm.org/D11684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243770 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAttempt to appease the MSVC build bots
David Majnemer [Fri, 31 Jul 2015 18:13:25 +0000 (18:13 +0000)]
Attempt to appease the MSVC build bots

They don't seem to care for initializing an ArrayRef with a
std::initializer_list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243769 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] record traces from the switch statements only when told to do so
Kostya Serebryany [Fri, 31 Jul 2015 18:09:08 +0000 (18:09 +0000)]
[libFuzzer] record traces from the switch statements only when told to do so

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243768 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoNew EH representation for MSVC compatibility
David Majnemer [Fri, 31 Jul 2015 17:58:14 +0000 (17:58 +0000)]
New EH representation for MSVC compatibility

This introduces new instructions neccessary to implement MSVC-compatible
exception handling support.  Most of the middle-end and none of the
back-end haven't been audited or updated to take them into account.

Differential Revision: http://reviews.llvm.org/D11097

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243766 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDI: Rewrite the DIBuilder local variable API
Duncan P. N. Exon Smith [Fri, 31 Jul 2015 17:55:53 +0000 (17:55 +0000)]
DI: Rewrite the DIBuilder local variable API

Replace the general `createLocalVariable()` with two more specific
functions: `createParameterVariable()` and `createAutoVariable()`, and
rewrite the documentation.

Besides cleaning up the API, this avoids exposing the fake DWARF tags
`DW_TAG_arg_variable` and `DW_TAG_auto_variable` to frontends, and is
preparation for removing them completely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243764 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoWebAssembly: print basic integer assembly.
JF Bastien [Fri, 31 Jul 2015 17:53:38 +0000 (17:53 +0000)]
WebAssembly: print basic integer assembly.

Summary:
This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats:

  - The operation names are currently incorrect.
  - Other integer and floating-point types will be added later.
  - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways.
  - The assembly format isn't full s-expressions yet either, this will be added later.
  - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter).

Reviewers: sunfish

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243763 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[COFF] Consider the ImageBase when reporting section addresses
David Majnemer [Fri, 31 Jul 2015 17:40:24 +0000 (17:40 +0000)]
[COFF] Consider the ImageBase when reporting section addresses

This lets us reenable the lld test disabled in r243758.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243761 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] support switch interception in dfsan mode
Kostya Serebryany [Fri, 31 Jul 2015 17:05:05 +0000 (17:05 +0000)]
[libFuzzer] support switch interception in dfsan mode

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243760 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CodeGenPrepare] Compress a pair. No functional change.
Benjamin Kramer [Fri, 31 Jul 2015 17:00:39 +0000 (17:00 +0000)]
[CodeGenPrepare] Compress a pair. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243759 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] reassociate integer multiplies using machine combiner pass
Sanjay Patel [Fri, 31 Jul 2015 16:21:55 +0000 (16:21 +0000)]
[x86] reassociate integer multiplies using machine combiner pass

Add i16, i32, i64 imul machine instructions to the list of reassociation
candidates.

A new bit of logic is needed to handle integer instructions: they have an
implicit EFLAGS operand, so we have to make sure it's dead in order to do
any reassociation with integer ops.

Differential Revision: http://reviews.llvm.org/D11660

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243756 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[COFF] Return symbol VAs instead of RVAs for PE files
Reid Kleckner [Fri, 31 Jul 2015 16:14:22 +0000 (16:14 +0000)]
[COFF] Return symbol VAs instead of RVAs for PE files

This makes llvm-nm consistent with binutils nm on executables and DLLs.
For a vanilla hello world executable, the address of main should include
the default image base of 0x400000.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243755 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Favor extended reg patterns for sub
Geoff Berry [Fri, 31 Jul 2015 15:55:54 +0000 (15:55 +0000)]
[AArch64] Favor extended reg patterns for sub

Summary:
Favor the extended reg patterns over the shifted reg patterns that match
only the operand shift and not the full sign/zero extend and shift.

Reviewers: jmolloy, t.p.northover

Subscribers: mcrosier, aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D11569

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243753 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agodon't repeat function names in comments; NFC
Sanjay Patel [Fri, 31 Jul 2015 15:10:44 +0000 (15:10 +0000)]
don't repeat function names in comments; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243751 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CaptureTracker] Provide an ordered basic block to PointerMayBeCapturedBefore
Bruno Cardoso Lopes [Fri, 31 Jul 2015 14:31:35 +0000 (14:31 +0000)]
[CaptureTracker] Provide an ordered basic block to PointerMayBeCapturedBefore

This patch is a follow up from r240560 and is a step further into
mitigating the compile time performance issues in CaptureTracker.

By providing the CaptureTracker with a "cached ordered basic block"
instead of computing it every time, MemDepAnalysis can use this cache
throughout its calls to AA->callCapturesBefore, avoiding to recompute it
for every scanned instruction. In the same testcase used in r240560,
compile time is reduced from 2min to 30s.

This also fixes PR22348.

rdar://problem/19230319
Differential Revision: http://reviews.llvm.org/D11364

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243750 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[regalloc] Make RegMask clobbers prevent merging vreg's into PhysRegs when hoisting...
Daniel Sanders [Fri, 31 Jul 2015 12:58:55 +0000 (12:58 +0000)]
[regalloc] Make RegMask clobbers prevent merging vreg's into PhysRegs when hoisting def's upwards.

Summary:
This prevents vreg260 and D7 from being merged in:
  %vreg260<def> = LDC1 ...
  JAL <ga:@sin>, <regmask ... list not containing D7 ...>
  %D7<def> = COPY %vreg260; ...
Doing so is not valid because the JAL clobbers the D7.

This fixes the almabench regression in the LLVM 3.7.0 release branch.

Reviewers: MatzeB

Subscribers: MatzeB, qcolombet, hans, llvm-commits

Differential Revision: http://reviews.llvm.org/D11649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243745 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRefactor: Simplify boolean conditional return statements in lib/Target/NVPTX
Jingyue Wu [Fri, 31 Jul 2015 05:09:47 +0000 (05:09 +0000)]
Refactor: Simplify boolean conditional return statements in lib/Target/NVPTX

Summary: Use clang-tidy to simplify boolean conditional return statements

Reviewers: rafael, echristo, chandlerc, bkramer, craig.topper, dexonsmith, chapuni, eliben, jingyue, jholewinski

Subscribers: llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D9983

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243734 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Fix v16i32 to v16i8 truncstore
Matt Arsenault [Fri, 31 Jul 2015 04:12:04 +0000 (04:12 +0000)]
AMDGPU: Fix v16i32 to v16i8 truncstore

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243731 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] trace switch statements and apply mutations based on the expected case...
Kostya Serebryany [Fri, 31 Jul 2015 01:33:06 +0000 (01:33 +0000)]
[libFuzzer] trace switch statements and apply mutations based on the expected case values

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243726 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoELFYAML: Enable parsing of EM_AMDGPU
Tom Stellard [Fri, 31 Jul 2015 01:15:15 +0000 (01:15 +0000)]
ELFYAML: Enable parsing of EM_AMDGPU

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11263

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243724 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Set DwarfRegNum
Matt Arsenault [Fri, 31 Jul 2015 01:12:10 +0000 (01:12 +0000)]
AMDGPU/SI: Set DwarfRegNum

This requires a fix in tablegen for the cast<int> from bits<16>
to work in the list initializer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243723 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTableGen: Support folding casts from bits to int
Matt Arsenault [Fri, 31 Jul 2015 01:12:06 +0000 (01:12 +0000)]
TableGen: Support folding casts from bits to int

This is to fix an incorrect error when trying to initialize
DwarfNumbers with a !cast<int> of a bits initializer.
getValuesAsListOfInts("DwarfNumbers") would not see an IntInit
and instead the cast, so would give up.

It seems likely that this could be generalized to attempt
the convertInitializerTo for any type. I'm not really sure
why the existing code seems to special case the string cast cases
when convertInitializerTo seems like it should generally handle this
sort of thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243722 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agodocs: Add information about helper scripts to HowToReleaseLLVM page
Tom Stellard [Fri, 31 Jul 2015 01:02:35 +0000 (01:02 +0000)]
docs: Add information about helper scripts to HowToReleaseLLVM page

Differential Revision: http://reviews.llvm.org/D10081

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243720 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Remove unused pattern for f32 constant loads
Tom Stellard [Fri, 31 Jul 2015 01:02:32 +0000 (01:02 +0000)]
AMDGPU/SI: Remove unused pattern for f32 constant loads

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11603

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243719 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Lower modulo operation to generate __aeabi_divmod on Android
Sumanth Gundapaneni [Fri, 31 Jul 2015 00:45:12 +0000 (00:45 +0000)]
[ARM] Lower modulo operation to generate __aeabi_divmod on Android

For a modulo (reminder) operation,
clang -target armv7-none-linux-gnueabi generates "__modsi3"
clang -target armv7-none-eabi generates "__aeabi_idivmod"
clang -target armv7-linux-androideabi generates "__modsi3"
Android bionic libc doesn't provide a __modsi3, instead it provides a
"__aeabi_idivmod". This patch fixes the LLVM ARMISelLowering to generate
the correct call when ever there is a modulo operation.

Differential Revision: http://reviews.llvm.org/D11661

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243717 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Parser: Report an error when a constant pool item is redefined.
Alex Lorenz [Thu, 30 Jul 2015 22:00:17 +0000 (22:00 +0000)]
MIR Parser: Report an error when a constant pool item is redefined.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243696 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Parser: Report an error when a virtual register is redefined.
Alex Lorenz [Thu, 30 Jul 2015 21:54:10 +0000 (21:54 +0000)]
MIR Parser: Report an error when a virtual register is redefined.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243695 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agofix memcpy/memset/memmove lowering when optimizing for size
Sanjay Patel [Thu, 30 Jul 2015 21:41:50 +0000 (21:41 +0000)]
fix memcpy/memset/memmove lowering when optimizing for size

Fixing MinSize attribute handling was discussed in D11363.
This is a prerequisite patch to doing that.

The handling of OptSize when lowering mem* functions was broken
on Darwin because it wants to ignore -Os for these cases, but the
existing logic also made it ignore -Oz (MinSize).

The Linux change demonstrates a widespread problem. The backend
doesn't usually recognize the MinSize attribute by itself; it
assumes that if the MinSize attribute exists, then the OptSize
attribute must also exist.

Fixing this more generally will be a follow-on patch or two.

Differential Revision: http://reviews.llvm.org/D11568

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243693 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] fix the strncmp interceptor -- it should respect short strings.
Kostya Serebryany [Thu, 30 Jul 2015 21:22:22 +0000 (21:22 +0000)]
[libFuzzer] fix the strncmp interceptor -- it should respect short strings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243691 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix TableGen code generation for ReadNone attribute.
Eric Christopher [Thu, 30 Jul 2015 21:16:34 +0000 (21:16 +0000)]
Fix TableGen code generation for ReadNone attribute.

Patch by Pete Abred!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243689 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoenable fast-math-flag propagation to DAG nodes
Sanjay Patel [Thu, 30 Jul 2015 21:06:55 +0000 (21:06 +0000)]
enable fast-math-flag propagation to DAG nodes

This uncovered latent bugs previously:
http://reviews.llvm.org/D10403

...but it's time to try again because internal tests aren't finding more.

If time passes and no other bugs are reported, we can remove this cl::opt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243687 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoEnable dfsan for aarch64
Adhemerval Zanella [Thu, 30 Jul 2015 20:49:35 +0000 (20:49 +0000)]
Enable dfsan for aarch64

This patch enable DFSan memory transformation for aarch64 (39-bit VMA).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243684 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd a TargetMachine hook that verifies DataLayout compatibility
Mehdi Amini [Thu, 30 Jul 2015 20:33:18 +0000 (20:33 +0000)]
Add a TargetMachine hook that verifies DataLayout compatibility

Summary: Also provide the associated assertion when CodeGen starts.

Reviewers: echristo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11654

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243682 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SLP vectorizer]: Choose the best consecutive candidate to pair with a store instruction.
Wei Mi [Thu, 30 Jul 2015 17:40:39 +0000 (17:40 +0000)]
[SLP vectorizer]: Choose the best consecutive candidate to pair with a store instruction.

The patch changes the SLPVectorizer::vectorizeStores to choose the immediate
succeeding or preceding candidate for a store instruction when it has multiple
consecutive candidates. In this way it has better chance to find more slp
vectorization opportunities.

Differential Revision: http://reviews.llvm.org/D10445

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243666 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix lli with OrcLazyJIT: the default DataLayout was used.
Mehdi Amini [Thu, 30 Jul 2015 17:29:33 +0000 (17:29 +0000)]
Fix lli with OrcLazyJIT: the default DataLayout was used.

Set the correct one using the TargetMachine instead.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243664 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Set SubRegIndex size and offset
Matt Arsenault [Thu, 30 Jul 2015 17:03:11 +0000 (17:03 +0000)]
AMDGPU: Set SubRegIndex size and offset

I'm not sure what reasons the comment here could have
had for not setting these. Without these set, there is
an assertion hit during DWARF emission.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243661 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Fix unreachable when emitting binary debug info
Matt Arsenault [Thu, 30 Jul 2015 17:03:08 +0000 (17:03 +0000)]
AMDGPU: Fix unreachable when emitting binary debug info

Copy implementation of applyFixup from AArch64 with AArch64 bits
ripped out.

Tests will be included with a later commit. Several other
problems must be fixed before binary debug info emission
will work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243660 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Serialization: Serialize the machine basic block's successor weights.
Alex Lorenz [Thu, 30 Jul 2015 16:54:38 +0000 (16:54 +0000)]
MIR Serialization: Serialize the machine basic block's successor weights.

Reviewers: Duncan P. N. Exon Smith

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243659 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[COFF] Add IMAGE_SCN_TYPE_NOLOAD to SectionCharacteristics
David Majnemer [Thu, 30 Jul 2015 16:47:56 +0000 (16:47 +0000)]
[COFF] Add IMAGE_SCN_TYPE_NOLOAD to SectionCharacteristics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243658 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Simplify moveSMRDToVALU()
Tom Stellard [Thu, 30 Jul 2015 16:20:42 +0000 (16:20 +0000)]
AMDGPU/SI: Simplify moveSMRDToVALU()

Summary:
Replace the switch on instruction opcode with a switch on register size.
This way we don't need to update the switch statement when we add new
SMRD variants.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11601

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243652 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Remove isTriviallyReMaterializable() function from SIInstrInfo
Tom Stellard [Thu, 30 Jul 2015 16:20:40 +0000 (16:20 +0000)]
AMDGPU/SI: Remove isTriviallyReMaterializable() function from SIInstrInfo

Summary:
This function is never called.  isReallyTriviallyReMaterializable() is
the function that should be implemented instead.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11620

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243651 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Fix out-of-date debug information in test file.
Vasileios Kalintiris [Thu, 30 Jul 2015 13:13:09 +0000 (13:13 +0000)]
[mips] Fix out-of-date debug information in test file.

Update the debug info in the check-lines because the change in r243638
introduced a constant initialization before the prologue's end as part
of a register spill.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243640 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMCJITTests/MCJITCAPITest.cpp: Try to appease i686-win32.
NAKAMURA Takumi [Thu, 30 Jul 2015 13:06:53 +0000 (13:06 +0000)]
MCJITTests/MCJITCAPITest.cpp: Try to appease i686-win32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243639 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][FastISel] Remove hidden mips-fast-isel option.
Vasileios Kalintiris [Thu, 30 Jul 2015 12:39:33 +0000 (12:39 +0000)]
[mips][FastISel] Remove hidden mips-fast-isel option.

Summary:
This hidden option would disable code generation through FastISel by
default. It was removed from the available options and from the
Fast-ISel tests that required it in order to run the tests.

Reviewers: dsanders

Subscribers: qcolombet, llvm-commits

Differential Revision: http://reviews.llvm.org/D11610

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243638 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][FastISel] Apply only zero-extension to constants prior to their materialization.
Vasileios Kalintiris [Thu, 30 Jul 2015 11:51:44 +0000 (11:51 +0000)]
[mips][FastISel] Apply only zero-extension to constants prior to their materialization.

Summary:
Previously, we would sign-extend non-boolean negative constants and
zero-extend otherwise. This was problematic for PHI instructions with
negative values that had a type with bitwidth less than that of the
register used for materialization.

More specifically, ComputePHILiveOutRegInfo() assumes the constants
present in a PHI node are zero extended in their container and
afterwards deduces the known bits.

For example, previously we would materialize an i16 -4 with the
following instruction:

  addiu $r, $zero, -4

The register would end-up with the 32-bit 2's complement representation
of -4. However, ComputePHILiveOutRegInfo() would generate a constant
with the upper 16-bits set to zero. The SelectionDAG builder would use
that information to generate an AssertZero node that would remove any
subsequent trunc & zero_extend nodes.

In theory, we should modify ComputePHILiveOutRegInfo() to consult
target-specific hooks about the way they prefer to materialize the
given constants. However, git-blame reports that this specific code
has not been touched since 2011 and it seems to be working well for every
target so far.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11592

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243636 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[test-release.sh] Add -no-libunwind to disable it on targets that don't support it.
Daniel Sanders [Thu, 30 Jul 2015 10:14:57 +0000 (10:14 +0000)]
[test-release.sh] Add -no-libunwind to disable it on targets that don't support it.

Summary:
Mips doesn't implement unw_getcontext() or libunwind::Registers_*::jumpto() yet
so we must disable libunwind for this release.

Reviewers: hans

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11563

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243633 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Recognize "flags" as an identifier, not a register in Intel-syntax inline asm
Michael Kuperstein [Thu, 30 Jul 2015 10:10:25 +0000 (10:10 +0000)]
[X86] Recognize "flags" as an identifier, not a register in Intel-syntax inline asm

Patch by: marina.yatsina@intel.com
Differential Revision: http://reviews.llvm.org/D11512

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243630 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd amdopencl environment to triple
Matt Arsenault [Thu, 30 Jul 2015 08:16:51 +0000 (08:16 +0000)]
Add amdopencl environment to triple

This is used by the AMD x86 OpenCL implementation
to change some ABI details on Windows and Linux.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243627 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LoopVer] Add missing std::move
Adam Nemet [Thu, 30 Jul 2015 04:21:13 +0000 (04:21 +0000)]
[LoopVer] Add missing std::move

The reason I was passing this vector by value in the constructor so that
I wouldn't have to copy when initializing the corresponding member but
then I forgot the std::move.

The use-case is LoopDistribution which filters the checks then
std::moves it to LoopVersioning's constructor.  With this interface we
can avoid any copies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243616 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LDist] Filter the checks locally rather than in LAA, NFC
Adam Nemet [Thu, 30 Jul 2015 03:29:16 +0000 (03:29 +0000)]
[LDist] Filter the checks locally rather than in LAA, NFC

Before, we were passing the pointer partitions to LAA.  Now, we get all
the checks from LAA and filter out the checks within partitions in
LoopDistribution.

This effectively concludes the steps to move filtering memchecks from
LAA into its clients.  There is still some cleanup left to remove the
unused interfaces in LAA that still take PtrPartition.

(Moving this functionality to LoopDistribution also requires
needsChecking on pointers to be made public.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243613 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] implement strncmp hook for data-flow-guided fuzzing (w/ and w/o dfsan...
Kostya Serebryany [Thu, 30 Jul 2015 02:33:45 +0000 (02:33 +0000)]
[libFuzzer] implement strncmp hook for data-flow-guided fuzzing (w/ and w/o dfsan), add a test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243611 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[MCJIT] Fix a memory leak in a unit test that was introduced in r243589.
Lang Hames [Thu, 30 Jul 2015 02:05:37 +0000 (02:05 +0000)]
[MCJIT] Fix a memory leak in a unit test that was introduced in r243589.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243609 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] implement memcmp hook for data-flow-guided fuzzing (w/o dfsan), extend...
Kostya Serebryany [Thu, 30 Jul 2015 01:34:58 +0000 (01:34 +0000)]
[libFuzzer] implement memcmp hook for data-flow-guided fuzzing (w/o dfsan), extend the memcmp fuzzer test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243603 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoPrefix make_reverse_iterator with llvm namespace.
Pete Cooper [Thu, 30 Jul 2015 00:40:42 +0000 (00:40 +0000)]
Prefix make_reverse_iterator with llvm namespace.

This was fallout from r243581.  Turns out C++14 has make_reverse_iterator.

Thanks to Filipe and David for the quick fix suggestion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243598 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agopush fast-math check for machine-combiner reassociations into instruction-type check...
Sanjay Patel [Thu, 30 Jul 2015 00:04:21 +0000 (00:04 +0000)]
push fast-math check for machine-combiner reassociations into instruction-type check; NFC

This makes it simpler to add instruction types that don't depend on fast-math.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243596 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIR: Implement Value::mergeUseLists() iteratively
Matthias Braun [Wed, 29 Jul 2015 23:22:48 +0000 (23:22 +0000)]
IR: Implement Value::mergeUseLists() iteratively

This avoids stack overflows when the the compiler does not perform tail call
elimination. Apparently this happens for MSVC with the /Ob2 switch which
may be used by external code including this header.

Reported by and based on a patch from Jean-Francois Riendeau.

Related to rdar://21900756

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243590 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[MCJIT] Fix PR20656 by teaching MCJIT to honor ExecutionEngine's global mapping.
Lang Hames [Wed, 29 Jul 2015 23:12:33 +0000 (23:12 +0000)]
[MCJIT] Fix PR20656 by teaching MCJIT to honor ExecutionEngine's global mapping.

This is important for users of the C API who can't supply custom symbol
resolvers yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243589 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix typo "fuction" noticed in comments in AssumptionCache.h, and also all the other...
Nick Lewycky [Wed, 29 Jul 2015 22:32:47 +0000 (22:32 +0000)]
Fix typo "fuction" noticed in comments in AssumptionCache.h, and also all the other files that have the same typo. All comments, no functionality change! (Merely a "fuctionality" change.)

Bonus change to remove emacs major mode marker from SystemZMachineFunctionInfo.cpp because emacs already knows it's C++ from the extension. Also fix typo "appeary" in AMDGPUMCAsmInfo.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243585 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[dsymutil] Re-add command line option -v this time printing the version.
Frederic Riss [Wed, 29 Jul 2015 22:29:50 +0000 (22:29 +0000)]
[dsymutil] Re-add command line option -v this time printing the version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243584 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[dsymutil] Use option categories.
Frederic Riss [Wed, 29 Jul 2015 22:29:46 +0000 (22:29 +0000)]
[dsymutil] Use option categories.

Prevent all the unrelated LLVM options to appear in the -help output
by introducing a tool specific option category. As a drive-by improve
the wording of the help message.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243583 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[dsymutil] Rename -v option to -verbose
Frederic Riss [Wed, 29 Jul 2015 22:29:34 +0000 (22:29 +0000)]
[dsymutil] Rename -v option to -verbose

The dsymutil-classic -v option dumps the tool version rather than
putting it in verbose mode. Rename -v to -verbose and update the
tests that use it (in the process removing it from a few tests that
didn't require it anymore since the -dump-debug-map option was
introduced).
A followup commit will reintroduce the -v option that dumps the
version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243582 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoReapply "Add reverse(ContainerTy) range adapter."
Pete Cooper [Wed, 29 Jul 2015 22:19:09 +0000 (22:19 +0000)]
Reapply "Add reverse(ContainerTy) range adapter."

This reverts commit r243567, which ultimately reapplies r243563.

The fix here was to use std::enable_if for overload resolution.  Thanks to David
Blaikie for lots of help on this, and for the extra tests!

Original commit message follows:

For cases where we needed a foreach loop in reverse over a container,
we had to do something like

 for (const GlobalValue *GV : make_range(TypeInfos.rbegin(),
                                         TypeInfos.rend())) {

This provides a convenience method which shortens this to

 for (const GlobalValue *GV : reverse(TypeInfos)) {

There are 2 versions of this, with a preference to the rbegin() version.

The first uses rbegin() and rend() to construct an iterator_range.

The second constructs an iterator_range from the begin() and end() methods
wrapped in std::reverse_iterator's.

Reviewed by David Blaikie.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243581 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRename hasCompatibleFunctionAttributes->areInlineCompatible based
Eric Christopher [Wed, 29 Jul 2015 22:09:48 +0000 (22:09 +0000)]
Rename hasCompatibleFunctionAttributes->areInlineCompatible based
on suggestions. Currently the function is only used for inline purposes
and this is more descriptive for the use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243578 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][SSE] Keep 32-bit target i64 vector shifts on SSE unit.
Simon Pilgrim [Wed, 29 Jul 2015 21:44:27 +0000 (21:44 +0000)]
[X86][SSE] Keep 32-bit target i64 vector shifts on SSE unit.

This patch improves the 32-bit target i64 constant matching to detect the shuffle vector splats that are introduced by i64 vector shift vectorization (D8416).

Differential Revision: http://reviews.llvm.org/D11327

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243577 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAArch64: use 32-bit MOV rather than UBFX to truncate registers.
Tim Northover [Wed, 29 Jul 2015 21:34:32 +0000 (21:34 +0000)]
AArch64: use 32-bit MOV rather than UBFX to truncate registers.

It's potentially more efficient on Cyclone, and from the optimization guides &
schedulers looks like it has no effect on Cortex-A53 or A57. In general you'd
expect a MOV to be about the most efficient instruction with its semantics,
even though the official "UXTW" alias is really a UBFX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243576 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Serialization: Serialize the frame info's save and restore points.
Alex Lorenz [Wed, 29 Jul 2015 21:09:09 +0000 (21:09 +0000)]
MIR Serialization: Serialize the frame info's save and restore points.

This commit serializes the save and restore machine basic block references from
the machine frame information class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243575 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Parser: Extract the code that parses MBB references into a new method. NFC.
Alex Lorenz [Wed, 29 Jul 2015 20:57:11 +0000 (20:57 +0000)]
MIR Parser: Extract the code that parses MBB references into a new method. NFC.

This commit extracts the code that's used by the class 'MIRParserImpl' to parse
the machine basic block references into a new method named 'parseMBBReference'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243572 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][SSE] Vectorize i64 ASHR operations
Simon Pilgrim [Wed, 29 Jul 2015 20:31:45 +0000 (20:31 +0000)]
[X86][SSE] Vectorize i64 ASHR operations

This patch vectorizes the v2i64/v4i64 ASHR shift operations - the last remaining integer vector shifts that are still being transferred to/from the scalar unit to be completed.

Differential Revision: http://reviews.llvm.org/D11439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243569 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "Add reverse(ContainerTy) range adapter."
Pete Cooper [Wed, 29 Jul 2015 20:29:10 +0000 (20:29 +0000)]
Revert "Add reverse(ContainerTy) range adapter."

This reverts commit r243563.

The GCC buildbots were extremely unhappy about this.  Reverting while
we discuss a better way of doing overload resolution.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243567 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[opaque pointers] Remove use of PointerType::getElementType in favor of GEPOperator...
David Blaikie [Wed, 29 Jul 2015 20:26:23 +0000 (20:26 +0000)]
[opaque pointers] Remove use of PointerType::getElementType in favor of GEPOperator::getSourceElementType

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243566 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd reverse(ContainerTy) range adapter.
Pete Cooper [Wed, 29 Jul 2015 20:00:39 +0000 (20:00 +0000)]
Add reverse(ContainerTy) range adapter.

For cases where we needed a foreach loop in reverse over a container,
we had to do something like

  for (const GlobalValue *GV : make_range(TypeInfos.rbegin(),
                                          TypeInfos.rend())) {

This provides a convenience method which shortens this to

  for (const GlobalValue *GV : reverse(TypeInfos)) {

There are 2 versions of this, with a preference to the rbegin() version.

The first uses rbegin() and rend() to construct an iterator_range.

The second constructs an iterator_range from the begin() and end() methods
wrapped in std::reverse_iterator's.

Reviewed by David Blaikie.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243563 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ASan] Disable dynamic alloca and UAR detection in presence of returns_twice calls.
Alexey Samsonov [Wed, 29 Jul 2015 19:36:08 +0000 (19:36 +0000)]
[ASan] Disable dynamic alloca and UAR detection in presence of returns_twice calls.

Summary:
returns_twice (most importantly, setjmp) functions are
optimization-hostile: if local variable is promoted to register, and is
changed between setjmp() and longjmp() calls, this update will be
undone. This is the reason why "man setjmp" advises to mark all these
locals as "volatile".

This can not be enough for ASan, though: when it replaces static alloca
with dynamic one, optionally called if UAR mode is enabled, it adds a
whole lot of SSA values, and computations of local variable addresses,
that can involve virtual registers, and cause unexpected behavior, when
these registers are restored from buffer saved in setjmp.

To fix this, just disable dynamic alloca and UAR tricks whenever we see
a returns_twice call in the function.

Reviewers: rnk

Subscribers: llvm-commits, kcc

Differential Revision: http://reviews.llvm.org/D11495

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243561 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[llvm-objdump] Inverting logic to match the word "predicate". Returning true when...
Colin LeMahieu [Wed, 29 Jul 2015 19:21:13 +0000 (19:21 +0000)]
[llvm-objdump] Inverting logic to match the word "predicate".  Returning true when we want it rather than when we want to discard it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243558 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[llvm-objdump] Merging MachO DumpSections in to FilterSections. Simplifying some...
Colin LeMahieu [Wed, 29 Jul 2015 19:08:10 +0000 (19:08 +0000)]
[llvm-objdump] Merging MachO DumpSections in to FilterSections.  Simplifying some predicate logic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243556 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRoll forward r242871
Jingyue Wu [Wed, 29 Jul 2015 18:59:09 +0000 (18:59 +0000)]
Roll forward r242871

r242871 missed one place that should be guarded with isPhysicalReg. This patch
fixes that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243555 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Serialization: Serialize the '.cfi_def_cfa' CFI instruction.
Alex Lorenz [Wed, 29 Jul 2015 18:57:23 +0000 (18:57 +0000)]
MIR Serialization: Serialize the '.cfi_def_cfa' CFI instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243554 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Parser: Parse multiple LHS register machine operands.
Alex Lorenz [Wed, 29 Jul 2015 18:51:21 +0000 (18:51 +0000)]
MIR Parser: Parse multiple LHS register machine operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243553 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agomove DAGCombiner's allowableAlignment() helper function into the TLI
Sanjay Patel [Wed, 29 Jul 2015 18:24:18 +0000 (18:24 +0000)]
move DAGCombiner's allowableAlignment() helper function into the TLI

Making allowableAlignment() more accessible was suggested as a predecessor patch
for D10662, so I've pulled it into TargetLowering. This let's us remove 4 instances
of duplicate logic in LegalizeDAG.

There's a subtle functional change in the implementation: the existing
allowableAlignment() code was using getPrefTypeAlignment() when checking
alignment with the DataLayout and assumed that was fast. In this implementation,
we use getABITypeAlignment() and assume that is fast. See the TODO comment or the
discussion in the Phab review for future improvements in this implementation
(don't use the data layout at all).

There are no regression test changes from this difference, and I'm not sure how to
expose it via a test. I think we actually do want to provide the 'Fast' param when
checking this from DAGCombiner::MergeConsecutiveStores(). Ie, we shouldn't merge
stores if the new stores are not going to be fast. But that change will require
fixing allowsMisalignedMemoryAccess() overrides as noted in D10662.

Differential Revision: http://reviews.llvm.org/D10905

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243549 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[asan] Remove special case mapping on Android/AArch64.
Evgeniy Stepanov [Wed, 29 Jul 2015 18:22:25 +0000 (18:22 +0000)]
[asan] Remove special case mapping on Android/AArch64.

ASan shadow on Android starts at address 0 for both historic and
performance reasons. This is possible because the platform mandates
-pie, which makes lower memory region always available.

This is not such a good idea on 64-bit platforms because of MAP_32BIT
incompatibility.

This patch changes Android/AArch64 mapping to be the same as that of
Linux/AAarch64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243548 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLowerBitSets: Add debugging output.
Peter Collingbourne [Wed, 29 Jul 2015 18:12:36 +0000 (18:12 +0000)]
LowerBitSets: Add debugging output.

Differential Revision: http://reviews.llvm.org/D11583

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243546 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Unroll] Handle SwitchInst properly.
Michael Zolotukhin [Wed, 29 Jul 2015 18:10:33 +0000 (18:10 +0000)]
[Unroll] Handle SwitchInst properly.

Previously successor selection was simply wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243545 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Unroll] Don't crash when simplified branch condition is undef.
Michael Zolotukhin [Wed, 29 Jul 2015 18:10:29 +0000 (18:10 +0000)]
[Unroll] Don't crash when simplified branch condition is undef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243544 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRename test full-unroll-bad-geps.ll to full-unroll-crashers.ll.
Michael Zolotukhin [Wed, 29 Jul 2015 18:10:23 +0000 (18:10 +0000)]
Rename test full-unroll-bad-geps.ll to full-unroll-crashers.ll.

No reason to limit it only to GEP-related crashes. More tests are to
come here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243543 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix typos in comments. NFC.
Lang Hames [Wed, 29 Jul 2015 18:07:48 +0000 (18:07 +0000)]
Fix typos in comments. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243542 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "[PeepholeOptimizer] Look through PHIs to find additional register sources"
Bruno Cardoso Lopes [Wed, 29 Jul 2015 17:46:47 +0000 (17:46 +0000)]
Revert "[PeepholeOptimizer] Look through PHIs to find additional register sources"

Reported to Broke some internal tests: PR24303

This reverts commit r243486.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243540 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd an ArgList::AddAllArgs that accepts a vector of OptSpecifier.
Douglas Katzman [Wed, 29 Jul 2015 17:34:41 +0000 (17:34 +0000)]
Add an ArgList::AddAllArgs that accepts a vector of OptSpecifier.

This lifts the somewhat arbitrary restriction on 3 OptSpecifiers.

Differential Revision: http://reviews.llvm.org/D11597

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243539 91177308-0d34-0410-b5e6-96231b3b80d8