MIR Parser: Report an error when a virtual register is redefined.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243695 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/MIRYamlMapping.h b/include/llvm/CodeGen/MIRYamlMapping.h
index 7ef4c6b6e39e2433a18a2cccf1b62a7e9609d40a..c986f57cd9533e121c3fea61aabc3af23207eaf4 100644 (file)
--- a/include/llvm/CodeGen/MIRYamlMapping.h
+++ b/include/llvm/CodeGen/MIRYamlMapping.h
@@ -131,7 +131,7 @@ namespace llvm {
 namespace yaml {
 
 struct VirtualRegisterDefinition {
-  unsigned ID;
+  UnsignedValue ID;
   StringValue Class;
   StringValue PreferredRegister;
   // TODO: Serialize the target specific register hints.

diff --git a/lib/CodeGen/MIRParser/MIRParser.cpp b/lib/CodeGen/MIRParser/MIRParser.cpp
index a179c59338090852fa6d1fee2532b8c3d75d808a..7966f389d3e41842d1cb07f9f0c303ecd0bc25e6 100644 (file)
--- a/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -414,9 +414,11 @@ bool MIRParserImpl::initializeRegisterInfo(MachineFunction &MF,
                    Twine("use of undefined register class '") +
                        VReg.Class.Value + "'");
     unsigned Reg = RegInfo.createVirtualRegister(RC);
-    // TODO: Report an error when the same virtual register with the same ID is
-    // redefined.
-    PFS.VirtualRegisterSlots.insert(std::make_pair(VReg.ID, Reg));
+    if (!PFS.VirtualRegisterSlots.insert(std::make_pair(VReg.ID.Value, Reg))
+             .second)
+      return error(VReg.ID.SourceRange.Start,
+                   Twine("redefinition of virtual register '%") +
+                       Twine(VReg.ID.Value) + "'");
     if (!VReg.PreferredRegister.Value.empty()) {
       unsigned PreferredReg = 0;
       if (parseNamedRegisterReference(PreferredReg, SM, MF,

diff --git a/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir b/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
new file mode 100644 (file)
index 0000000..baadeae
--- /dev/null
+++ b/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
@@ -0,0 +1,28 @@
+# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @test(i32 %a) {
+  body:
+    ret i32 %a
+  }
+
+...
+---
+name:            test
+isSSA:           true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gr32 }
+# CHECK: [[@LINE+1]]:11: redefinition of virtual register '%0'
+  - { id: 0, class: gr32 }
+body:
+  - id:          0
+    name:        body
+    liveins:     [ '%edi' ]
+    instructions:
+      - '%0 = COPY %edi'
+      - '%eax = COPY %0'
+      - 'RETQ %eax'
+...
+