fix some 80-col violations

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55565 91177308-0d34-0410-b5e6-96231b3b80d8

Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55564 91177308-0d34-0410-b5e6-96231b3b80d8

Fold isRematerializable checks into isSafeToReMat.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55563 91177308-0d34-0410-b5e6-96231b3b80d8

For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55562 91177308-0d34-0410-b5e6-96231b3b80d8

Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55558 91177308-0d34-0410-b5e6-96231b3b80d8

Enable -fvisibility-inlines-hidden by default for compilers which
support it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55557 91177308-0d34-0410-b5e6-96231b3b80d8

Testcases for ppc atomics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55556 91177308-0d34-0410-b5e6-96231b3b80d8

Fix an issue where a use might be selected before a def, and then we didn't respect the pre-chosen vreg
assignment when selecting the def.  This is the naive solution to the problem: insert a copy to the pre-chosen
vreg.  Other solutions might be preferable, such as:
  1) Passing the dest reg into FastEmit_.  However, this would require the higher level code to know about reg classes, which they don't currently.
  2) Selecting blocks in reverse postorder.  This has some compile time cost for computing the order, and we'd need to measure its impact.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55555 91177308-0d34-0410-b5e6-96231b3b80d8

Add ppc partial-word ATOMIC_CMP_SWAP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55554 91177308-0d34-0410-b5e6-96231b3b80d8

Swap fp comparison operands and change predicate to allow load folding (safely this time).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55553 91177308-0d34-0410-b5e6-96231b3b80d8

Use static_cast instead of C style cast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55552 91177308-0d34-0410-b5e6-96231b3b80d8

Fix 80 col. violations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55551 91177308-0d34-0410-b5e6-96231b3b80d8

xfail this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55550 91177308-0d34-0410-b5e6-96231b3b80d8

Back out 55498. It broken Apple style bootstrapping.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55549 91177308-0d34-0410-b5e6-96231b3b80d8

Backing out 55521. Not safe.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55548 91177308-0d34-0410-b5e6-96231b3b80d8

Add partial word version of ATOMIC_SWAP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55546 91177308-0d34-0410-b5e6-96231b3b80d8

Add initial support for fast isel of instructions that have inputs pinned to physical registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55545 91177308-0d34-0410-b5e6-96231b3b80d8

regenerate

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55542 91177308-0d34-0410-b5e6-96231b3b80d8

Asmprint nameless instructions as:

%4 = add ...

instead of:

add ...    ; 4

This makes opt -print-cfg output actually usable and makes .ll files
generally easier to read.  This fixes PR2480

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55541 91177308-0d34-0410-b5e6-96231b3b80d8

allow this to pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55540 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for parsing .ll files that have numbers in front of
nameless values, such as:

%3 = add i32 4, 2

This fixes the first half of PR2480

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55539 91177308-0d34-0410-b5e6-96231b3b80d8

TableGen'ing instruction encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55533 91177308-0d34-0410-b5e6-96231b3b80d8

addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55531 91177308-0d34-0410-b5e6-96231b3b80d8

MVN is addrmode1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55530 91177308-0d34-0410-b5e6-96231b3b80d8

Add GlobalValue::{removeFromParent,eraseFromParent}

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55529 91177308-0d34-0410-b5e6-96231b3b80d8

More refactoring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55528 91177308-0d34-0410-b5e6-96231b3b80d8

Add DenseMap::lookup:
  /// lookup - Return the entry for the specified key, or a default
  /// constructed value if no such entry exists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55523 91177308-0d34-0410-b5e6-96231b3b80d8

Swap fp comparison operands and change predicate to allow load folding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55521 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor ARM instruction format definitions into a separate file. No functionality changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55518 91177308-0d34-0410-b5e6-96231b3b80d8

Add a target callback for FastISel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55512 91177308-0d34-0410-b5e6-96231b3b80d8

remove tabs, fix > 80 cols

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55511 91177308-0d34-0410-b5e6-96231b3b80d8

Add another description to my entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55510 91177308-0d34-0410-b5e6-96231b3b80d8

just a brain dump for a small tool
that brings us to 80-col violations
or tabs.

Usage:
  visit-violations <file>

At the moment it outputs editor invocations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55509 91177308-0d34-0410-b5e6-96231b3b80d8

rename destroy -> releaseMemory to properly hook into passmgr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55508 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for JIT exceptions on Darwin. Since we're dealing with libgcc,
whose darwin code was written after the ability to dynamically register frames,
we need to do special hacks to make things work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55507 91177308-0d34-0410-b5e6-96231b3b80d8

fix the output dumbness I have introduced some time ago

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55506 91177308-0d34-0410-b5e6-96231b3b80d8

erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8

Implement null and undef values for FastISel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55500 91177308-0d34-0410-b5e6-96231b3b80d8

In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55499 91177308-0d34-0410-b5e6-96231b3b80d8

Optimize DAGCombiner's worklist processing. Previously it started
its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.

This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55498 91177308-0d34-0410-b5e6-96231b3b80d8

Move CaseBlock, JumpTable, and BitTestBlock to be members of
SelectionDAGLowering instead of being in an anonymous namespace.
This fixes warnings about SelectionDAGLowering having fields
using anonymous namespaces.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55497 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a FastISel bug where the instructions from lowering the arguments
were being emitted after the first instructions of the entry block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55496 91177308-0d34-0410-b5e6-96231b3b80d8

Use resize instead of reserve. Reserve doesn't change size().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55486 91177308-0d34-0410-b5e6-96231b3b80d8

Reduce the size of the Parts vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55483 91177308-0d34-0410-b5e6-96231b3b80d8

Hook up support for fast-isel of trunc instructions, using the newly working support for EXTRACT_SUBREG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55482 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for fast-isel of opcodes that require use of extract_subreg.  Because of how extract_subreg is treated, it requires special case handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55480 91177308-0d34-0410-b5e6-96231b3b80d8

Implement partial-word binary atomics on ppc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55478 91177308-0d34-0410-b5e6-96231b3b80d8

FastEmitInst_extractsubreg doesn't need to be passed the register class.  It can get it from MachineRegisterInfo instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55476 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r55467; it causes regressions in UnitTests/Vector/divides,
Benchmarks/sim/sim, and others on x86-64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55475 91177308-0d34-0410-b5e6-96231b3b80d8

Correctly resize the Parts array.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55471 91177308-0d34-0410-b5e6-96231b3b80d8

If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55467 91177308-0d34-0410-b5e6-96231b3b80d8

FsFLD0S{S|D} and V_SETALLONES are as cheap as moves.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55466 91177308-0d34-0410-b5e6-96231b3b80d8

Make the verifier reject instructions which have null pointers
for operands: rdar://6179606.  no testcase, because I can't write
a .ll file that is this broken ;-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55460 91177308-0d34-0410-b5e6-96231b3b80d8

Clear the intervals list in "destroy", patch by
Prakash Prabhu!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55458 91177308-0d34-0410-b5e6-96231b3b80d8

Split the ATOMIC NodeType's to include the size, e.g.
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55457 91177308-0d34-0410-b5e6-96231b3b80d8

This test crashes on non-x86 host; make SSE explicit.
Feel free to fix a better way!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55456 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a missing #include. Patch by Andrew John Hughes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55451 91177308-0d34-0410-b5e6-96231b3b80d8

Reorganize the lifetimes of the major objects SelectionDAGISel
works with.

SelectionDAG, FunctionLoweringInfo, and SelectionDAGLowering
objects now get created once per SelectionDAGISel instance, and
can be reused across blocks and across functions. Previously,
they were created and destroyed each time they were needed.

This reorganization simplifies the handling of PHI nodes, and
also SwitchCases, JumpTables, and BitTestBlocks. This
simplification has the side effect of fixing a bug in FastISel
where successor PHI nodes weren't being updated correctly.

This is also a step towards making the transition from FastISel
into and out of SelectionDAG faster, and also making
plain SelectionDAG faster on code with lots of little blocks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55450 91177308-0d34-0410-b5e6-96231b3b80d8

Add a helper method that will be used to support EXTRACT_SUBREG for selecting trunc's in fast-isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55439 91177308-0d34-0410-b5e6-96231b3b80d8

Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the
SSE2 registers as well as the MMX registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55436 91177308-0d34-0410-b5e6-96231b3b80d8

Put file scoped constants in an anonymous namespace. Use the "using namespace
llvm" for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55435 91177308-0d34-0410-b5e6-96231b3b80d8

Move the check whether it's worth remating to caller.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55434 91177308-0d34-0410-b5e6-96231b3b80d8

Do not apply the transformation if the target does not support DestTy natively.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55433 91177308-0d34-0410-b5e6-96231b3b80d8

Backout 55429

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55432 91177308-0d34-0410-b5e6-96231b3b80d8

Fix FastISel's bitcast code for the case where getRegForValue fails.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55431 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor isSafeToReMat out of 2addr pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55430 91177308-0d34-0410-b5e6-96231b3b80d8

Add facility to create a target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55429 91177308-0d34-0410-b5e6-96231b3b80d8

Use TargetLowering to get the types in fast isel, which handles pointer types correctly for our purposes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55428 91177308-0d34-0410-b5e6-96231b3b80d8

Don't check TLI.getOperationAction. The FastISel way is to
just try to do the action and let the tablegen-generated code
determine if there is target-support for an operation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55427 91177308-0d34-0410-b5e6-96231b3b80d8

Add a new FastISel method, getRegForValue, which takes care of
the details of materializing constants and other values into
registers, and make use of it in several places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55426 91177308-0d34-0410-b5e6-96231b3b80d8

Add a comment about the current floating-point constant code in FastISel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55425 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typos and whitespaces. Other cosmetic changes based on feedback.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55424 91177308-0d34-0410-b5e6-96231b3b80d8

Minor cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55423 91177308-0d34-0410-b5e6-96231b3b80d8

Reinstate the x86-64 portion of r55190. When doing extloads into
64-bit registers from 16-bit and smaller memory locations, prefer
instructions that define the entire 64-bit register, to avoid
partial-register updates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55422 91177308-0d34-0410-b5e6-96231b3b80d8

Optimize ScheduleDAGRRList's topological sort to use one pass instead
of two, and to not need a scratch std::vector. Also, compute the ordering
immediately in the result array, instead of in another scratch std::vector
that is copied to the result array.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55421 91177308-0d34-0410-b5e6-96231b3b80d8

Optimize ScheduleDAG's ComputeDepths and ComputeHeights to not need
a scratch std::vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55420 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the std::ostream form of PseudoSourceValue's print,
which isn't needed anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55419 91177308-0d34-0410-b5e6-96231b3b80d8

Update a comment to reflect recent changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55418 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak PseudoSourceValue::print. This fixes -print-machine-instrs
and various other things.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55415 91177308-0d34-0410-b5e6-96231b3b80d8

Diagnose uses of unsized types with the byval attribute in the
verifier. See PR2711 for details.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55414 91177308-0d34-0410-b5e6-96231b3b80d8

Update wording, as aggregates are now first-class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55413 91177308-0d34-0410-b5e6-96231b3b80d8

Add DebugInfoBuilder. Patch by Talin!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55409 91177308-0d34-0410-b5e6-96231b3b80d8

Basic FastISel support for floating-point constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55401 91177308-0d34-0410-b5e6-96231b3b80d8

Fix handling of inttoptr and ptrtoint when unhandled operands are present.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55400 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for fast isel of inttoptr and ptrtoint in the cases where truncation is not needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55399 91177308-0d34-0410-b5e6-96231b3b80d8

Factor out a large amoutn of the cast handling code in fast isel into helper methods.
This simultaneously makes the code simpler and adds support for sext as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55398 91177308-0d34-0410-b5e6-96231b3b80d8

Add a MachineInstrBuilder method for adding floating-point
immediate operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55397 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for fast isel of zext.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55396 91177308-0d34-0410-b5e6-96231b3b80d8

disallow direct access to SDValue::ResNo, provide a getter instead

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for fptosi of constants in fast isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55393 91177308-0d34-0410-b5e6-96231b3b80d8

Put a heuristic in place to prevent GVN from falling into bad cases with massively complicated CFGs.
This speeds up a particular testcase from 12+ hours to 5 seconds with little perceptible loss of quality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55391 91177308-0d34-0410-b5e6-96231b3b80d8

Optimize SelectionDAG's topological sort to use one pass instead
of two, and to not need a scratch std::vector. Also, use the
SelectionDAG's topological sort in LegalizeDAG instead of having
a separate implementation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55389 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor the bitcast code into its own function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55387 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor a bunch of FastISelEmitter code into a helper class, and
put each major step in a separate function. This makes the high
level sequence of events easier to follow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55385 91177308-0d34-0410-b5e6-96231b3b80d8

Make FastISel use the correct argument type when casting GEP indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55384 91177308-0d34-0410-b5e6-96231b3b80d8

Don't select binary instructions with illegal types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55383 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for fast isel of sitofp, and remove some unnecessary and imprecise legality checks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55381 91177308-0d34-0410-b5e6-96231b3b80d8

- small bug corrected: incorrect iterator type.
- fix to please VS: add a return after an assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55380 91177308-0d34-0410-b5e6-96231b3b80d8

Use a combination of copyRegToReg and ISD::BIT_CONVERT when doing fast isel of bitcasts,
allowing it to support the full range of conversions people might ask for in a correct manner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55378 91177308-0d34-0410-b5e6-96231b3b80d8

These assertions should be return false's instead, allowing the client to detect the failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55377 91177308-0d34-0410-b5e6-96231b3b80d8