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Move the test for the data in code into the ARM directory as it is an ARM
[oota-llvm.git] / lib /
2013-06-06 Arnold SchwaighoferARM sched model: Add integer VFP/SIMD instructions... tree | commitdiff
2013-06-06 Jakub StaszakRe-apply "Use IRBuilder instead of ConstantInt methods... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add integer load/store instructions... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add integer arithmetic instructions... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Cortex A9 - More InstRW sched resources tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add branch thumb instructions tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add branch thumb2 instructions tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add branch instructions tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add preload thumb2 instructions tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add preload instructions tree | commitdiff
2013-06-06 Kevin EnderbyTeach llvm-objdump with the -macho parser how to use... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions tree | commitdiff
2013-06-06 Rafael EspindolaRevert "Use IRBuilder instead of ConstantInt methods... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb2 instructions tree | commitdiff
2013-06-06 Vincent LejeuneR600: Remove leftover code in R600MachineScheduler.cpp tree | commitdiff
2013-06-06 Rafael EspindolaPrint symbol names in relocations when dumping COFF... tree | commitdiff
2013-06-06 Bill WendlingCast to the correct type. Pointer, not reference. tree | commitdiff
2013-06-06 NAKAMURA TakumiR600OptimizeVectorRegisters.cpp: Tweak a warning. ... tree | commitdiff
2013-06-06 NAKAMURA TakumiR600OptimizeVectorRegisters.cpp: Suppress a warning... tree | commitdiff
2013-06-06 NAKAMURA TakumiTrailing linefeed. tree | commitdiff
2013-06-06 Bill WendlingCast to the proper type. tree | commitdiff
2013-06-06 Jakub StaszakRemove unneeded cast<>. tree | commitdiff
2013-06-06 Bill WendlingCache the TargetLowering info object as a pointer. tree | commitdiff
2013-06-06 Jakub StaszakUse IRBuilder instead of ConstantInt methods. tree | commitdiff
2013-06-06 Bill WendlingDon't cache the TargetLoweringInfo object inside of... tree | commitdiff
2013-06-05 Sean SilvaAdd writeAsHex(raw_ostream &) method to BinaryRef. tree | commitdiff
2013-06-05 Tom StellardR600: Replace predicate loop with predicate function tree | commitdiff
2013-06-05 Sean SilvaRename BinaryRef::isBinary to more descriptive DataIsHe... tree | commitdiff
2013-06-05 Bill WendlingAdd space to assert message. tree | commitdiff
2013-06-05 Sean SilvaAdd writeAsBinary(raw_ostream &) method to BinaryRef. tree | commitdiff
2013-06-05 Vincent LejeuneR600: Add a pass that merge Vector Register tree | commitdiff
2013-06-05 Vincent LejeuneR600: Schedule copy from phys register at beginning... tree | commitdiff
2013-06-05 Akira Hatanaka[mips] brcond + setgt/setugt instruction selection... tree | commitdiff
2013-06-05 Jakub StaszakUse IRBuilder instead of ConstantInt methods. It simpli... tree | commitdiff
2013-06-05 Michael Liao[PATCH] Fix VGATHER* operand constraints tree | commitdiff
2013-06-05 Arnold SchwaighoferARM sched model: Add more ALU and CMP instructions tree | commitdiff
2013-06-05 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt tree | commitdiff
2013-06-05 Arnold SchwaighoferARMInstrInfo: Improve isSwiftFastImmShift tree | commitdiff
2013-06-05 Mihai PopaThis is a simple patch that changes RRX and RRXS to... tree | commitdiff
2013-06-05 David BlaikiePR15662: Optimized debug info produces out of order... tree | commitdiff
2013-06-05 Tom StellardR600: Make sure to schedule AR register uses and defs... tree | commitdiff
2013-06-05 Rafael EspindolaDon't print default values for NumberOfAuxSymbols and... tree | commitdiff
2013-06-05 Rafael EspindolaHandle (at least don't crash on) relocations with no... tree | commitdiff
2013-06-05 Rafael EspindolaMove BinaryRef to a new include/llvm/Object/YAML.h... tree | commitdiff
2013-06-05 Rafael EspindolaRevert "R600: Add a pass that merge Vector Register" tree | commitdiff
2013-06-05 Rafael EspindolaHandle relocations that don't point to symbols. tree | commitdiff
2013-06-04 Vincent LejeuneR600: Add a pass that merge Vector Register tree | commitdiff
2013-06-04 Vincent LejeuneR600: Const/Neg/Abs can be folded to dot4 tree | commitdiff
2013-06-04 Evan ChengCortex-R5 can issue Thumb2 integer division instructions. tree | commitdiff
2013-06-04 Arnold SchwaighoferRevert series of sched model patches until I figure... tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add VFP div instruction on Swift tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions... tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add integer VFP/SIMD instructions... tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add integer load/store instructions... tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add integer arithmetic instructions... tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Cortex A9 - More InstRW sched resources tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add branch thumb instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add branch thumb2 instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add branch instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add preload thumb2 instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add preload instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions tree | commitdiff
2013-06-04 Arnold Schwaighofer ARM sched model: Add more ALU and CMP thumb2 instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add more ALU and CMP instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt tree | commitdiff
2013-06-04 Arnold SchwaighoferARMInstrInfo: Improve isSwiftFastImmShift tree | commitdiff
2013-06-04 Venkatraman Govind... Sparc: No functionality change. Cleanup whitespaces... tree | commitdiff
2013-06-04 David MajnemerIndVarSimplify: check if loop invariant expansion can... tree | commitdiff
2013-06-04 David MajnemerARM: Fix crash in ARM backend inside of ARMConstantIsla... tree | commitdiff
2013-06-04 Vincent LejeuneR600: Swizzle texture/export instructions tree | commitdiff
2013-06-04 Rafael EspindolaSecond part of pr16069 tree | commitdiff
2013-06-04 Hans WennborgTypo: s/caes/cases/ in SimplifyCFG tree | commitdiff
2013-06-04 Benjamin KramerPreserve const correctness. tree | commitdiff
2013-06-04 Vladimir MedicTest commit for user vmedic, to verify commit access... tree | commitdiff
2013-06-04 Aaron BallmanSilencing an MSVC warning about mixing bool and unsigne... tree | commitdiff
2013-06-04 Aaron BallmanSilencing an MSVC warning about */ being found outside... tree | commitdiff
2013-06-04 Shuxin YangFix a defect in code-layout pass, improving Benchmarks... tree | commitdiff
2013-06-03 Nick LewyckyDelete dead safety check. tree | commitdiff
2013-06-03 David MajnemerSimplifyCFG: Do not transform PHI to select if doing... tree | commitdiff
2013-06-03 David MajnemerSimplifyCFG: Small cleanup, use ICmpInst::isEquality() tree | commitdiff
2013-06-03 Rafael EspindolaUpdate RuntimeDyldELF::findOPDEntrySection the new... tree | commitdiff
2013-06-03 Tom StellardR600/SI: Add support for work item and work group intri... tree | commitdiff
2013-06-03 Tom StellardR600/SI: Add a calling convention for compute shaders tree | commitdiff
2013-06-03 Tom StellardR600/SI: Custom lower i64 sign_extend tree | commitdiff
2013-06-03 Tom StellardR600/SI: Adjust some instructions' out register class... tree | commitdiff
2013-06-03 Tom StellardR600/SI: Handle REG_SEQUENCE in fitsRegClass() tree | commitdiff
2013-06-03 Tom StellardR600/SI: Handle nodes with glue results correctly SITar... tree | commitdiff
2013-06-03 Tom StellardR600/SI: Fixup CopyToReg register class in PostprocessI... tree | commitdiff
2013-06-03 Tom StellardR600/SI: Add support for global loads tree | commitdiff
2013-06-03 Tom StellardR600/SI: Rework MUBUF store instructions tree | commitdiff
2013-06-03 Vincent LejeuneR600: 3 op instructions have no write bit but the resul... tree | commitdiff
2013-06-03 Vincent LejeuneR600: CALL_FS consumes a stack size entry tree | commitdiff
2013-06-03 Vincent LejeuneR600: use capital letter for PV channel tree | commitdiff
2013-06-03 Vincent LejeuneR600: Constraints input regs of interp_xy,_zw tree | commitdiff
2013-06-03 Kostya Serebryany[asan] ASan Linux MIPS32 support (llvm part), patch... tree | commitdiff
2013-06-03 Ahmed BougachaX86: sub_xmm registers are 128 bits wide. tree | commitdiff
2013-06-03 Manuel KlimekIntroduce needsCleanup() for APFloat and APInt. tree | commitdiff
2013-06-03 Venkatraman Govind... Sparc: Add support for indirect branch and blockaddress... tree | commitdiff
2013-06-03 Rui Ueyama[Object/COFF] Fix Windows .lib name handling. tree | commitdiff
2013-06-03 Venkatraman Govind... Sparc: When storing 0, use %g0 directly in the store... tree | commitdiff
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C/C++ LLVM-based compilers that forbids OOTA behaviors