Adding a new option to CMake to disable C++ atexit on llvm-shlib.
[oota-llvm.git] / lib / Target /
2014-12-09 Robert Khasanov[AVX512] Added lowering for VBROADCASTSS/SD instructions.
2014-12-09 Duncan P. N. Exon... IR: Split Metadata from Value
2014-12-09 Colin LeMahieu[Hexagon] Updating predicate register transfers and...
2014-12-09 Bill Schmidt[PowerPC 4/4] Enable little-endian support for VSX.
2014-12-09 Bill Schmidt[PowerPC 3/4] Little-endian adjustments for VSX vector...
2014-12-09 Bill Schmidt[PowerPC 2/4] Little-endian adjustments for VSX insert...
2014-12-09 Robert Khasanov[AVX512] Added VPBROADCAST{BWDQ} (Load with Broadcast...
2014-12-09 Bill Schmidt[PowerPC 1/4] Little-endian adjustments for VSX loads...
2014-12-09 Chandler Carruth[x86] Fix the test to actually test things for the...
2014-12-09 Aaron BallmanRemoving an unused variable to silence a -Wunused-but...
2014-12-09 Asiri RathnayakeFix modified immediate bug reported by MC Hammer.
2014-12-09 Chandler Carruth[x86] Bring some sanity to the x86 CPU processor defini...
2014-12-09 Elena DemikhovskyAVX-512: Added some comments to ERI scalar intrinsics.
2014-12-09 Mohit K. Bhakkadtest commit (spelling correction)
2014-12-09 Michael Kuperstein[X86] Convert esp-relative movs of function arguments...
2014-12-09 Bill SchmidtRestore r223709 as it was meant to be, and enable Featu...
2014-12-09 NAKAMURA TakumiRevert r223709, "[PowerPC]Activate FeatureVSX for the...
2014-12-09 Tom StellardR600/SI: Set MayStore = 0 on MUBUF loads
2014-12-09 Tom StellardR600/SI: Move setting of the lds bit to the base MUBUF...
2014-12-08 Colin LeMahieu[Hexagon] Removing old def versions and replacing usage...
2014-12-08 Colin LeMahieu[Hexagon] Adding any8, all8, and/or/xor/andn/orn/not...
2014-12-08 Bill Seurer[PowerPC]Activate FeatureVSX for the Power target
2014-12-08 Hal Finkel[PowerPC] Don't use a non-allocatable register to imple...
2014-12-08 Colin LeMahieu[Hexagon] Adding xtype doubleword add, sub, and, or...
2014-12-08 Colin LeMahieu[Hexagon] Adding xtype doubleword comparisons. Removin...
2014-12-08 Colin LeMahieu[Hexagon] Adding xtype parity, min, minu, max, maxu...
2014-12-08 Colin LeMahieu[Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh...
2014-12-08 Matt ArsenaultR600/SI: Move continue after checking s_mov_b32.
2014-12-08 Colin LeMahieu[Hexagon] Adding add/sub with saturation. Removing...
2014-12-08 Bruno Cardoso Lopes[CompactUnwind] Fix register encoding logic
2014-12-08 Tim NorthoverAArch64: treat HFAs containing "half" types as blocks...
2014-12-08 Andrea Di Biagio[X86] Improved tablegen patters for matching TZCNT...
2014-12-08 Colin LeMahieu[Hexagon] Adding combine reg, reg with predicated forms.
2014-12-08 Colin LeMahieu[Hexagon] Adding packhl instruction.
2014-12-08 Daniel Sanders[mips] Add Mips-specific CCIf's for accessing the MipsC...
2014-12-08 Andrea Di Biagio[X86] Improved lowering of packed v8i16 vector shifts...
2014-12-08 Elena DemikhovskyX86 intrinsics moved form X86ISelLowering.cpp to X86Int...
2014-12-07 Marek OlsakR600/SI: Disable VMEM and SMEM clauses by breaking...
2014-12-07 Marek OlsakR600/SI: Set 20-bit immediate byte offset for SMRD...
2014-12-07 Marek OlsakR600/SI: Update instruction conversions for VI
2014-12-07 Marek OlsakR600/SI: Add VI instructions
2014-12-07 Marek OlsakR600/SI: Add SCC Defs/Uses to SOP1 and SOP2 opcodes
2014-12-06 Benjamin KramerMake the DenseMap bucket type configurable and use...
2014-12-06 Tom StellardR600/SI: Restore PrivateGlobalPrefix to the default...
2014-12-06 Ahmed Bougacha[X86] Refactor PMOV[SZ]Xrm to add missing AVX2 patterns.
2014-12-06 Tim NorthoverAArch64: use explicit MVT::i64 when creating EXTRACT_SU...
2014-12-05 Ahmed Bougacha[X86] Cleanup FCOPYSIGN lowering. NFC intended.
2014-12-05 Colin LeMahieu[Hexagon] Relocating logical instructions and templates...
2014-12-05 Colin LeMahieu[Hexagon] Adding sub/and/or reg, imm forms
2014-12-05 Sanjay PatelOptimize merging of scalar loads for 32-byte vectors...
2014-12-05 Colin LeMahieu[Hexagon] Updating mux_ir/ri/ii/rr with encoding bits
2014-12-05 Jan Wen VoungUse 32-bit ebp for NaCl64 in a limited case: llvm.frame...
2014-12-05 Bill Seurer[PowerPC]Add VSX loads/stores to fastisel for PPC target
2014-12-05 Colin LeMahieu[Hexagon] Adding tfrih/l instructions.
2014-12-05 Andrea Di Biagio[X86] Improved lowering of packed vector shifts to...
2014-12-05 Colin LeMahieu[Hexagon] Adding add reg, imm form with encoding bits...
2014-12-05 Colin LeMahieu[Hexagon] Adding DoubleRegs decoder. Moving C2_mux...
2014-12-05 Colin LeMahieu[Hexagon] [NFC] Rearranging patterns and mux instruction.
2014-12-05 Colin LeMahieu[Hexagon] [NFC] Rearranging def order.
2014-12-05 Colin LeMahieu[Hexagon] Adding combine reg-reg forms.
2014-12-05 Colin LeMahieu[Hexagon] Marking several instructions as isCodeGenOnly...
2014-12-05 Andrea Di Biagio[X86] Avoid introducing extra shuffles when lowering...
2014-12-05 Charlie TurnerAdd missing FP build attribute tests.
2014-12-05 Eric ChristopherRename the x86 isTargetMacho to isTargetMachO for unifo...
2014-12-05 Eric ChristopherBoth of these subtargets have functions that check...
2014-12-04 Ahmed Bougacha[X86] Delete dead code in fcopysign lowering. NFC.
2014-12-04 Roman DivackyAdd a FIXME as requested by Renato Golin.
2014-12-04 Bruno Cardoso Lopes[x86] Fix isOffsetSuitableForCodeModel kernel code...
2014-12-04 Weiming Zhao[AArch64] Combining Load and IntToFp should check for...
2014-12-04 Asiri RathnayakeFix yet another unseen regression caused by r223113
2014-12-04 Jonathan RoelofsFix thumbv4t indirect calls
2014-12-04 Asiri RathnayakeFix a minor regression introduced in r223113
2014-12-04 Rafael EspindolaRevert "[Thumb/Thumb2] Added restrictions on PC, LR...
2014-12-04 Michael Kuperstein[X86] Improve a dag-combine that handles a vector extra...
2014-12-04 Jyoti Allur[Thumb/Thumb2] Added restrictions on PC, LR, SP in...
2014-12-04 Andrea Di Biagio[X86] Simplify code. NFC.
2014-12-04 Elena DemikhovskyMasked Load / Store Intrinsics - the CodeGen part.
2014-12-04 Michael Liao[X86] Clean up whitespace as well as minor coding style
2014-12-04 Colin LeMahieu[Hexagon] Marking some instructions as CodeGenOnly...
2014-12-04 Michael Liao[X86] Restore X86 base pointer after call to llvm.eh...
2014-12-04 Hal Finkel[PowerPC] 'cc' should be an alias only to 'cr0'
2014-12-04 NAKAMURA TakumiHexagonMCInst.h: Qualify constants explicitly to appeas...
2014-12-04 Matt ArsenaultAllow target to specify prefix for labels
2014-12-03 Hal Finkel[PowerPC] Fix inline asm memory operands not to use r0
2014-12-03 Jacques PienaarTest commit.
2014-12-03 Sanjay Patelfix typos, grammar, formatting; NFC
2014-12-03 Colin LeMahieu[Hexagon] Converting member InstrDesc to static variable.
2014-12-03 Colin LeMahieu[Hexagon] Converting subclass members to an implicit...
2014-12-03 Will SchmidtAdd TableGen info for Power8.
2014-12-03 Roman DivackyChange the name to be in style.
2014-12-03 Tom StellardR600/SI: Move SIInsertWaits into AMDGPUPassConfig:...
2014-12-03 Tom StellardR600/SI: Don't run SI passes on R600 subtargets
2014-12-03 Tim NorthoverAArch64: fix wrong-endian parameter passing.
2014-12-03 Colin LeMahieu[NFC] Fixing pendantic warning extra semicolons.
2014-12-03 Colin LeMahieu[Hexagon] [NFC] Moving function implementations out...
2014-12-03 Colin LeMahieu[Hexagon] [NFC] Renaming *packetStart to *packetBegin
2014-12-03 Aaron BallmanSilencing a 32-bit implicit conversion warning in MSVC...
2014-12-03 Hal Finkel[PowerPC] Print all inline-asm consts as signed numbers
2014-12-03 Charlie TurnerEmit ABI_FP_rounding attribute.
2014-12-03 Matt ArsenaultR600/SI: Fix SIFixSGPRCopies for copies to physical...
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