[Orc] Fix the MSVC bots by using LLVM_EXPLICIT rather than explicit.
[oota-llvm.git] / lib / Target /
2015-02-09 Craig Topper[X86] Remove 256-bit and 512-bit memop pattern fragment...
2015-02-09 Craig Topper[X86] Remove 'memop' uses from AVX512. Use 'load' instead.
2015-02-08 Craig Topper[X86] Remove the remaining uses of memop from AVX and...
2015-02-08 Sanjay Patelfix typos; NFC
2015-02-08 Simon PilgrimMoved AVX2 vbroadcast (reg) instruction foldings under...
2015-02-08 Tim NorthoverARM & AArch64: teach LowerVSETCC that output type size...
2015-02-07 Craig Topper[X86] Add register use/def for wrmsr and rdmsr.
2015-02-07 Craig Topper[X86] Add GETSEC instruction.
2015-02-07 Simon Pilgrim[X86][AVX] Added missing stack folding support + test...
2015-02-07 Andrea Di BiagioFix typos; NFC.
2015-02-07 Hal Finkel[PowerPC] Handle loop predecessor invokes
2015-02-06 Ahmed Bougacha[AArch64] Use the source location of the IR branch...
2015-02-06 Hal FinkelRevert "r227976 - [PowerPC] Yet another approach to...
2015-02-06 Sanjay Pateluse local variables; NFC
2015-02-06 Cameron EsfahaniTest commit to see if it triggers an email to llvm...
2015-02-06 Reid KlecknerDon't dllexport declarations
2015-02-06 Benjamin KramerMake helper functions/classes/globals static. NFC.
2015-02-06 Benjamin KramerAArch64PromoteConstant: Modernize and resolve some...
2015-02-06 Michel DanzerR600/SI: Don't enable WQM for V_INTERP_* instructions v2
2015-02-06 Michel DanzerR600/SI: Also enable WQM for image opcodes which calcul...
2015-02-05 Colin LeMahieu[Hexagon] Renaming v4 compare-and-jump instructions.
2015-02-05 Colin LeMahieu[Hexagon] Deleting unused patterns.
2015-02-05 Colin LeMahieu[Hexagon] Simplifying and formatting several patterns...
2015-02-05 Colin LeMahieu[Hexagon] Factoring a class out of some store patterns...
2015-02-05 Colin LeMahieu[Hexagon] Factoring out a class for immediate transfers...
2015-02-05 Eric ChristopherRemove the use of getSubtarget in the creation of the X86
2015-02-05 Eric ChristopherUse cached subtargets inside X86FixupLEAs.
2015-02-05 Eric ChristopherMigrate the X86 AsmPrinter away from using the subtarge...
2015-02-05 Sylvestre LedruFix an incorrect identifier
2015-02-05 Colin LeMahieu[Hexagon] Renaming Y2_barrier. Fixing issues where...
2015-02-05 Hal Finkel[PowerPC] Prepare loops for pre-increment loads/stores
2015-02-05 Hal Finkel[PowerPC] Generate pre-increment floating-point ld...
2015-02-05 Colin LeMahieu[Hexagon] Renaming A2_subri, A2_andir, A2_orir. Fixing...
2015-02-05 Ahmed Bougacha[CodeGen] Add hook/combine to form vector extloads...
2015-02-05 Andrew TrickX86 ABI fix for return values > 24 bytes.
2015-02-05 Colin LeMahieu[Hexagon] Renaming A2_addi and formatting.
2015-02-05 Sanjay Patelmove fold comments to the corresponding fold; NFC
2015-02-05 Colin LeMahieu[Hexagon] Since decoding conflicts have been resolved...
2015-02-05 Tom StellardR600/SI: Fix bug in TTI loop unrolling preferences
2015-02-05 Tom StellardR600/SI: Fix bug from insertion of llvm.SI.end.cf into...
2015-02-05 Bill Schmidt[PowerPC] Implement the vclz instructions for PWR8
2015-02-05 Bruno Cardoso Lopes[X86][MMX] Handle i32->mmx conversion using movd
2015-02-05 Bruno Cardoso Lopes[X86][MMX] Move MMX DAG node to proper file
2015-02-05 Craig Topper[X86] Add xrstors/xsavec/xsaves/clflushopt/clwb/pcommit...
2015-02-05 Craig Topper[X86] Remove two feature flags that covered sets of...
2015-02-05 Matt ArsenaultR600/SI: Fix i64 truncate to i1
2015-02-05 Larisse VoufoDisable enumeral mismatch warning when compiling llvm...
2015-02-05 Cameron EsfahaniValue soft float calls as more expensive in the inliner.
2015-02-05 Colin LeMahieu[Hexagon] Deleting unused instructions and adding isCod...
2015-02-04 Colin LeMahieu[Hexagon] Updating load extend to i64 patterns.
2015-02-04 Colin LeMahieu[Hexagon] Cleaning up i1 load and extension patterns.
2015-02-04 Colin LeMahieu[Hexagon] Simplifying more load and store patterns...
2015-02-04 Tom StellardR600/SI: Enable subreg liveness by default
2015-02-04 Colin LeMahieu[Hexagon] Simplifying some load and store patterns.
2015-02-04 Colin LeMahieu[Hexagon] Converting absolute-address load patterns...
2015-02-04 Colin LeMahieu[Hexagon] Converting atomic store/load to use AddrGP...
2015-02-04 Colin LeMahieu[Hexagon] Simplifying some store patterns. Adding...
2015-02-04 Tom StellardR600/SI: Expand misaligned 16-bit memory accesses
2015-02-04 Tom StellardR600/SI: Make more store operations legal
2015-02-04 Tom StellardR600: Don't promote i64 stores to v2i32 during DAG...
2015-02-04 Colin LeMahieu[Hexagon] Adding selection for GlobalAddress and conver...
2015-02-04 Colin LeMahieu[Hexagon] Replacing some load patterns with cleaner...
2015-02-04 Colin LeMahieu[Hexagon] Adding missing isCodeGenOnly = 0
2015-02-04 Colin LeMahieu[Hexagon] Adding encoding information for absolute...
2015-02-04 Colin LeMahieu[Hexagon] Adding encoding information for absolute...
2015-02-04 Colin LeMahieu[Hexagon] Adding encoding bits for indirect long load...
2015-02-04 Bradley Smith[ARM] Fix subtarget feature set truncation when using...
2015-02-04 Zoran Jovanovic[mips][microMIPS] Implement CodeGen support for SW16...
2015-02-04 Daniel Sanders[mips] Make MipsSubtarget::hasMips*() functions consist...
2015-02-04 Renato GolinAdding support to LLVM for targeting Cortex-A72
2015-02-04 Chandler Carruth[x86] Give movss and movsd execution domains in the...
2015-02-04 Renato GolinReverting VLD1/VST1 base-updating/post-incrementing...
2015-02-04 Chandler Carruth[x86] Start to introduce bit-masking based blend lowering.
2015-02-04 Chandler Carruth[x86] Add missing patterns for andps, orps, xorps,...
2015-02-04 Bill SchmidtReplace tabs with spaces from r228116. Oops.
2015-02-04 Bill Schmidt[PowerPC] Handle 32-bit targets properly in PPCTLSDynam...
2015-02-04 Frederic RissFix some unnoticed/unwanted behavior change from r222319.
2015-02-04 Colin LeMahieu[Hexagon] Revert change to isCodeGenOnly = 1 in r228080
2015-02-04 Colin LeMahieu[Hexagon] Changing some isCodeGenOnly to isAsmParserOnl...
2015-02-03 Chandler Carruth[x86] Fix signed vs. unsigned comparison.
2015-02-03 Simon PilgrimFixed unused variable warning.
2015-02-03 Colin LeMahieu[Hexagon] Marking a bunch of non-encoded instructions...
2015-02-03 Simon Pilgrim[X86][SSE] psrl(w/d/q) and psll(w/d/q) bit shifts for...
2015-02-03 Bill Schmidt[PowerPC] Implement the vpopcnt instructions for POWER8
2015-02-03 Marek OlsakR600/SI: Remove useless patterns in VALU which are...
2015-02-03 Marek OlsakR600/SI: Rewrite VOP1InstSI to contain a pseudo and...
2015-02-03 Marek OlsakR600/SI: Fix B64 VALU shifts on VI
2015-02-03 Simon PilgrimFixed signed/unsigned comparison warning.
2015-02-03 Colin LeMahieu[Hexagon] Converting XTYPE/SHIFT intrinsics. Cleaning...
2015-02-03 Simon PilgrimFixed unused variable warning.
2015-02-03 Simon Pilgrim[X86][SSE] Added general integer shuffle matching for...
2015-02-03 Colin LeMahieu[Hexagon] Updating XTYPE/PRED intrinsics.
2015-02-03 Jingyue WuAdd straight-line strength reduction to LLVM
2015-02-03 Colin LeMahieu[Hexagon] Updating XTYPE/PERM intrinsics.
2015-02-03 Simon Pilgrim[X86][AVX2] Enabled shuffle matching for the AVX2 zero...
2015-02-03 Colin LeMahieu[Hexagon] Adding missing vector multiply instruction...
2015-02-03 Sanjay PatelMerge consecutive 16-byte loads into one 32-byte load...
2015-02-03 Sanjay Patelremove variable names from comments; NFC
2015-02-03 Colin LeMahieu[Hexagon] Converting complex number intrinsics and...
2015-02-03 Colin LeMahieu[Hexagon] Adding vector intrinsics for alu32/alu and...
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