(TZMSK64rr GR64:$src)>;
} // HasTBM
+//===----------------------------------------------------------------------===//
+// Memory Instructions
+//
+
+def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
+ "clflushopt\t$src", []>, PD;
+def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD;
+def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD;
+
+
//===----------------------------------------------------------------------===//
// Subsystems.
//===----------------------------------------------------------------------===//
// Flush cache
def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
"clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
- IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
+ IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
}
let SchedRW = [WriteNop] in {
// Load, store, and memory fence
def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
"sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
- TB, Requires<[HasSSE1]>;
+ PS, Requires<[HasSSE1]>;
def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
"lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
TB, Requires<[HasSSE2]>;
def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
"xrstor64\t$dst", []>, TB, Requires<[In64BitMode]>;
def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
- "xsaveopt\t$dst", []>, TB;
+ "xsaveopt\t$dst", []>, PS;
def XSAVEOPT64 : RI<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
- "xsaveopt64\t$dst", []>, TB, Requires<[In64BitMode]>;
+ "xsaveopt64\t$dst", []>, PS, Requires<[In64BitMode]>;
+
+ def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
+ "xrstors\t$dst", []>, TB;
+ def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
+ "xrstors64\t$dst", []>, TB, Requires<[In64BitMode]>;
+ def XSAVEC : I<0xC7, MRM4m, (outs opaque512mem:$dst), (ins),
+ "xsavec\t$dst", []>, TB;
+ def XSAVEC64 : RI<0xC7, MRM4m, (outs opaque512mem:$dst), (ins),
+ "xsavec64\t$dst", []>, TB, Requires<[In64BitMode]>;
+ def XSAVES : I<0xC7, MRM5m, (outs opaque512mem:$dst), (ins),
+ "xsaves\t$dst", []>, TB;
+ def XSAVES64 : RI<0xC7, MRM5m, (outs opaque512mem:$dst), (ins),
+ "xsaves64\t$dst", []>, TB, Requires<[In64BitMode]>;
}
} // SchedRW