[fuzzer] add -runs=N to limit the number of runs per session. Also, make sure we...
[oota-llvm.git] / lib / Target / R600 /
2015-02-04 Tom StellardR600/SI: Expand misaligned 16-bit memory accesses
2015-02-04 Tom StellardR600/SI: Make more store operations legal
2015-02-04 Tom StellardR600: Don't promote i64 stores to v2i32 during DAG...
2015-02-03 Marek OlsakR600/SI: Remove useless patterns in VALU which are...
2015-02-03 Marek OlsakR600/SI: Rewrite VOP1InstSI to contain a pseudo and...
2015-02-03 Marek OlsakR600/SI: Fix B64 VALU shifts on VI
2015-02-03 Marek OlsakR600/SI: Don't generate non-existent LSHL, LSHR, ASHR...
2015-02-03 Marek OlsakR600/SI: Remove VOP2_REV definitions from target-specif...
2015-02-03 Marek OlsakR600/SI: Trivial instruction definition corrections...
2015-02-03 Marek OlsakR600/SI: Determine target-specific encoding of READLANE...
2015-02-03 Marek OlsakR600/SI: Fix dependency between instruction writing...
2015-02-02 Tom StellardR600/SI: 64-bit and larger memory access must be at...
2015-02-01 Chandler Carruth[multiversion] Remove the function parameter from the...
2015-02-01 Chandler Carruth[multiversion] Switch the TTI queries from TargetMachin...
2015-02-01 Chandler Carruth[multiversion] Remove the cached TargetMachine pointer...
2015-02-01 Chandler Carruth[multiversion] Switch all of the targets over to use the
2015-02-01 Chandler Carruth[multiversion] Remove a false freedom to leave the...
2015-02-01 Chandler Carruth[PM] Remove a bunch of stale TTI creation method declar...
2015-01-31 Matt ArsenaultFix typo
2015-01-31 Matt ArsenaultR600/SI: Only select cvt_flr/cvt_rpi with no NaNs.
2015-01-31 Chandler Carruth[PM] Switch the TargetMachine interface from accepting...
2015-01-31 Chandler Carruth[PM] Change the core design of the TTI analysis to...
2015-01-30 Eric ChristopherReuse a bunch of cached subtargets and remove getSubtar...
2015-01-30 Tom StellardR600/SI: Handle SI_SPILL_V96_RESTORE in SIRegisterInfo...
2015-01-29 Matt ArsenaultR600/SI: Implement enableAggressiveFMAFusion
2015-01-29 Matt ArsenaultR600/SI: Add subtarget feature for if f32 fma is fast
2015-01-29 Matt ArsenaultR600/SI: Fix tonga's basic scheduling model
2015-01-29 Rafael EspindolaCompute the ELF SectionKind from the flags.
2015-01-29 Tom StellardR600/SI: Remove stray debug statements
2015-01-29 Tom StellardR600/SI: Define a schedule model and enable the generic...
2015-01-28 Tom StellardR600: Move DataLayout to AMDGPUTargetMachine
2015-01-28 Tom StellardR600: Use a Southern Islands GPU as the default for...
2015-01-27 Marek OlsakR600/SI: Fix MIN3/MAX3 on VI, define MED3
2015-01-27 Marek OlsakR600/SI: Don't set patterns for chip-specific instructi...
2015-01-27 Marek OlsakR600/SI: Add VI versions of LDS atomics
2015-01-27 Marek OlsakR600/SI: Add VI versions of MUBUF atomics
2015-01-27 Marek OlsakR600/SI: Add VI versions of MUBUF loads and stores
2015-01-27 Marek OlsakR600/SI: Add pseudos for MUBUF loads and stores
2015-01-26 Eric ChristopherMove DataLayout back to the TargetMachine from TargetSu...
2015-01-23 Tom StellardR600/SI: Emit .hsa.version section for amdhsa OS
2015-01-23 Tom StellardR600/SI: Move i64 -> v2i32 load promotion into AMDGPUDA...
2015-01-22 Jan VeselyR600: Try to use lower types for 64bit division if...
2015-01-22 Jan VeselyR600: Simplify LowerUDIVREM
2015-01-21 Matt ArsenaultR600/SI: Custom lower fround
2015-01-20 Tom StellardR600/SI: Add subtarget feature to enable VGPR spilling...
2015-01-20 Tom StellardR600/SI: Fix simple-loop.ll test
2015-01-20 Tom StellardR600/SI: Remove stray debugging code from r226586
2015-01-20 Tom StellardR600/SI: Use external symbols for scratch buffer
2015-01-20 Tom StellardR600/SI: Add kill flag when copying scratch offset...
2015-01-20 Tom StellardR600/SI: Don't store scratch buffer frame index in...
2015-01-20 Tom StellardR600/SI: Update SIInstrInfo:verifyInstruction() after...
2015-01-19 Rafael EspindolaAdd r224985 back with fixes.
2015-01-18 David Blaikiestd::unique_ptrify the MCStreamer argument to createAsm...
2015-01-15 Matt ArsenaultR600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32
2015-01-15 Matt ArsenaultR600/SI: Fix trailing comma with modifiers
2015-01-15 Marek OlsakR600/SI: Unify VOP2 instructions which are VOP3-only...
2015-01-15 Marek OlsakR600/SI: Use 64-bit encoding by default for opcodes...
2015-01-15 Marek OlsakR600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VI
2015-01-15 Marek OlsakR600/SI: Don't shrink instructions whose e32 encoding...
2015-01-15 Marek OlsakR600/SI: Add common class VOPAnyCommon
2015-01-15 Marek OlsakR600/SI: Don't select SI-only VOP3 opcodes on VI
2015-01-14 Rafael EspindolaRevert "Add r224985 back with two fixes."
2015-01-14 Tom StellardR600/SI: Use IMPLICIT_DEF and KILL when failing to...
2015-01-14 Tom StellardR600/SI: Spill VGPRs to scratch space for compute shaders
2015-01-14 Chandler Carruth[cleanup] Re-sort all the #include lines in LLVM using
2015-01-14 Matt ArsenaultR600/SI: Fix bad code with unaligned byte vector loads
2015-01-14 Matt ArsenaultImplement new way of expanding extloads.
2015-01-14 Tom StellardR600/SI: Define a schedule model
2015-01-13 Tom StellardR600/SI: Add pattern for bitcasting fp immediates to...
2015-01-13 Matt ArsenaultR600: Implement getRecipEstimate
2015-01-13 Matt ArsenaultR600: Implement getRsqrtEstimate
2015-01-13 Matt ArsenaultR600: Make cttz / ctlz cheap to speculate
2015-01-12 Matt ArsenaultR600/SI: Remove redundant setting expand on f64 vectors
2015-01-12 Tom StellardR600/SI: Use RegisterOperands to specify which operands...
2015-01-12 Rafael EspindolaAdd r224985 back with two fixes.
2015-01-08 Tom StellardR600/SI: Remove SIISelLowering::legalizeOperands()
2015-01-08 Ahmed Bougacha[SelectionDAG] Allow targets to specify legality of...
2015-01-07 Tom StellardR600/SI: Commute instructions to enable more folding...
2015-01-07 Tom StellardR600/SI: Only fold immediates that have one use
2015-01-07 Tom StellardR600/SI: Remove VReg_32 register class
2015-01-07 Tom StellardR600/SI: Add a V_MOV_B64 pseudo instruction
2015-01-07 Tom StellardR600/SI: Teach SIFoldOperands to split 64-bit constants...
2015-01-07 Tom StellardR600/SI: Refactor SIFoldOperands to simplify immediate...
2015-01-06 Matt ArsenaultR600/SI: Add combine for isinfinite pattern
2015-01-06 Matt ArsenaultR600/SI: Pattern match isinf to v_cmp_class instructions
2015-01-06 Matt ArsenaultR600/SI: Add basic DAG combines for fp_class
2015-01-06 Matt ArsenaultR600/SI: Add class intrinsic
2015-01-06 Tom StellardR600/SI: Insert s_waitcnt before s_barrier instructions.
2015-01-06 Tom StellardR600/SI: Fix dependency calculation for DS writes instr...
2015-01-06 Tom StellardR600/SI: Add a stub GCNTargetMachine
2015-01-06 Tom StellardR600/SI: Remove MachineFunction dump from AsmPrinter
2015-01-06 Lang HamesRevert r225048: It broke ObjC on AArch64.
2015-01-03 Craig TopperMinor cleanup to all the switches after MatchInstructio...
2014-12-31 Rafael EspindolaAdd r224985 back with a fix.
2014-12-31 Rafael EspindolaRevert "Remove doesSectionRequireSymbols."
2014-12-30 Rafael EspindolaRemove doesSectionRequireSymbols.
2014-12-21 Matt ArsenaultEnable (sext x) == C --> x == (trunc C) combine
2014-12-19 Matt ArsenaultR600: Remove outdated comment
2014-12-19 Matt ArsenaultR600/SI: Only form min/max with 1 use.
2014-12-19 Tom StellardR600/SI: isLegalOperand() shouldn't check constant...
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