[SelectionDAG] Allow targets to specify legality of extloads' result
authorAhmed Bougacha <ahmed.bougacha@gmail.com>
Thu, 8 Jan 2015 00:51:32 +0000 (00:51 +0000)
committerAhmed Bougacha <ahmed.bougacha@gmail.com>
Thu, 8 Jan 2015 00:51:32 +0000 (00:51 +0000)
commit7fac1d945f6d1a72e4e2b6de3c2acc8bee1bf9d1
tree0ae5dd2515018faade51113019144da33837366a
parentf411a8dd29ae9cf1c2e318c7de0d9b26ebf8af18
[SelectionDAG] Allow targets to specify legality of extloads' result
type (in addition to the memory type).

The *LoadExt* legalization handling used to only have one type, the
memory type.  This forced users to assume that as long as the extload
for the memory type was declared legal, and the result type was legal,
the whole extload was legal.

However, this isn't always the case.  For instance, on X86, with AVX,
this is legal:
    v4i32 load, zext from v4i8
but this isn't:
    v4i64 load, zext from v4i8
Whereas v4i64 is (arguably) legal, even without AVX2.

Note that the same thing was done a while ago for truncstores (r46140),
but I assume no one needed it yet for extloads, so here we go.

Calls to getLoadExtAction were changed to add the value type, found
manually in the surrounding code.

Calls to setLoadExtAction were mechanically changed, by wrapping the
call in a loop, to match previous behavior.  The loop iterates over
the MVT subrange corresponding to the memory type (FP vectors, etc...).
I also pulled neighboring setTruncStoreActions into some of the loops;
those shouldn't make a difference, as the additional types are illegal.
(e.g., i128->i1 truncstores on PPC.)

No functional change intended.

Differential Revision: http://reviews.llvm.org/D6532

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225421 91177308-0d34-0410-b5e6-96231b3b80d8
21 files changed:
include/llvm/Target/TargetLowering.h
lib/CodeGen/BasicTargetTransformInfo.cpp
lib/CodeGen/CodeGenPrepare.cpp
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
lib/Target/AArch64/AArch64ISelLowering.cpp
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/Hexagon/HexagonISelLowering.cpp
lib/Target/MSP430/MSP430ISelLowering.cpp
lib/Target/Mips/MipsISelLowering.cpp
lib/Target/Mips/MipsSEISelLowering.cpp
lib/Target/NVPTX/NVPTXISelLowering.cpp
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/R600/AMDGPUISelLowering.cpp
lib/Target/R600/R600ISelLowering.cpp
lib/Target/R600/SIISelLowering.cpp
lib/Target/Sparc/SparcISelLowering.cpp
lib/Target/SystemZ/SystemZISelLowering.cpp
lib/Target/X86/X86ISelLowering.cpp
lib/Target/XCore/XCoreISelLowering.cpp