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Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count trailing/leading zeros)
[oota-llvm.git]
/
lib
/
Target
/
Hexagon
/
HexagonInstrInfoV4.td
2012-12-04
Jyotsna Verma
Add patterns to define 'combine', 'tstbit', 'ct0/cl0...
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2012-12-03
Jyotsna Verma
Define store instructions with base+immediate offset...
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2012-11-30
Jyotsna Verma
Use multiclass for the store instructions with MEMri...
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2012-11-30
Jyotsna Verma
Use multiclass for the load instructions with 'base...
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2012-11-20
Jyotsna Verma
Removing some unused instruction definitions from the...
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2012-11-14
Jyotsna Verma
Added multiclass for post-increment load instructions.
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2012-07-13
Jakob Stoklund Olesen
Remove variable_ops from call instructions in most...
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2012-05-14
Brendon Cahoon
Revert 156634 upon request until code improvement chang...
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2012-05-11
Brendon Cahoon
Hexagon constant extender support.
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2012-05-08
Sirish Pande
Update load/store instruction patterns in Hexagon V4.
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2012-05-03
Sirish Pande
Extensions of Hexagon V4 instructions.
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2012-04-23
Chandler Carruth
Revert r155365, r155366, and r155367. All three of...
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2012-04-23
Sirish Pande
Support for Hexagon VLIW Packetizer.
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2012-04-18
Chandler Carruth
This reverts a long string of commits to the Hexagon...
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2012-04-12
Sirish Pande
HexagonPacketizer patch.
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2012-02-15
Sirish Pande
Optimize redundant sign extends and negation of predicates.
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2012-02-15
Eric Christopher
Revert "Optimize redundant sign extends and negation...
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2012-02-15
Sirish Pande
Optimize redundant sign extends and negation of predicates
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2012-02-08
Brendon Cahoon
Use TSFlag bit to describe instruction properties.
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2011-12-12
Tony Linthicum
Hexagon backend support
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