Hexagon constant extender support.

Patch by Jyotsna Verma.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156634 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/CMakeLists.txt b/lib/Target/Hexagon/CMakeLists.txt
index 29cf8a76c4fef9481e9353c0dd0694f8dc015bf1..8ccecb13cd5cff1161856e74cf26972d2ca989f1 100644 (file)
--- a/lib/Target/Hexagon/CMakeLists.txt
+++ b/lib/Target/Hexagon/CMakeLists.txt
@@ -29,6 +29,7 @@ add_llvm_target(HexagonCodeGen
   HexagonTargetMachine.cpp
   HexagonTargetObjectFile.cpp
   HexagonVLIWPacketizer.cpp
+  HexagonOptimizeConstExt.cpp
 )
 
 add_subdirectory(TargetInfo)

diff --git a/lib/Target/Hexagon/Hexagon.h b/lib/Target/Hexagon/Hexagon.h
index b8dc24fd3e2238c9fbdbc671a1b8f27903323802..d73be80f5301a05fecee0bc82b8bcbf4077203b0 100644 (file)
--- a/lib/Target/Hexagon/Hexagon.h
+++ b/lib/Target/Hexagon/Hexagon.h
@@ -36,7 +36,7 @@ namespace llvm {
 
   FunctionPass *createHexagonSplitTFRCondSets(HexagonTargetMachine &TM);
   FunctionPass *createHexagonExpandPredSpillCode(HexagonTargetMachine &TM);
-
+  FunctionPass *createHexagonOptimizeConstExt(HexagonTargetMachine &TM);
   FunctionPass *createHexagonHardwareLoops();
   FunctionPass *createHexagonPeephole();
   FunctionPass *createHexagonFixupHwLoops();

diff --git a/lib/Target/Hexagon/HexagonCExtTable.h b/lib/Target/Hexagon/HexagonCExtTable.h
new file mode 100644 (file)
index 0000000..4e5ac1e
--- /dev/null
+++ b/lib/Target/Hexagon/HexagonCExtTable.h
@@ -0,0 +1,1898 @@
+//===--- HexagonCExttable.h - Instruction constant extender table info. ---===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// HexagonCExt table maps the constant extended form of an instruction to
+// the non-extended form. In addition, it also contains other information,
+// such as the extended operand number and their min/max values.
+//===----------------------------------------------------------------------===//
+
+#ifndef HEXAGONCEXTTABLE_H
+#define HEXAGONCEXTTABLE_H
+
+const HexagonConstExtInfo HexagonCExt[] = {
+  {"PHI", -1, 0, 0, -1},
+  {"INLINEASM", -1, 0, 0, -1},
+  {"PROLOG_LABEL", -1, 0, 0, -1},
+  {"EH_LABEL", -1, 0, 0, -1},
+  {"GC_LABEL", -1, 0, 0, -1},
+  {"KILL", -1, 0, 0, -1},
+  {"EXTRACT_SUBREG", -1, 0, 0, -1},
+  {"INSERT_SUBREG", -1, 0, 0, -1},
+  {"IMPLICIT_DEF", -1, 0, 0, -1},
+  {"SUBREG_TO_REG", -1, 0, 0, -1},
+  {"COPY_TO_REGCLASS", -1, 0, 0, -1},
+  {"DBG_VALUE", -1, 0, 0, -1},
+  {"REG_SEQUENCE", -1, 0, 0, -1},
+  {"COPY", -1, 0, 0, -1},
+  {"BUNDLE", -1, 0, 0, -1},
+  {"ADD64_rr", -1, 0, 0, -1},
+  {"ADDASL", -1, 0, 0, -1},
+  {"ADD_ri", 2, -32768, 32767, Hexagon::ADD_rr},
+  {"ADD_ri_cNotPt", 3, -128, 127, Hexagon::ADD_rr_cNotPt},
+  {"ADD_ri_cPt", 3, -128, 127, Hexagon::ADD_rr_cPt},
+  {"ADD_ri_cdnNotPt", 3, -128, 127, Hexagon::ADD_rr_cdnNotPt},
+  {"ADD_ri_cdnPt", 3, -128, 127, Hexagon::ADD_rr_cdnPt},
+  {"ADD_rr", -1, 0, 0, -1},
+  {"ADD_rr_cNotPt", -1, 0, 0, -1},
+  {"ADD_rr_cPt", -1, 0, 0, -1},
+  {"ADD_rr_cdnNotPt", -1, 0, 0, -1},
+  {"ADD_rr_cdnPt", -1, 0, 0, -1},
+  {"ADDi_ASLri_V4", 1, 0, 255, -1},
+  {"ADDi_LSRri_V4", 1, 0, 255, -1},
+  {"ADDi_MPYri_V4", 1, 0, 63, -1},
+  {"ADDi_MPYrr_V4", 1, 0, 63, Hexagon::ADDr_MPYrr_V4},
+  {"ADDr_ADDri_V4", 3, -32, 31, -1},
+  {"ADDr_MPYir_V4", -1, 0, 0, -1},
+  {"ADDr_MPYri_V4", 3, 0, 63, Hexagon::ADDr_MPYrr_V4},
+  {"ADDr_MPYrr_V4", -1, 0, 0, -1},
+  {"ADDr_SUBri_V4", 2, -32, 31, -1},
+  {"ADDri_SUBr_V4", 2, -32, 31, -1},
+  {"ADDri_acc", 3, -128, 127, Hexagon::ADDrr_acc},
+  {"ADDrr_acc", -1, 0, 0, -1},
+  {"ADJCALLSTACKDOWN", -1, 0, 0, -1},
+  {"ADJCALLSTACKUP", -1, 0, 0, -1},
+  {"ADJDYNALLOC", -1, 0, 0, -1},
+  {"ALLOCFRAME", -1, 0, 0, -1},
+  {"ALL_pp", -1, 0, 0, -1},
+  {"AND_pnotp", -1, 0, 0, -1},
+  {"AND_pp", -1, 0, 0, -1},
+  {"AND_ri", 2, -512, 511, Hexagon::AND_rr},
+  {"AND_rr", -1, 0, 0, -1},
+  {"AND_rr64", -1, 0, 0, -1},
+  {"AND_rr_cNotPt", -1, 0, 0, -1},
+  {"AND_rr_cPt", -1, 0, 0, -1},
+  {"AND_rr_cdnNotPt", -1, 0, 0, -1},
+  {"AND_rr_cdnPt", -1, 0, 0, -1},
+  {"ANDd_NOTd_V4", -1, 0, 0, -1},
+  {"ANDi_ASLri_V4", 1, 0, 255, -1},
+  {"ANDi_LSRri_V4", 1, 0, 255, -1},
+  {"ANDr_ANDr_NOTr_V4", -1, 0, 0, -1},
+  {"ANDr_ANDrr_V4", -1, 0, 0, -1},
+  {"ANDr_ORrr_V4", -1, 0, 0, -1},
+  {"ANDr_XORrr_V4", -1, 0, 0, -1},
+  {"ANY_pp", -1, 0, 0, -1},
+  {"ARGEXTEND", -1, 0, 0, -1},
+  {"ASL", -1, 0, 0, -1},
+  {"ASLH", -1, 0, 0, -1},
+  {"ASLH_cNotPt_V4", -1, 0, 0, -1},
+  {"ASLH_cPt_V4", -1, 0, 0, -1},
+  {"ASLH_cdnNotPt_V4", -1, 0, 0, -1},
+  {"ASLH_cdnPt_V4", -1, 0, 0, -1},
+  {"ASL_ADD_ri", -1, 0, 0, -1},
+  {"ASL_ADD_rr", -1, 0, 0, -1},
+  {"ASL_ADDd_ri", -1, 0, 0, -1},
+  {"ASL_ADDd_rr", -1, 0, 0, -1},
+  {"ASL_AND_ri", -1, 0, 0, -1},
+  {"ASL_AND_rr", -1, 0, 0, -1},
+  {"ASL_ANDd_ri", -1, 0, 0, -1},
+  {"ASL_ANDd_rr", -1, 0, 0, -1},
+  {"ASL_OR_ri", -1, 0, 0, -1},
+  {"ASL_OR_rr", -1, 0, 0, -1},
+  {"ASL_ORd_ri", -1, 0, 0, -1},
+  {"ASL_ORd_rr", -1, 0, 0, -1},
+  {"ASL_SUB_ri", -1, 0, 0, -1},
+  {"ASL_SUB_rr", -1, 0, 0, -1},
+  {"ASL_SUBd_ri", -1, 0, 0, -1},
+  {"ASL_SUBd_rr", -1, 0, 0, -1},
+  {"ASL_XOR_ri", -1, 0, 0, -1},
+  {"ASL_XORd_ri", -1, 0, 0, -1},
+  {"ASL_rr", -1, 0, 0, -1},
+  {"ASLd", -1, 0, 0, -1},
+  {"ASLd_ri", -1, 0, 0, -1},
+  {"ASLd_rr_xor_V4", -1, 0, 0, -1},
+  {"ASRH", -1, 0, 0, -1},
+  {"ASRH_cNotPt_V4", -1, 0, 0, -1},
+  {"ASRH_cPt_V4", -1, 0, 0, -1},
+  {"ASRH_cdnNotPt_V4", -1, 0, 0, -1},
+  {"ASRH_cdnPt_V4", -1, 0, 0, -1},
+  {"ASR_ADD_ri", -1, 0, 0, -1},
+  {"ASR_ADD_rr", -1, 0, 0, -1},
+  {"ASR_ADDd_ri", -1, 0, 0, -1},
+  {"ASR_ADDd_rr", -1, 0, 0, -1},
+  {"ASR_AND_ri", -1, 0, 0, -1},
+  {"ASR_AND_rr", -1, 0, 0, -1},
+  {"ASR_ANDd_ri", -1, 0, 0, -1},
+  {"ASR_ANDd_rr", -1, 0, 0, -1},
+  {"ASR_OR_ri", -1, 0, 0, -1},
+  {"ASR_OR_rr", -1, 0, 0, -1},
+  {"ASR_ORd_ri", -1, 0, 0, -1},
+  {"ASR_ORd_rr", -1, 0, 0, -1},
+  {"ASR_SUB_ri", -1, 0, 0, -1},
+  {"ASR_SUB_rr", -1, 0, 0, -1},
+  {"ASR_SUBd_ri", -1, 0, 0, -1},
+  {"ASR_SUBd_rr", -1, 0, 0, -1},
+  {"ASR_ri", -1, 0, 0, -1},
+  {"ASR_rr", -1, 0, 0, -1},
+  {"ASRd_ri", -1, 0, 0, -1},
+  {"ASRd_rr", -1, 0, 0, -1},
+  {"ASRd_rr_xor_V4", -1, 0, 0, -1},
+  {"BARRIER", -1, 0, 0, -1},
+  {"BRCOND", -1, 0, 0, -1},
+  {"BR_JT", -1, 0, 0, -1},
+  {"CALL", -1, 0, 0, -1},
+  {"CALLR", -1, 0, 0, -1},
+  {"CALLRv3", -1, 0, 0, -1},
+  {"CALLv3", -1, 0, 0, -1},
+  {"CLRBIT", -1, 0, 0, -1},
+  {"CLRBIT_31", -1, 0, 0, -1},
+  {"CMPEHexagon4rr", -1, 0, 0, -1},
+  {"CMPEQri", 2, -512, 511, Hexagon::CMPEQrr},
+  {"CMPEQrr", -1, 0, 0, -1},
+  {"CMPGEUri", 2, 0, 255, -1},
+  {"CMPGEri", 2, -128, 127, -1},
+  {"CMPGT64rr", -1, 0, 0, -1},
+  {"CMPGTU64rr", -1, 0, 0, -1},
+  {"CMPGTUri", 2, 0, 511, Hexagon::CMPGTUrr},
+  {"CMPGTUrr", -1, 0, 0, -1},
+  {"CMPGTri", 2, -512, 511, Hexagon::CMPGTrr},
+  {"CMPGTrr", -1, 0, 0, -1},
+  {"CMPLTUrr", -1, 0, 0, -1},
+  {"CMPLTrr", -1, 0, 0, -1},
+  {"CMPbEQri_V4", -1, 0, 0, -1},
+  {"CMPbEQrr_sbsb_V4", -1, 0, 0, -1},
+  {"CMPbEQrr_ubub_V4", -1, 0, 0, -1},
+  {"CMPbGTUri_V4", 2, 0, 127, Hexagon::CMPbGTUrr_V4},
+  {"CMPbGTUrr_V4", -1, 0, 0, -1},
+  {"CMPbGTrr_V4", -1, 0, 0, -1},
+  {"CMPhEQri_V4", -1, 0, 0, -1},
+  {"CMPhEQrr_shl_V4", -1, 0, 0, -1},
+  {"CMPhEQrr_xor_V4", -1, 0, 0, -1},
+  {"CMPhGTUri_V4", 2, 0, 127, Hexagon::CMPhGTUrr_V4},
+  {"CMPhGTUrr_V4", -1, 0, 0, -1},
+  {"CMPhGTrr_shl_V4", -1, 0, 0, -1},
+  {"COMBINE_ii", -1, 0, 0, -1},
+  {"COMBINE_ir_V4", -1, 0, 0, -1},
+  {"COMBINE_ri_V4", -1, 0, 0, -1},
+  {"COMBINE_rr", -1, 0, 0, -1},
+  {"COMBINE_rr_cNotPt", -1, 0, 0, -1},
+  {"COMBINE_rr_cPt", -1, 0, 0, -1},
+  {"COMBINE_rr_cdnNotPt", -1, 0, 0, -1},
+  {"COMBINE_rr_cdnPt", -1, 0, 0, -1},
+  {"CONST32", -1, 0, 0, -1},
+  {"CONST32GP_set", -1, 0, 0, -1},
+  {"CONST32_Float_Real", -1, 0, 0, -1},
+  {"CONST32_Int_Real", -1, 0, 0, -1},
+  {"CONST32_Label", -1, 0, 0, -1},
+  {"CONST32_set", -1, 0, 0, -1},
+  {"CONST32_set_jt", -1, 0, 0, -1},
+  {"CONST64_Float_Real", -1, 0, 0, -1},
+  {"CONST64_Int_Real", -1, 0, 0, -1},
+  {"CONVERT_d2df", -1, 0, 0, -1},
+  {"CONVERT_d2sf", -1, 0, 0, -1},
+  {"CONVERT_df2d", -1, 0, 0, -1},
+  {"CONVERT_df2d_nchop", -1, 0, 0, -1},
+  {"CONVERT_df2sf", -1, 0, 0, -1},
+  {"CONVERT_df2ud", -1, 0, 0, -1},
+  {"CONVERT_df2ud_nchop", -1, 0, 0, -1},
+  {"CONVERT_df2uw", -1, 0, 0, -1},
+  {"CONVERT_df2uw_nchop", -1, 0, 0, -1},
+  {"CONVERT_df2w", -1, 0, 0, -1},
+  {"CONVERT_df2w_nchop", -1, 0, 0, -1},
+  {"CONVERT_sf2d", -1, 0, 0, -1},
+  {"CONVERT_sf2d_nchop", -1, 0, 0, -1},
+  {"CONVERT_sf2df", -1, 0, 0, -1},
+  {"CONVERT_sf2ud", -1, 0, 0, -1},
+  {"CONVERT_sf2ud_nchop", -1, 0, 0, -1},
+  {"CONVERT_sf2uw", -1, 0, 0, -1},
+  {"CONVERT_sf2uw_nchop", -1, 0, 0, -1},
+  {"CONVERT_sf2w", -1, 0, 0, -1},
+  {"CONVERT_sf2w_nchop", -1, 0, 0, -1},
+  {"CONVERT_ud2df", -1, 0, 0, -1},
+  {"CONVERT_ud2sf", -1, 0, 0, -1},
+  {"CONVERT_uw2df", -1, 0, 0, -1},
+  {"CONVERT_uw2sf", -1, 0, 0, -1},
+  {"CONVERT_w2df", -1, 0, 0, -1},
+  {"CONVERT_w2sf", -1, 0, 0, -1},
+  {"DEALLOCFRAME", -1, 0, 0, -1},
+  {"DEALLOC_RET_V4", -1, 0, 0, -1},
+  {"DEALLOC_RET_cNotPt_V4", -1, 0, 0, -1},
+  {"DEALLOC_RET_cNotdnPnt_V4", -1, 0, 0, -1},
+  {"DEALLOC_RET_cNotdnPt_V4", -1, 0, 0, -1},
+  {"DEALLOC_RET_cPt_V4", -1, 0, 0, -1},
+  {"DEALLOC_RET_cdnPnt_V4", -1, 0, 0, -1},
+  {"DEALLOC_RET_cdnPt_V4", -1, 0, 0, -1},
+  {"ENDLOOP0", -1, 0, 0, -1},
+  {"FCMPOEQ32_rr", -1, 0, 0, -1},
+  {"FCMPOEQ64_rr", -1, 0, 0, -1},
+  {"FCMPOGE32_rr", -1, 0, 0, -1},
+  {"FCMPOGE64_rr", -1, 0, 0, -1},
+  {"FCMPOGT32_rr", -1, 0, 0, -1},
+  {"FCMPOGT64_rr", -1, 0, 0, -1},
+  {"FCMPUEQ32_rr", -1, 0, 0, -1},
+  {"FCMPUEQ64_rr", -1, 0, 0, -1},
+  {"FCMPUGE32_rr", -1, 0, 0, -1},
+  {"FCMPUGE64_rr", -1, 0, 0, -1},
+  {"FCMPUGT32_rr", -1, 0, 0, -1},
+  {"FCMPUGT64_rr", -1, 0, 0, -1},
+  {"FCONST32_nsdata", -1, 0, 0, -1},
+  {"FMADD_dp", -1, 0, 0, -1},
+  {"FMADD_sp", -1, 0, 0, -1},
+  {"FMAX_dp", -1, 0, 0, -1},
+  {"FMAX_sp", -1, 0, 0, -1},
+  {"FMIN_dp", -1, 0, 0, -1},
+  {"FMIN_sp", -1, 0, 0, -1},
+  {"HEXAGON_A4_cround_ri", -1, 0, 0, -1},
+  {"HEXAGON_A4_cround_rr", -1, 0, 0, -1},
+  {"HEXAGON_A4_modwrapu", -1, 0, 0, -1},
+  {"HEXAGON_A4_round_ri", -1, 0, 0, -1},
+  {"HEXAGON_A4_round_ri_sat", -1, 0, 0, -1},
+  {"HEXAGON_A4_round_rr", -1, 0, 0, -1},
+  {"HEXAGON_A4_round_rr_sat", -1, 0, 0, -1},
+  {"HEXAGON_C2_bitsclr", -1, 0, 0, -1},
+  {"HEXAGON_C2_bitsclri", -1, 0, 0, -1},
+  {"HEXAGON_C2_bitsset", -1, 0, 0, -1},
+  {"HEXAGON_M4_and_and", -1, 0, 0, -1},
+  {"HEXAGON_M4_and_andn", -1, 0, 0, -1},
+  {"HEXAGON_M4_and_or", -1, 0, 0, -1},
+  {"HEXAGON_M4_and_xor", -1, 0, 0, -1},
+  {"HEXAGON_M4_or_and", -1, 0, 0, -1},
+  {"HEXAGON_M4_or_andn", -1, 0, 0, -1},
+  {"HEXAGON_M4_or_or", -1, 0, 0, -1},
+  {"HEXAGON_M4_or_xor", -1, 0, 0, -1},
+  {"HEXAGON_M4_xor_and", -1, 0, 0, -1},
+  {"HEXAGON_M4_xor_andn", -1, 0, 0, -1},
+  {"HEXAGON_M4_xor_or", -1, 0, 0, -1},
+  {"HEXAGON_S2_brev", -1, 0, 0, -1},
+  {"HEXAGON_S2_deinterleave", -1, 0, 0, -1},
+  {"HEXAGON_S2_insert", -1, 0, 0, -1},
+  {"HEXAGON_S2_insert_rp", -1, 0, 0, -1},
+  {"HEXAGON_S2_insertp", -1, 0, 0, -1},
+  {"HEXAGON_S2_insertp_rp", -1, 0, 0, -1},
+  {"HEXAGON_S2_interleave", -1, 0, 0, -1},
+  {"HEXAGON_S2_lfsp", -1, 0, 0, -1},
+  {"HEXAGON_S2_tableidxb_goodsyntax", -1, 0, 0, -1},
+  {"HEXAGON_S2_tableidxd_goodsyntax", -1, 0, 0, -1},
+  {"HEXAGON_S2_tableidxh_goodsyntax", -1, 0, 0, -1},
+  {"HEXAGON_S2_tableidxw_goodsyntax", -1, 0, 0, -1},
+  {"HEXAGON_S2_vspliceib", -1, 0, 0, -1},
+  {"HEXAGON_S2_vsplicerb", -1, 0, 0, -1},
+  {"HEXAGON_S4_or_andi", -1, 0, 0, -1},
+  {"HEXAGON_S4_or_andix", -1, 0, 0, -1},
+  {"HEXAGON_S4_or_ori", -1, 0, 0, -1},
+  {"HI", -1, 0, 0, -1},
+  {"HI_jt", -1, 0, 0, -1},
+  {"HI_label", -1, 0, 0, -1},
+  {"HIi", -1, 0, 0, -1},
+  {"Hexagon_A2_abs", -1, 0, 0, -1},
+  {"Hexagon_A2_absp", -1, 0, 0, -1},
+  {"Hexagon_A2_abssat", -1, 0, 0, -1},
+  {"Hexagon_A2_add", -1, 0, 0, -1},
+  {"Hexagon_A2_addh_h16_hh", -1, 0, 0, -1},
+  {"Hexagon_A2_addh_h16_hl", -1, 0, 0, -1},
+  {"Hexagon_A2_addh_h16_lh", -1, 0, 0, -1},
+  {"Hexagon_A2_addh_h16_ll", -1, 0, 0, -1},
+  {"Hexagon_A2_addh_h16_sat_hh", -1, 0, 0, -1},
+  {"Hexagon_A2_addh_h16_sat_hl", -1, 0, 0, -1},
+  {"Hexagon_A2_addh_h16_sat_lh", -1, 0, 0, -1},
+  {"Hexagon_A2_addh_h16_sat_ll", -1, 0, 0, -1},
+  {"Hexagon_A2_addh_l16_hl", -1, 0, 0, -1},
+  {"Hexagon_A2_addh_l16_ll", -1, 0, 0, -1},
+  {"Hexagon_A2_addh_l16_sat_hl", -1, 0, 0, -1},
+  {"Hexagon_A2_addh_l16_sat_ll", -1, 0, 0, -1},
+  {"Hexagon_A2_addi", -1, 0, 0, -1},
+  {"Hexagon_A2_addp", -1, 0, 0, -1},
+  {"Hexagon_A2_addpsat", -1, 0, 0, -1},
+  {"Hexagon_A2_addsat", -1, 0, 0, -1},
+  {"Hexagon_A2_addsp", -1, 0, 0, -1},
+  {"Hexagon_A2_and", -1, 0, 0, -1},
+  {"Hexagon_A2_andir", -1, 0, 0, -1},
+  {"Hexagon_A2_andp", -1, 0, 0, -1},
+  {"Hexagon_A2_aslh", -1, 0, 0, -1},
+  {"Hexagon_A2_asrh", -1, 0, 0, -1},
+  {"Hexagon_A2_combine_hh", -1, 0, 0, -1},
+  {"Hexagon_A2_combine_hl", -1, 0, 0, -1},
+  {"Hexagon_A2_combine_lh", -1, 0, 0, -1},
+  {"Hexagon_A2_combine_ll", -1, 0, 0, -1},
+  {"Hexagon_A2_combineii", -1, 0, 0, -1},
+  {"Hexagon_A2_combinew", -1, 0, 0, -1},
+  {"Hexagon_A2_max", -1, 0, 0, -1},
+  {"Hexagon_A2_maxp", -1, 0, 0, -1},
+  {"Hexagon_A2_maxu", -1, 0, 0, -1},
+  {"Hexagon_A2_maxup", -1, 0, 0, -1},
+  {"Hexagon_A2_min", -1, 0, 0, -1},
+  {"Hexagon_A2_minu", -1, 0, 0, -1},
+  {"Hexagon_A2_neg", -1, 0, 0, -1},
+  {"Hexagon_A2_negp", -1, 0, 0, -1},
+  {"Hexagon_A2_negsat", -1, 0, 0, -1},
+  {"Hexagon_A2_not", -1, 0, 0, -1},
+  {"Hexagon_A2_notp", -1, 0, 0, -1},
+  {"Hexagon_A2_or", -1, 0, 0, -1},
+  {"Hexagon_A2_orir", -1, 0, 0, -1},
+  {"Hexagon_A2_orp", -1, 0, 0, -1},
+  {"Hexagon_A2_sat", -1, 0, 0, -1},
+  {"Hexagon_A2_satb", -1, 0, 0, -1},
+  {"Hexagon_A2_sath", -1, 0, 0, -1},
+  {"Hexagon_A2_satub", -1, 0, 0, -1},
+  {"Hexagon_A2_satuh", -1, 0, 0, -1},
+  {"Hexagon_A2_sub", -1, 0, 0, -1},
+  {"Hexagon_A2_subh_h16_hh", -1, 0, 0, -1},
+  {"Hexagon_A2_subh_h16_hl", -1, 0, 0, -1},
+  {"Hexagon_A2_subh_h16_lh", -1, 0, 0, -1},
+  {"Hexagon_A2_subh_h16_ll", -1, 0, 0, -1},
+  {"Hexagon_A2_subh_h16_sat_hh", -1, 0, 0, -1},
+  {"Hexagon_A2_subh_h16_sat_hl", -1, 0, 0, -1},
+  {"Hexagon_A2_subh_h16_sat_lh", -1, 0, 0, -1},
+  {"Hexagon_A2_subh_h16_sat_ll", -1, 0, 0, -1},
+  {"Hexagon_A2_subh_l16_hl", -1, 0, 0, -1},
+  {"Hexagon_A2_subh_l16_ll", -1, 0, 0, -1},
+  {"Hexagon_A2_subh_l16_sat_hl", -1, 0, 0, -1},
+  {"Hexagon_A2_subh_l16_sat_ll", -1, 0, 0, -1},
+  {"Hexagon_A2_subp", -1, 0, 0, -1},
+  {"Hexagon_A2_subri", -1, 0, 0, -1},
+  {"Hexagon_A2_subsat", -1, 0, 0, -1},
+  {"Hexagon_A2_svaddh", -1, 0, 0, -1},
+  {"Hexagon_A2_svaddhs", -1, 0, 0, -1},
+  {"Hexagon_A2_svadduhs", -1, 0, 0, -1},
+  {"Hexagon_A2_svavgh", -1, 0, 0, -1},
+  {"Hexagon_A2_svavghs", -1, 0, 0, -1},
+  {"Hexagon_A2_svnavgh", -1, 0, 0, -1},
+  {"Hexagon_A2_svsubh", -1, 0, 0, -1},
+  {"Hexagon_A2_svsubhs", -1, 0, 0, -1},
+  {"Hexagon_A2_svsubuhs", -1, 0, 0, -1},
+  {"Hexagon_A2_swiz", -1, 0, 0, -1},
+  {"Hexagon_A2_sxtb", -1, 0, 0, -1},
+  {"Hexagon_A2_sxth", -1, 0, 0, -1},
+  {"Hexagon_A2_sxtw", -1, 0, 0, -1},
+  {"Hexagon_A2_tfr", -1, 0, 0, -1},
+  {"Hexagon_A2_tfrih", -1, 0, 0, -1},
+  {"Hexagon_A2_tfril", -1, 0, 0, -1},
+  {"Hexagon_A2_tfrp", -1, 0, 0, -1},
+  {"Hexagon_A2_tfrpi", -1, 0, 0, -1},
+  {"Hexagon_A2_tfrsi", -1, 0, 0, -1},
+  {"Hexagon_A2_vabsh", -1, 0, 0, -1},
+  {"Hexagon_A2_vabshsat", -1, 0, 0, -1},
+  {"Hexagon_A2_vabsw", -1, 0, 0, -1},
+  {"Hexagon_A2_vabswsat", -1, 0, 0, -1},
+  {"Hexagon_A2_vaddh", -1, 0, 0, -1},
+  {"Hexagon_A2_vaddhs", -1, 0, 0, -1},
+  {"Hexagon_A2_vaddub", -1, 0, 0, -1},
+  {"Hexagon_A2_vaddubs", -1, 0, 0, -1},
+  {"Hexagon_A2_vadduhs", -1, 0, 0, -1},
+  {"Hexagon_A2_vaddw", -1, 0, 0, -1},
+  {"Hexagon_A2_vaddws", -1, 0, 0, -1},
+  {"Hexagon_A2_vavgh", -1, 0, 0, -1},
+  {"Hexagon_A2_vavghcr", -1, 0, 0, -1},
+  {"Hexagon_A2_vavghr", -1, 0, 0, -1},
+  {"Hexagon_A2_vavgub", -1, 0, 0, -1},
+  {"Hexagon_A2_vavgubr", -1, 0, 0, -1},
+  {"Hexagon_A2_vavguh", -1, 0, 0, -1},
+  {"Hexagon_A2_vavguhr", -1, 0, 0, -1},
+  {"Hexagon_A2_vavguw", -1, 0, 0, -1},
+  {"Hexagon_A2_vavguwr", -1, 0, 0, -1},
+  {"Hexagon_A2_vavgw", -1, 0, 0, -1},
+  {"Hexagon_A2_vavgwcr", -1, 0, 0, -1},
+  {"Hexagon_A2_vavgwr", -1, 0, 0, -1},
+  {"Hexagon_A2_vcmpbeq", -1, 0, 0, -1},
+  {"Hexagon_A2_vcmpbgtu", -1, 0, 0, -1},
+  {"Hexagon_A2_vcmpheq", -1, 0, 0, -1},
+  {"Hexagon_A2_vcmphgt", -1, 0, 0, -1},
+  {"Hexagon_A2_vcmphgtu", -1, 0, 0, -1},
+  {"Hexagon_A2_vcmpweq", -1, 0, 0, -1},
+  {"Hexagon_A2_vcmpwgt", -1, 0, 0, -1},
+  {"Hexagon_A2_vcmpwgtu", -1, 0, 0, -1},
+  {"Hexagon_A2_vconj", -1, 0, 0, -1},
+  {"Hexagon_A2_vmaxh", -1, 0, 0, -1},
+  {"Hexagon_A2_vmaxub", -1, 0, 0, -1},
+  {"Hexagon_A2_vmaxuh", -1, 0, 0, -1},
+  {"Hexagon_A2_vmaxuw", -1, 0, 0, -1},
+  {"Hexagon_A2_vmaxw", -1, 0, 0, -1},
+  {"Hexagon_A2_vminh", -1, 0, 0, -1},
+  {"Hexagon_A2_vminub", -1, 0, 0, -1},
+  {"Hexagon_A2_vminuh", -1, 0, 0, -1},
+  {"Hexagon_A2_vminuw", -1, 0, 0, -1},
+  {"Hexagon_A2_vminw", -1, 0, 0, -1},
+  {"Hexagon_A2_vnavgh", -1, 0, 0, -1},
+  {"Hexagon_A2_vnavghcr", -1, 0, 0, -1},
+  {"Hexagon_A2_vnavghr", -1, 0, 0, -1},
+  {"Hexagon_A2_vnavgw", -1, 0, 0, -1},
+  {"Hexagon_A2_vnavgwcr", -1, 0, 0, -1},
+  {"Hexagon_A2_vnavgwr", -1, 0, 0, -1},
+  {"Hexagon_A2_vraddub", -1, 0, 0, -1},
+  {"Hexagon_A2_vraddub_acc", -1, 0, 0, -1},
+  {"Hexagon_A2_vrsadub", -1, 0, 0, -1},
+  {"Hexagon_A2_vrsadub_acc", -1, 0, 0, -1},
+  {"Hexagon_A2_vsubh", -1, 0, 0, -1},
+  {"Hexagon_A2_vsubhs", -1, 0, 0, -1},
+  {"Hexagon_A2_vsubub", -1, 0, 0, -1},
+  {"Hexagon_A2_vsububs", -1, 0, 0, -1},
+  {"Hexagon_A2_vsubuhs", -1, 0, 0, -1},
+  {"Hexagon_A2_vsubw", -1, 0, 0, -1},
+  {"Hexagon_A2_vsubws", -1, 0, 0, -1},
+  {"Hexagon_A2_xor", -1, 0, 0, -1},
+  {"Hexagon_A2_xorp", -1, 0, 0, -1},
+  {"Hexagon_A2_zxtb", -1, 0, 0, -1},
+  {"Hexagon_A2_zxth", -1, 0, 0, -1},
+  {"Hexagon_A4_andn", -1, 0, 0, -1},
+  {"Hexagon_A4_combineir", -1, 0, 0, -1},
+  {"Hexagon_A4_combineri", -1, 0, 0, -1},
+  {"Hexagon_A4_orn", -1, 0, 0, -1},
+  {"Hexagon_A4_rcmpeq", -1, 0, 0, -1},
+  {"Hexagon_A4_rcmpeqi", -1, 0, 0, -1},
+  {"Hexagon_A4_rcmpneq", -1, 0, 0, -1},
+  {"Hexagon_A4_rcmpneqi", -1, 0, 0, -1},
+  {"Hexagon_C2_all8", -1, 0, 0, -1},
+  {"Hexagon_C2_and", -1, 0, 0, -1},
+  {"Hexagon_C2_andn", -1, 0, 0, -1},
+  {"Hexagon_C2_any8", -1, 0, 0, -1},
+  {"Hexagon_C2_cmpeq", -1, 0, 0, -1},
+  {"Hexagon_C2_cmpeqi", -1, 0, 0, -1},
+  {"Hexagon_C2_cmpeqp", -1, 0, 0, -1},
+  {"Hexagon_C2_cmpgei", -1, 0, 0, -1},
+  {"Hexagon_C2_cmpgeui", -1, 0, 0, -1},
+  {"Hexagon_C2_cmpgt", -1, 0, 0, -1},
+  {"Hexagon_C2_cmpgti", -1, 0, 0, -1},
+  {"Hexagon_C2_cmpgtp", -1, 0, 0, -1},
+  {"Hexagon_C2_cmpgtu", -1, 0, 0, -1},
+  {"Hexagon_C2_cmpgtui", -1, 0, 0, -1},
+  {"Hexagon_C2_cmpgtup", -1, 0, 0, -1},
+  {"Hexagon_C2_cmplt", -1, 0, 0, -1},
+  {"Hexagon_C2_cmpltu", -1, 0, 0, -1},
+  {"Hexagon_C2_mask", -1, 0, 0, -1},
+  {"Hexagon_C2_mux", -1, 0, 0, -1},
+  {"Hexagon_C2_muxii", -1, 0, 0, -1},
+  {"Hexagon_C2_muxir", -1, 0, 0, -1},
+  {"Hexagon_C2_muxri", -1, 0, 0, -1},
+  {"Hexagon_C2_not", -1, 0, 0, -1},
+  {"Hexagon_C2_or", -1, 0, 0, -1},
+  {"Hexagon_C2_orn", -1, 0, 0, -1},
+  {"Hexagon_C2_pxfer_map", -1, 0, 0, -1},
+  {"Hexagon_C2_tfrpr", -1, 0, 0, -1},
+  {"Hexagon_C2_tfrrp", -1, 0, 0, -1},
+  {"Hexagon_C2_vitpack", -1, 0, 0, -1},
+  {"Hexagon_C2_vmux", -1, 0, 0, -1},
+  {"Hexagon_C2_xor", -1, 0, 0, -1},
+  {"Hexagon_C4_and_and", -1, 0, 0, -1},
+  {"Hexagon_C4_and_andn", -1, 0, 0, -1},
+  {"Hexagon_C4_and_or", -1, 0, 0, -1},
+  {"Hexagon_C4_and_orn", -1, 0, 0, -1},
+  {"Hexagon_C4_cmplte", -1, 0, 0, -1},
+  {"Hexagon_C4_cmpltei", -1, 0, 0, -1},
+  {"Hexagon_C4_cmplteu", -1, 0, 0, -1},
+  {"Hexagon_C4_cmplteui", -1, 0, 0, -1},
+  {"Hexagon_C4_cmpneq", -1, 0, 0, -1},
+  {"Hexagon_C4_cmpneqi", -1, 0, 0, -1},
+  {"Hexagon_C4_fastcorner9", -1, 0, 0, -1},
+  {"Hexagon_C4_fastcorner9_not", -1, 0, 0, -1},
+  {"Hexagon_C4_or_and", -1, 0, 0, -1},
+  {"Hexagon_C4_or_andn", -1, 0, 0, -1},
+  {"Hexagon_C4_or_or", -1, 0, 0, -1},
+  {"Hexagon_C4_or_orn", -1, 0, 0, -1},
+  {"Hexagon_M2_acci", -1, 0, 0, -1},
+  {"Hexagon_M2_accii", -1, 0, 0, -1},
+  {"Hexagon_M2_cmaci_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_cmacr_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_cmacs_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_cmacs_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_cmacsc_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_cmacsc_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_cmpyi_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_cmpyr_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_cmpyrs_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_cmpyrs_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_cmpyrsc_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_cmpyrsc_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_cmpys_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_cmpys_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_cmpysc_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_cmpysc_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_cnacs_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_cnacs_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_cnacsc_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_cnacsc_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_dpmpyss_acc_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_dpmpyss_nac_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_dpmpyss_rnd_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_dpmpyss_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_dpmpyuu_acc_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_dpmpyuu_nac_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_dpmpyuu_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_hmmpyh_rs1", -1, 0, 0, -1},
+  {"Hexagon_M2_hmmpyl_rs1", -1, 0, 0, -1},
+  {"Hexagon_M2_maci", -1, 0, 0, -1},
+  {"Hexagon_M2_macsin", -1, 0, 0, -1},
+  {"Hexagon_M2_macsip", -1, 0, 0, -1},
+  {"Hexagon_M2_mmachs_rs0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmachs_rs1", -1, 0, 0, -1},
+  {"Hexagon_M2_mmachs_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmachs_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mmacls_rs0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmacls_rs1", -1, 0, 0, -1},
+  {"Hexagon_M2_mmacls_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmacls_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mmacuhs_rs0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmacuhs_rs1", -1, 0, 0, -1},
+  {"Hexagon_M2_mmacuhs_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmacuhs_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mmaculs_rs0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmaculs_rs1", -1, 0, 0, -1},
+  {"Hexagon_M2_mmaculs_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmaculs_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyh_rs0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyh_rs1", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyl_rs0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyl_rs1", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyuh_rs0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyuh_rs1", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyuh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyuh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyul_rs0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyul_rs1", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyul_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mmpyul_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_sat_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_sat_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_sat_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_sat_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_sat_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_sat_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_sat_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_acc_sat_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_sat_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_sat_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_sat_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_sat_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_sat_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_sat_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_sat_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_nac_sat_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_rnd_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_rnd_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_rnd_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_rnd_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_rnd_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_rnd_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_rnd_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_rnd_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_rnd_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_rnd_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_rnd_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_rnd_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_rnd_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_rnd_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_rnd_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_sat_rnd_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpy_up", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_acc_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_acc_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_acc_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_acc_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_acc_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_acc_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_acc_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_acc_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_nac_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_nac_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_nac_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_nac_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_nac_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_nac_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_nac_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_nac_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_rnd_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_rnd_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_rnd_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_rnd_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_rnd_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_rnd_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_rnd_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyd_rnd_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyi", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_acc_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_acc_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_acc_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_acc_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_acc_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_acc_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_acc_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_acc_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_nac_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_nac_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_nac_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_nac_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_nac_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_nac_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_nac_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_nac_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyu_up", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_acc_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_acc_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_acc_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_acc_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_acc_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_acc_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_acc_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_acc_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_nac_hh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_nac_hh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_nac_hl_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_nac_hl_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_nac_lh_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_nac_lh_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_nac_ll_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyud_nac_ll_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_mpyui", -1, 0, 0, -1},
+  {"Hexagon_M2_nacci", -1, 0, 0, -1},
+  {"Hexagon_M2_naccii", -1, 0, 0, -1},
+  {"Hexagon_M2_subacc", -1, 0, 0, -1},
+  {"Hexagon_M2_vabsdiffh", -1, 0, 0, -1},
+  {"Hexagon_M2_vabsdiffw", -1, 0, 0, -1},
+  {"Hexagon_M2_vcmac_s0_sat_i", -1, 0, 0, -1},
+  {"Hexagon_M2_vcmac_s0_sat_r", -1, 0, 0, -1},
+  {"Hexagon_M2_vcmpy_s0_sat_i", -1, 0, 0, -1},
+  {"Hexagon_M2_vcmpy_s0_sat_r", -1, 0, 0, -1},
+  {"Hexagon_M2_vcmpy_s1_sat_i", -1, 0, 0, -1},
+  {"Hexagon_M2_vcmpy_s1_sat_r", -1, 0, 0, -1},
+  {"Hexagon_M2_vdmacs_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_vdmacs_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_vdmpyrs_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_vdmpyrs_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_vdmpys_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_vdmpys_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_vmac2", -1, 0, 0, -1},
+  {"Hexagon_M2_vmac2es", -1, 0, 0, -1},
+  {"Hexagon_M2_vmac2es_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_vmac2es_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_vmac2s_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_vmac2s_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_vmpy2es_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_vmpy2es_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_vmpy2s_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_vmpy2s_s0pack", -1, 0, 0, -1},
+  {"Hexagon_M2_vmpy2s_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_vmpy2s_s1pack", -1, 0, 0, -1},
+  {"Hexagon_M2_vradduh", -1, 0, 0, -1},
+  {"Hexagon_M2_vrcmaci_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_vrcmaci_s0c", -1, 0, 0, -1},
+  {"Hexagon_M2_vrcmacr_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_vrcmacr_s0c", -1, 0, 0, -1},
+  {"Hexagon_M2_vrcmpyi_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_vrcmpyi_s0c", -1, 0, 0, -1},
+  {"Hexagon_M2_vrcmpyr_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_vrcmpyr_s0c", -1, 0, 0, -1},
+  {"Hexagon_M2_vrcmpys_acc_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_vrcmpys_s1", -1, 0, 0, -1},
+  {"Hexagon_M2_vrcmpys_s1rp", -1, 0, 0, -1},
+  {"Hexagon_M2_vrmac_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_vrmpy_s0", -1, 0, 0, -1},
+  {"Hexagon_M2_xor_xacc", -1, 0, 0, -1},
+  {"Hexagon_M4_xor_xacc", -1, 0, 0, -1},
+  {"Hexagon_S2_addasl_rrri", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_i_p", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_i_p_acc", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_i_p_and", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_i_p_nac", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_i_p_or", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_i_p_xacc", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_i_r", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_i_r_acc", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_i_r_and", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_i_r_nac", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_i_r_or", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_i_r_sat", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_i_r_xacc", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_i_vh", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_i_vw", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_r_p", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_r_p_acc", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_r_p_and", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_r_p_nac", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_r_p_or", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_r_r", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_r_r_acc", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_r_r_and", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_r_r_nac", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_r_r_or", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_r_r_sat", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_r_vh", -1, 0, 0, -1},
+  {"Hexagon_S2_asl_r_vw", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_i_p", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_i_p_acc", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_i_p_and", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_i_p_nac", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_i_p_or", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_i_r", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_i_r_acc", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_i_r_and", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_i_r_nac", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_i_r_or", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_i_r_rnd", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_i_r_rnd_goodsyntax", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_i_svw_trun", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_i_vh", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_i_vw", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_r_p", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_r_p_acc", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_r_p_and", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_r_p_nac", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_r_p_or", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_r_r", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_r_r_acc", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_r_r_and", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_r_r_nac", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_r_r_or", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_r_r_sat", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_r_svw_trun", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_r_vh", -1, 0, 0, -1},
+  {"Hexagon_S2_asr_r_vw", -1, 0, 0, -1},
+  {"Hexagon_S2_cl0", -1, 0, 0, -1},
+  {"Hexagon_S2_cl0p", -1, 0, 0, -1},
+  {"Hexagon_S2_cl1", -1, 0, 0, -1},
+  {"Hexagon_S2_cl1p", -1, 0, 0, -1},
+  {"Hexagon_S2_clb", -1, 0, 0, -1},
+  {"Hexagon_S2_clbnorm", -1, 0, 0, -1},
+  {"Hexagon_S2_clbp", -1, 0, 0, -1},
+  {"Hexagon_S2_clrbit_i", -1, 0, 0, -1},
+  {"Hexagon_S2_clrbit_r", -1, 0, 0, -1},
+  {"Hexagon_S2_ct0", -1, 0, 0, -1},
+  {"Hexagon_S2_ct1", -1, 0, 0, -1},
+  {"Hexagon_S2_extractu", -1, 0, 0, -1},
+  {"Hexagon_S2_extractu_rp", -1, 0, 0, -1},
+  {"Hexagon_S2_extractup", -1, 0, 0, -1},
+  {"Hexagon_S2_extractup_rp", -1, 0, 0, -1},
+  {"Hexagon_S2_lsl_r_p", -1, 0, 0, -1},
+  {"Hexagon_S2_lsl_r_p_acc", -1, 0, 0, -1},
+  {"Hexagon_S2_lsl_r_p_and", -1, 0, 0, -1},
+  {"Hexagon_S2_lsl_r_p_nac", -1, 0, 0, -1},
+  {"Hexagon_S2_lsl_r_p_or", -1, 0, 0, -1},
+  {"Hexagon_S2_lsl_r_r", -1, 0, 0, -1},
+  {"Hexagon_S2_lsl_r_r_acc", -1, 0, 0, -1},
+  {"Hexagon_S2_lsl_r_r_and", -1, 0, 0, -1},
+  {"Hexagon_S2_lsl_r_r_nac", -1, 0, 0, -1},
+  {"Hexagon_S2_lsl_r_r_or", -1, 0, 0, -1},
+  {"Hexagon_S2_lsl_r_vh", -1, 0, 0, -1},
+  {"Hexagon_S2_lsl_r_vw", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_i_p", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_i_p_acc", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_i_p_and", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_i_p_nac", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_i_p_or", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_i_p_xacc", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_i_r", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_i_r_acc", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_i_r_and", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_i_r_nac", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_i_r_or", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_i_r_xacc", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_i_vh", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_i_vw", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_r_p", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_r_p_acc", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_r_p_and", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_r_p_nac", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_r_p_or", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_r_r", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_r_r_acc", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_r_r_and", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_r_r_nac", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_r_r_or", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_r_vh", -1, 0, 0, -1},
+  {"Hexagon_S2_lsr_r_vw", -1, 0, 0, -1},
+  {"Hexagon_S2_packhl", -1, 0, 0, -1},
+  {"Hexagon_S2_parityp", -1, 0, 0, -1},
+  {"Hexagon_S2_setbit_i", -1, 0, 0, -1},
+  {"Hexagon_S2_setbit_r", -1, 0, 0, -1},
+  {"Hexagon_S2_shuffeb", -1, 0, 0, -1},
+  {"Hexagon_S2_shuffeh", -1, 0, 0, -1},
+  {"Hexagon_S2_shuffob", -1, 0, 0, -1},
+  {"Hexagon_S2_shuffoh", -1, 0, 0, -1},
+  {"Hexagon_S2_svsathb", -1, 0, 0, -1},
+  {"Hexagon_S2_svsathub", -1, 0, 0, -1},
+  {"Hexagon_S2_togglebit_i", -1, 0, 0, -1},
+  {"Hexagon_S2_togglebit_r", -1, 0, 0, -1},
+  {"Hexagon_S2_tstbit_i", -1, 0, 0, -1},
+  {"Hexagon_S2_tstbit_r", -1, 0, 0, -1},
+  {"Hexagon_S2_valignib", -1, 0, 0, -1},
+  {"Hexagon_S2_valignrb", -1, 0, 0, -1},
+  {"Hexagon_S2_vcrotate", -1, 0, 0, -1},
+  {"Hexagon_S2_vrndpackwh", -1, 0, 0, -1},
+  {"Hexagon_S2_vrndpackwhs", -1, 0, 0, -1},
+  {"Hexagon_S2_vsathb", -1, 0, 0, -1},
+  {"Hexagon_S2_vsathb_nopack", -1, 0, 0, -1},
+  {"Hexagon_S2_vsathub", -1, 0, 0, -1},
+  {"Hexagon_S2_vsathub_nopack", -1, 0, 0, -1},
+  {"Hexagon_S2_vsatwh", -1, 0, 0, -1},
+  {"Hexagon_S2_vsatwh_nopack", -1, 0, 0, -1},
+  {"Hexagon_S2_vsatwuh", -1, 0, 0, -1},
+  {"Hexagon_S2_vsatwuh_nopack", -1, 0, 0, -1},
+  {"Hexagon_S2_vsplatrb", -1, 0, 0, -1},
+  {"Hexagon_S2_vsplatrh", -1, 0, 0, -1},
+  {"Hexagon_S2_vsxtbh", -1, 0, 0, -1},
+  {"Hexagon_S2_vsxthw", -1, 0, 0, -1},
+  {"Hexagon_S2_vtrunehb", -1, 0, 0, -1},
+  {"Hexagon_S2_vtrunewh", -1, 0, 0, -1},
+  {"Hexagon_S2_vtrunohb", -1, 0, 0, -1},
+  {"Hexagon_S2_vtrunowh", -1, 0, 0, -1},
+  {"Hexagon_S2_vzxtbh", -1, 0, 0, -1},
+  {"Hexagon_S2_vzxthw", -1, 0, 0, -1},
+  {"Hexagon_S4_addaddi", -1, 0, 0, -1},
+  {"Hexagon_S4_andnp", -1, 0, 0, -1},
+  {"Hexagon_S4_ornp", -1, 0, 0, -1},
+  {"Hexagon_S4_subaddi", -1, 0, 0, -1},
+  {"IMMEXT", -1, 0, 0, -1},
+  {"JMP", -1, 0, 0, -1},
+  {"JMPR", -1, 0, 0, -1},
+  {"JMPR_cNotPt", -1, 0, 0, -1},
+  {"JMPR_cPt", -1, 0, 0, -1},
+  {"JMPR_cdnNotPnt", -1, 0, 0, -1},
+  {"JMPR_cdnNotPt_V3", -1, 0, 0, -1},
+  {"JMPR_cdnPnt", -1, 0, 0, -1},
+  {"JMPR_cdnPt_V3", -1, 0, 0, -1},
+  {"JMP_EQriNotPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQriNotPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQriNotPntneg_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQriNotPntneg_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQriNotPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQriNotPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQriNotPtneg_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQriNotPtneg_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQriPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQriPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQriPntneg_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQriPntneg_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQriPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQriPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQriPtneg_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQriPtneg_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQrrNotPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQrrNotPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQrrNotPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQrrNotPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQrrPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQrrPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQrrPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_EQrrPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUriNotPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUriNotPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUriNotPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUriNotPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUriPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUriPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUriPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUriPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrNotPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrNotPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrNotPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrNotPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrdnNotPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrdnNotPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrdnNotPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrdnNotPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrdnPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrdnPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrdnPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTUrrdnPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriNotPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriNotPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriNotPntneg_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriNotPntneg_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriNotPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriNotPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriNotPtneg_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriNotPtneg_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriPntneg_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriPntneg_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriPtneg_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTriPtneg_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrNotPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrNotPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrNotPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrNotPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrdnNotPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrdnNotPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrdnNotPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrdnNotPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrdnPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrdnPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrdnPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_GTrrdnPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_TSTBITr0NotPnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_TSTBITr0NotPnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_TSTBITr0NotPt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_TSTBITr0NotPt_nv_V4", -1, 0, 0, -1},
+  {"JMP_TSTBITr0Pnt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_TSTBITr0Pnt_nv_V4", -1, 0, 0, -1},
+  {"JMP_TSTBITr0Pt_ie_nv_V4", -1, 0, 0, -1},
+  {"JMP_TSTBITr0Pt_nv_V4", -1, 0, 0, -1},
+  {"JMP_c", -1, 0, 0, -1},
+  {"JMP_cNot", -1, 0, 0, -1},
+  {"JMP_cdnNotPnt", -1, 0, 0, -1},
+  {"JMP_cdnNotPt", -1, 0, 0, -1},
+  {"JMP_cdnPnt", -1, 0, 0, -1},
+  {"JMP_cdnPt", -1, 0, 0, -1},
+  {"LDb_GP", -1, 0, 0, -1},
+  {"LDb_GP_V4", -1, 0, 0, -1},
+  {"LDb_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"LDb_GP_cPt_V4", -1, 0, 0, -1},
+  {"LDb_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDb_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"LDd_GP", -1, 0, 0, -1},
+  {"LDd_GP_V4", -1, 0, 0, -1},
+  {"LDd_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"LDd_GP_cPt_V4", -1, 0, 0, -1},
+  {"LDd_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDd_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"LDh_GP", -1, 0, 0, -1},
+  {"LDh_GP_V4", -1, 0, 0, -1},
+  {"LDh_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"LDh_GP_cPt_V4", -1, 0, 0, -1},
+  {"LDh_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDh_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"LDrib", 2, -1024, 1023, Hexagon::LDrib_indexed_shl_V4},
+  {"LDrib_GP", -1, 0, 0, -1},
+  {"LDrib_GP_V4", -1, 0, 0, -1},
+  {"LDrib_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"LDrib_GP_cPt_V4", -1, 0, 0, -1},
+  {"LDrib_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDrib_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"LDrib_abs_V4", 1, 0, 0, Hexagon::LDrib_indexed},
+  {"LDrib_abs_cNotPt_V4", 2, 0, 0, Hexagon::LDrib_indexed_cNotPt},
+  {"LDrib_abs_cPt_V4", 2, 0, 0, Hexagon::LDrib_indexed_cPt},
+  {"LDrib_abs_cdnNotPt_V4", 2, 0, 0, Hexagon::LDrib_indexed_cdnNotPt},
+  {"LDrib_abs_cdnPt_V4", 2, 0, 0, Hexagon::LDrib_indexed_cdnPt},
+  {"LDrib_abs_set_V4", 2, 0, 0, -1},
+  {"LDrib_abs_setimm_V4", 2, 0, 63, -1},
+  {"LDrib_cNotPt", 3, -1024, 1023, Hexagon::LDrib_indexed_shl_cNotPt_V4},
+  {"LDrib_cPt", 3, -1024, 1023, Hexagon::LDrib_indexed_shl_cPt_V4},
+  {"LDrib_cdnNotPt", 3, -1024, 1023, Hexagon::LDrib_indexed_shl_cdnNotPt_V4},
+  {"LDrib_cdnPt", 3, -1024, 1023, Hexagon::LDrib_indexed_shl_cdnPt_V4},
+  {"LDrib_imm_abs_V4", 1, 0, 63, Hexagon::LDrib_indexed},
+  {"LDrib_imm_abs_cNotPt_V4", 2, 0, 63, Hexagon::LDrib_indexed_cNotPt},
+  {"LDrib_imm_abs_cPt_V4", 2, 0, 63, Hexagon::LDrib_indexed_cPt},
+  {"LDrib_imm_abs_cdnNotPt_V4", 2, 0, 63, Hexagon::LDrib_indexed_cdnNotPt},
+  {"LDrib_imm_abs_cdnPt_V4", 2, 0, 63, Hexagon::LDrib_indexed_cdnPt},
+  {"LDrib_ind_lo_V4", 3, 0, 0, -1},
+  {"LDrib_indexed", 2, -1024, 1023, Hexagon::LDrib_indexed_shl_V4},
+  {"LDrib_indexed_V4", -1, 0, 0, -1},
+  {"LDrib_indexed_cNotPt", 3, 0, 63, Hexagon::LDrib_indexed_shl_cNotPt_V4},
+  {"LDrib_indexed_cNotPt_V4", -1, 0, 0, -1},
+  {"LDrib_indexed_cPt", 3, 0, 63, Hexagon::LDrib_indexed_shl_cPt_V4},
+  {"LDrib_indexed_cPt_V4", -1, 0, 0, -1},
+  {"LDrib_indexed_cdnNotPt", 3, 0, 63, Hexagon::LDrib_indexed_shl_cdnNotPt_V4},
+  {"LDrib_indexed_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDrib_indexed_cdnPt", 3, 0, 63, Hexagon::LDrib_indexed_shl_cdnPt_V4},
+  {"LDrib_indexed_cdnPt_V4", -1, 0, 0, -1},
+  {"LDrib_indexed_shl_V4", -1, 0, 0, -1},
+  {"LDrib_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
+  {"LDrib_indexed_shl_cPt_V4", -1, 0, 0, -1},
+  {"LDrib_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDrib_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
+  {"LDrid", 2, -8192, 8184, Hexagon::LDrid_indexed_shl_V4},
+  {"LDrid_GP", -1, 0, 0, -1},
+  {"LDrid_GP_V4", -1, 0, 0, -1},
+  {"LDrid_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"LDrid_GP_cPt_V4", -1, 0, 0, -1},
+  {"LDrid_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDrid_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"LDrid_abs_V4", 1, 0, 0, Hexagon::LDrid_indexed},
+  {"LDrid_abs_cNotPt_V4", 2, 0, 0, Hexagon::LDrid_indexed_cNotPt},
+  {"LDrid_abs_cPt_V4", 2, 0, 0, Hexagon::LDrid_indexed_cPt},
+  {"LDrid_abs_cdnNotPt_V4", 2, 0, 0, Hexagon::LDrid_indexed_cdnNotPt},
+  {"LDrid_abs_cdnPt_V4", 2, 0, 0, Hexagon::LDrid_indexed_cdnPt},
+  {"LDrid_abs_set_V4", 2, 0, 0, -1},
+  {"LDrid_abs_setimm_V4", 2, 0, 63, -1},
+  {"LDrid_cNotPt", 3, -8192, 8184, Hexagon::LDrid_indexed_shl_cNotPt_V4},
+  {"LDrid_cPt", 3, -8192, 8184, Hexagon::LDrid_indexed_shl_cPt_V4},
+  {"LDrid_cdnNotPt", 3, -8192, 8184, Hexagon::LDrid_indexed_shl_cdnNotPt_V4},
+  {"LDrid_cdnPt", 3, -8192, 8184, Hexagon::LDrid_indexed_shl_cdnPt_V4},
+  {"LDrid_f", 2, -8192, 8184, Hexagon::LDrid_indexed_shl_V4},
+  {"LDrid_ind_lo_V4", 3, 0, 0, -1},
+  {"LDrid_indexed", 2, -8192, 8184, Hexagon::LDrid_indexed_shl_V4},
+  {"LDrid_indexed_V4", -1, 0, 0, -1},
+  {"LDrid_indexed_cNotPt", 3, 0, 504, Hexagon::LDrid_indexed_shl_cNotPt_V4},
+  {"LDrid_indexed_cNotPt_V4", -1, 0, 0, -1},
+  {"LDrid_indexed_cPt", 3, 0, 504, Hexagon::LDrid_indexed_shl_cPt_V4},
+  {"LDrid_indexed_cPt_V4", -1, 0, 0, -1},
+  {"LDrid_indexed_cdnNotPt", 3, 0, 504, Hexagon::LDrid_indexed_shl_cdnNotPt_V4},
+  {"LDrid_indexed_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDrid_indexed_cdnPt", 3, 0, 504, Hexagon::LDrid_indexed_shl_cdnPt_V4},
+  {"LDrid_indexed_cdnPt_V4", -1, 0, 0, -1},
+  {"LDrid_indexed_f", 2, -8192, 8184, Hexagon::LDrid_indexed_shl_V4},
+  {"LDrid_indexed_shl_V4", -1, 0, 0, -1},
+  {"LDrid_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
+  {"LDrid_indexed_shl_cPt_V4", -1, 0, 0, -1},
+  {"LDrid_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDrid_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
+  {"LDrih", 2, -2048, 2046, Hexagon::LDrih_indexed_shl_V4},
+  {"LDrih_GP", -1, 0, 0, -1},
+  {"LDrih_GP_V4", -1, 0, 0, -1},
+  {"LDrih_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"LDrih_GP_cPt_V4", -1, 0, 0, -1},
+  {"LDrih_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDrih_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"LDrih_abs_V4", 1, 0, 0, Hexagon::LDrih_indexed},
+  {"LDrih_abs_cNotPt_V4", 2, 0, 0, Hexagon::LDrih_indexed_cNotPt},
+  {"LDrih_abs_cPt_V4", 2, 0, 0, Hexagon::LDrih_indexed_cPt},
+  {"LDrih_abs_cdnNotPt_V4", 2, 0, 0, Hexagon::LDrih_indexed_cdnNotPt},
+  {"LDrih_abs_cdnPt_V4", 2, 0, 0, Hexagon::LDrih_indexed_cdnPt},
+  {"LDrih_abs_set_V4", 2, 0, 0, -1},
+  {"LDrih_abs_setimm_V4", 2, 0, 63, -1},
+  {"LDrih_cNotPt", 3, -2048, 2046, Hexagon::LDrih_indexed_shl_cNotPt_V4},
+  {"LDrih_cPt", 3, -2048, 2046, Hexagon::LDrih_indexed_shl_cPt_V4},
+  {"LDrih_cdnNotPt", 3, -2048, 2046, Hexagon::LDrih_indexed_shl_cdnNotPt_V4},
+  {"LDrih_cdnPt", 3, -2048, 2046, Hexagon::LDrih_indexed_shl_cdnPt_V4},
+  {"LDrih_imm_abs_V4", 1, 0, 63, Hexagon::LDrih_indexed},
+  {"LDrih_imm_abs_cNotPt_V4", 2, 0, 63, Hexagon::LDrih_indexed_cNotPt},
+  {"LDrih_imm_abs_cPt_V4", 2, 0, 63, Hexagon::LDrih_indexed_cPt},
+  {"LDrih_imm_abs_cdnNotPt_V4", 2, 0, 63, Hexagon::LDrih_indexed_cdnNotPt},
+  {"LDrih_imm_abs_cdnPt_V4", 2, 0, 63, Hexagon::LDrih_indexed_cdnPt},
+  {"LDrih_ind_lo_V4", 3, 0, 0, -1},
+  {"LDrih_indexed", 2, -2048, 2046, Hexagon::LDrih_indexed_shl_V4},
+  {"LDrih_indexed_V4", -1, 0, 0, -1},
+  {"LDrih_indexed_cNotPt", 3, 0, 126, Hexagon::LDrih_indexed_shl_cNotPt_V4},
+  {"LDrih_indexed_cNotPt_V4", -1, 0, 0, -1},
+  {"LDrih_indexed_cPt", 3, 0, 126, Hexagon::LDrih_indexed_shl_cPt_V4},
+  {"LDrih_indexed_cPt_V4", -1, 0, 0, -1},
+  {"LDrih_indexed_cdnNotPt", 3, 0, 126, Hexagon::LDrih_indexed_shl_cdnNotPt_V4},
+  {"LDrih_indexed_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDrih_indexed_cdnPt", 3, 0, 126, Hexagon::LDrih_indexed_shl_cdnPt_V4},
+  {"LDrih_indexed_cdnPt_V4", -1, 0, 0, -1},
+  {"LDrih_indexed_shl_V4", -1, 0, 0, -1},
+  {"LDrih_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
+  {"LDrih_indexed_shl_cPt_V4", -1, 0, 0, -1},
+  {"LDrih_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDrih_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
+  {"LDriub", 2, -1024, 1023, Hexagon::LDriub_ae_indexed_shl_V4},
+  {"LDriub_GP", -1, 0, 0, -1},
+  {"LDriub_GP_V4", -1, 0, 0, -1},
+  {"LDriub_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"LDriub_GP_cPt_V4", -1, 0, 0, -1},
+  {"LDriub_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDriub_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"LDriub_abs_V4", 1, 0, 0, Hexagon::LDriub_indexed},
+  {"LDriub_abs_cNotPt_V4", 2, 0, 0, Hexagon::LDriub_indexed_cNotPt},
+  {"LDriub_abs_cPt_V4", 2, 0, 0, Hexagon::LDriub_indexed_cPt},
+  {"LDriub_abs_cdnNotPt_V4", 2, 0, 0, Hexagon::LDriub_indexed_cdnNotPt},
+  {"LDriub_abs_cdnPt_V4", 2, 0, 0, Hexagon::LDriub_indexed_cdnPt},
+  {"LDriub_abs_set_V4", 2, 0, 0, -1},
+  {"LDriub_abs_setimm_V4", 2, 0, 63, -1},
+  {"LDriub_ae_indexed_V4", -1, 0, 0, -1},
+  {"LDriub_ae_indexed_shl_V4", -1, 0, 0, -1},
+  {"LDriub_cNotPt", 3, -1024, 1023, Hexagon::LDriub_indexed_shl_cNotPt_V4},
+  {"LDriub_cPt", 3, -1024, 1023, Hexagon::LDriub_indexed_shl_cPt_V4},
+  {"LDriub_cdnNotPt", 3, -1024, 1023, Hexagon::LDriub_indexed_shl_cdnNotPt_V4},
+  {"LDriub_cdnPt", 3, -1024, 1023, Hexagon::LDriub_indexed_shl_cdnPt_V4},
+  {"LDriub_imm_abs_V4", 1, 0, 63, Hexagon::LDriub_indexed},
+  {"LDriub_imm_abs_cNotPt_V4", 2, 0, 63, Hexagon::LDriub_indexed_cNotPt},
+  {"LDriub_imm_abs_cPt_V4", 2, 0, 63, Hexagon::LDriub_indexed_cPt},
+  {"LDriub_imm_abs_cdnNotPt_V4", 2, 0, 63, Hexagon::LDriub_indexed_cdnNotPt},
+  {"LDriub_imm_abs_cdnPt_V4", 2, 0, 63, Hexagon::LDriub_indexed_cdnPt},
+  {"LDriub_ind_lo_V4", 3, 0, 0, -1},
+  {"LDriub_indexed", 2, -1024, 1023, Hexagon::LDriub_ae_indexed_shl_V4},
+  {"LDriub_indexed_V4", -1, 0, 0, -1},
+  {"LDriub_indexed_cNotPt", 3, 0, 63, Hexagon::LDriub_indexed_shl_cNotPt_V4},
+  {"LDriub_indexed_cNotPt_V4", -1, 0, 0, -1},
+  {"LDriub_indexed_cPt", 3, 0, 63, Hexagon::LDriub_indexed_shl_cPt_V4},
+  {"LDriub_indexed_cPt_V4", -1, 0, 0, -1},
+  {"LDriub_indexed_cdnNotPt", 3, 0, 63,
+                                       Hexagon::LDriub_indexed_shl_cdnNotPt_V4},
+  {"LDriub_indexed_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDriub_indexed_cdnPt", 3, 0, 63, Hexagon::LDriub_indexed_shl_cdnPt_V4},
+  {"LDriub_indexed_cdnPt_V4", -1, 0, 0, -1},
+  {"LDriub_indexed_shl_V4", -1, 0, 0, -1},
+  {"LDriub_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
+  {"LDriub_indexed_shl_cPt_V4", -1, 0, 0, -1},
+  {"LDriub_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDriub_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
+  {"LDriuh", 2, -2048, 2046, Hexagon::LDriuh_ae_indexed_shl_V4},
+  {"LDriuh_GP", -1, 0, 0, -1},
+  {"LDriuh_GP_V4", -1, 0, 0, -1},
+  {"LDriuh_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"LDriuh_GP_cPt_V4", -1, 0, 0, -1},
+  {"LDriuh_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDriuh_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"LDriuh_abs_V4", 1, 0, 0, Hexagon::LDriuh_indexed},
+  {"LDriuh_abs_cNotPt_V4", 2, 0, 0, Hexagon::LDriuh_indexed_cNotPt},
+  {"LDriuh_abs_cPt_V4", 2, 0, 0, Hexagon::LDriuh_indexed_cPt},
+  {"LDriuh_abs_cdnNotPt_V4", 2, 0, 0, Hexagon::LDriuh_indexed_cdnNotPt},
+  {"LDriuh_abs_cdnPt_V4", 2, 0, 0, Hexagon::LDriuh_indexed_cdnPt},
+  {"LDriuh_abs_set_V4", 2, 0, 0, -1},
+  {"LDriuh_abs_setimm_V4", 2, 0, 63, -1},
+  {"LDriuh_ae_indexed_V4", -1, 0, 0, -1},
+  {"LDriuh_ae_indexed_shl_V4", -1, 0, 0, -1},
+  {"LDriuh_cNotPt", 3, -2048, 2046, Hexagon::LDriuh_indexed_shl_cNotPt_V4},
+  {"LDriuh_cPt", 3, -2048, 2046, Hexagon::LDriuh_indexed_shl_cPt_V4},
+  {"LDriuh_cdnNotPt", 3, -2048, 2046, Hexagon::LDriuh_indexed_shl_cdnNotPt_V4},
+  {"LDriuh_cdnPt", 3, -2048, 2046, Hexagon::LDriuh_indexed_shl_cdnPt_V4},
+  {"LDriuh_imm_abs_V4", 1, 0, 63, Hexagon::LDriuh_indexed},
+  {"LDriuh_imm_abs_cNotPt_V4", 2, 0, 63, Hexagon::LDriuh_indexed_cNotPt},
+  {"LDriuh_imm_abs_cPt_V4", 2, 0, 63, Hexagon::LDriuh_indexed_cPt},
+  {"LDriuh_imm_abs_cdnNotPt_V4", 2, 0, 63, Hexagon::LDriuh_indexed_cdnNotPt},
+  {"LDriuh_imm_abs_cdnPt_V4", 2, 0, 63, Hexagon::LDriuh_indexed_cdnPt},
+  {"LDriuh_ind_lo_V4", 3, 0, 0, -1},
+  {"LDriuh_indexed", 2, -2048, 2046, Hexagon::LDriuh_ae_indexed_shl_V4},
+  {"LDriuh_indexed_V4", -1, 0, 0, -1},
+  {"LDriuh_indexed_cNotPt", 3, 0, 126, Hexagon::LDriuh_indexed_shl_cNotPt_V4},
+  {"LDriuh_indexed_cNotPt_V4", -1, 0, 0, -1},
+  {"LDriuh_indexed_cPt", 3, 0, 126, Hexagon::LDriuh_indexed_shl_cPt_V4},
+  {"LDriuh_indexed_cPt_V4", -1, 0, 0, -1},
+  {"LDriuh_indexed_cdnNotPt", 3, 0, 126,
+                                       Hexagon::LDriuh_indexed_shl_cdnNotPt_V4},
+  {"LDriuh_indexed_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDriuh_indexed_cdnPt", 3, 0, 126, Hexagon::LDriuh_indexed_shl_cdnPt_V4},
+  {"LDriuh_indexed_cdnPt_V4", -1, 0, 0, -1},
+  {"LDriuh_indexed_shl_V4", -1, 0, 0, -1},
+  {"LDriuh_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
+  {"LDriuh_indexed_shl_cPt_V4", -1, 0, 0, -1},
+  {"LDriuh_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDriuh_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
+  {"LDriw", 2, -4096, 4092, Hexagon::LDriw_indexed_shl_V4},
+  {"LDriw_GP", -1, 0, 0, -1},
+  {"LDriw_GP_V4", -1, 0, 0, -1},
+  {"LDriw_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"LDriw_GP_cPt_V4", -1, 0, 0, -1},
+  {"LDriw_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDriw_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"LDriw_abs_V4", 1, 0, 0, Hexagon::LDriw_indexed},
+  {"LDriw_abs_cNotPt_V4", 2, 0, 0, Hexagon::LDriw_indexed_cNotPt},
+  {"LDriw_abs_cPt_V4", 2, 0, 0, Hexagon::LDriw_indexed_cPt},
+  {"LDriw_abs_cdnNotPt_V4", 2, 0, 0, Hexagon::LDriw_indexed_cdnNotPt},
+  {"LDriw_abs_cdnPt_V4", 2, 0, 0, Hexagon::LDriw_indexed_cdnPt},
+  {"LDriw_abs_set_V4", 2, 0, 0, -1},
+  {"LDriw_abs_setimm_V4", 2, 0, 63, -1},
+  {"LDriw_cNotPt", 3, -4096, 4092, Hexagon::LDriw_indexed_shl_cNotPt_V4},
+  {"LDriw_cPt", 3, -4096, 4092, Hexagon::LDriw_indexed_shl_cPt_V4},
+  {"LDriw_cdnNotPt", 3, -4096, 4092, Hexagon::LDriw_indexed_shl_cdnNotPt_V4},
+  {"LDriw_cdnPt", 3, -4096, 4092, Hexagon::LDriw_indexed_shl_cdnPt_V4},
+  {"LDriw_f", 2, -4096, 4092, Hexagon::LDriw_indexed_shl_V4},
+  {"LDriw_imm_abs_V4", 1, 0, 63, Hexagon::LDriw_indexed},
+  {"LDriw_imm_abs_cNotPt_V4", 2, 0, 63, Hexagon::LDriw_indexed_cNotPt},
+  {"LDriw_imm_abs_cPt_V4", 2, 0, 63, Hexagon::LDriw_indexed_cPt},
+  {"LDriw_imm_abs_cdnNotPt_V4", 2, 0, 63, Hexagon::LDriw_indexed_cdnNotPt},
+  {"LDriw_imm_abs_cdnPt_V4", 2, 0, 63, Hexagon::LDriw_indexed_cdnPt},
+  {"LDriw_ind_lo_V4", 3, 0, 0, -1},
+  {"LDriw_indexed", 2, -4096, 4092, Hexagon::LDriw_indexed_shl_V4},
+  {"LDriw_indexed_V4", -1, 0, 0, -1},
+  {"LDriw_indexed_cNotPt", 3, 0, 252, Hexagon::LDriw_indexed_shl_cNotPt_V4},
+  {"LDriw_indexed_cNotPt_V4", -1, 0, 0, -1},
+  {"LDriw_indexed_cPt", 3, 0, 252, Hexagon::LDriw_indexed_shl_cPt_V4},
+  {"LDriw_indexed_cPt_V4", -1, 0, 0, -1},
+  {"LDriw_indexed_cdnNotPt", 3, 0, 252, Hexagon::LDriw_indexed_shl_cdnNotPt_V4},
+  {"LDriw_indexed_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDriw_indexed_cdnPt", 3, 0, 252, Hexagon::LDriw_indexed_shl_cdnPt_V4},
+  {"LDriw_indexed_cdnPt_V4", -1, 0, 0, -1},
+  {"LDriw_indexed_f", 2, -4096, 4092, Hexagon::LDriw_indexed_shl_V4},
+  {"LDriw_indexed_shl_V4", -1, 0, 0, -1},
+  {"LDriw_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
+  {"LDriw_indexed_shl_cPt_V4", -1, 0, 0, -1},
+  {"LDriw_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDriw_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
+  {"LDriw_pred", 2, -4096, 4092, -1},
+  {"LDriw_pred_V4", 2, -4096, 4092, -1},
+  {"LDub_GP", -1, 0, 0, -1},
+  {"LDub_GP_V4", -1, 0, 0, -1},
+  {"LDub_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"LDub_GP_cPt_V4", -1, 0, 0, -1},
+  {"LDub_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDub_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"LDuh_GP", -1, 0, 0, -1},
+  {"LDuh_GP_V4", -1, 0, 0, -1},
+  {"LDuh_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"LDuh_GP_cPt_V4", -1, 0, 0, -1},
+  {"LDuh_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDuh_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"LDw_GP", -1, 0, 0, -1},
+  {"LDw_GP_V4", -1, 0, 0, -1},
+  {"LDw_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"LDw_GP_cPt_V4", -1, 0, 0, -1},
+  {"LDw_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"LDw_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"LO", -1, 0, 0, -1},
+  {"LOOP0_i", -1, 0, 0, -1},
+  {"LOOP0_iext", 0, 0, 0, -1},
+  {"LOOP0_r", -1, 0, 0, -1},
+  {"LOOP0_rext", 0, 0, 0, -1},
+  {"LO_jt", -1, 0, 0, -1},
+  {"LO_label", -1, 0, 0, -1},
+  {"LOi", -1, 0, 0, -1},
+  {"LSL_ADD_rr", -1, 0, 0, -1},
+  {"LSL_ADDd_rr", -1, 0, 0, -1},
+  {"LSL_AND_rr", -1, 0, 0, -1},
+  {"LSL_ANDd_rr", -1, 0, 0, -1},
+  {"LSL_OR_rr", -1, 0, 0, -1},
+  {"LSL_ORd_rr", -1, 0, 0, -1},
+  {"LSL_SUB_rr", -1, 0, 0, -1},
+  {"LSL_SUBd_rr", -1, 0, 0, -1},
+  {"LSL_rr", -1, 0, 0, -1},
+  {"LSLd", -1, 0, 0, -1},
+  {"LSLd_rr_xor_V4", -1, 0, 0, -1},
+  {"LSLi_V4", -1, 0, 0, -1},
+  {"LSR_ADD_ri", -1, 0, 0, -1},
+  {"LSR_ADD_rr", -1, 0, 0, -1},
+  {"LSR_ADDd_ri", -1, 0, 0, -1},
+  {"LSR_ADDd_rr", -1, 0, 0, -1},
+  {"LSR_AND_ri", -1, 0, 0, -1},
+  {"LSR_AND_rr", -1, 0, 0, -1},
+  {"LSR_ANDd_ri", -1, 0, 0, -1},
+  {"LSR_ANDd_rr", -1, 0, 0, -1},
+  {"LSR_OR_ri", -1, 0, 0, -1},
+  {"LSR_OR_rr", -1, 0, 0, -1},
+  {"LSR_ORd_ri", -1, 0, 0, -1},
+  {"LSR_ORd_rr", -1, 0, 0, -1},
+  {"LSR_SUB_ri", -1, 0, 0, -1},
+  {"LSR_SUB_rr", -1, 0, 0, -1},
+  {"LSR_SUBd_ri", -1, 0, 0, -1},
+  {"LSR_SUBd_rr", -1, 0, 0, -1},
+  {"LSR_XOR_ri", -1, 0, 0, -1},
+  {"LSR_XORd_ri", -1, 0, 0, -1},
+  {"LSR_ri", -1, 0, 0, -1},
+  {"LSR_rr", -1, 0, 0, -1},
+  {"LSRd_ri", -1, 0, 0, -1},
+  {"LSRd_rr", -1, 0, 0, -1},
+  {"LSRd_rr_xor_V4", -1, 0, 0, -1},
+  {"MASK_p", -1, 0, 0, -1},
+  {"MAXUd_rr", -1, 0, 0, -1},
+  {"MAXUw_rr", -1, 0, 0, -1},
+  {"MAXd_rr", -1, 0, 0, -1},
+  {"MAXw_dd", -1, 0, 0, -1},
+  {"MAXw_rr", -1, 0, 0, -1},
+  {"MEMb_ADDSUBi_MEM_V4", -1, 0, 0, -1},
+  {"MEMb_ADDSUBi_indexed_MEM_V4", -1, 0, 0, -1},
+  {"MEMb_ADDi_MEM_V4", -1, 0, 0, -1},
+  {"MEMb_ADDi_indexed_MEM_V4", -1, 0, 0, -1},
+  {"MEMb_ADDr_MEM_V4", -1, 0, 0, -1},
+  {"MEMb_ADDr_indexed_MEM_V4", -1, 0, 0, -1},
+  {"MEMb_ANDr_MEM_V4", -1, 0, 0, -1},
+  {"MEMb_ANDr_indexed_MEM_V4", -1, 0, 0, -1},
+  {"MEMb_ORr_MEM_V4", -1, 0, 0, -1},
+  {"MEMb_ORr_indexed_MEM_V4", -1, 0, 0, -1},
+  {"MEMb_SUBi_MEM_V4", -1, 0, 0, -1},
+  {"MEMb_SUBi_indexed_MEM_V4", -1, 0, 0, -1},
+  {"MEMb_SUBr_MEM_V4", -1, 0, 0, -1},
+  {"MEMb_SUBr_indexed_MEM_V4", -1, 0, 0, -1},
+  {"MEMh_ADDSUBi_MEM_V4", -1, 0, 0, -1},
+  {"MEMh_ADDSUBi_indexed_MEM_V4", -1, 0, 0, -1},
+  {"MEMh_ADDi_MEM_V4", -1, 0, 0, -1},
+  {"MEMh_ADDi_indexed_MEM_V4", -1, 0, 0, -1},
+  {"MEMh_ADDr_MEM_V4", -1, 0, 0, -1},
+  {"MEMh_ADDr_indexed_MEM_V4", -1, 0, 0, -1},
+  {"MEMh_ANDr_MEM_V4", -1, 0, 0, -1},
+  {"MEMh_ANDr_indexed_MEM_V4", -1, 0, 0, -1},
+  {"MEMh_ORr_MEM_V4", -1, 0, 0, -1},
+  {"MEMh_ORr_indexed_MEM_V4", -1, 0, 0, -1},
+  {"MEMh_SUBi_MEM_V4", -1, 0, 0, -1},
+  {"MEMh_SUBi_indexed_MEM_V4", -1, 0, 0, -1},
+  {"MEMh_SUBr_MEM_V4", -1, 0, 0, -1},
+  {"MEMh_SUBr_indexed_MEM_V4", -1, 0, 0, -1},
+  {"MEMw_ADDSUBi_MEM_V4", -1, 0, 0, -1},
+  {"MEMw_ADDSUBi_indexed_MEM_V4", -1, 0, 0, -1},
+  {"MEMw_ADDi_MEM_V4", -1, 0, 0, -1},
+  {"MEMw_ADDi_indexed_MEM_V4", 1, 0, 252, -1},
+  {"MEMw_ADDr_MEM_V4", -1, 0, 0, -1},
+  {"MEMw_ADDr_indexed_MEM_V4", 1, 0, 252, -1},
+  {"MEMw_ANDr_MEM_V4", -1, 0, 0, -1},
+  {"MEMw_ANDr_indexed_MEM_V4", 1, 0, 252, -1},
+  {"MEMw_ORr_MEM_V4", -1, 0, 0, -1},
+  {"MEMw_ORr_indexed_MEM_V4", 1, 0, 252, -1},
+  {"MEMw_SUBi_MEM_V4", -1, 0, 0, -1},
+  {"MEMw_SUBi_indexed_MEM_V4", 1, 0, 252, -1},
+  {"MEMw_SUBr_MEM_V4", -1, 0, 0, -1},
+  {"MEMw_SUBr_indexed_MEM_V4", 1, 0, 252, -1},
+  {"MINUd_rr", -1, 0, 0, -1},
+  {"MINUw_rr", -1, 0, 0, -1},
+  {"MINd_rr", -1, 0, 0, -1},
+  {"MINw_dd", -1, 0, 0, -1},
+  {"MINw_rr", -1, 0, 0, -1},
+  {"MPY", -1, 0, 0, -1},
+  {"MPY64", -1, 0, 0, -1},
+  {"MPY64_acc", -1, 0, 0, -1},
+  {"MPY64_sub", -1, 0, 0, -1},
+  {"MPYI", -1, 0, 0, -1},
+  {"MPYI_acc_ri", 3, 0, 255, Hexagon::MPYI_acc_rr},
+  {"MPYI_acc_rr", -1, 0, 0, -1},
+  {"MPYI_ri", 2, -256, 255, Hexagon::MPYI},
+  {"MPYI_rin", -1, 0, 0, -1},
+  {"MPYI_riu", 2, 0, 255, -1},
+  {"MPYI_sub_ri", 3, 0, 255, -1},
+  {"MPYU", -1, 0, 0, -1},
+  {"MPYU64", -1, 0, 0, -1},
+  {"MPYU64_acc", -1, 0, 0, -1},
+  {"MPYU64_sub", -1, 0, 0, -1},
+  {"MPY_trsext", -1, 0, 0, -1},
+  {"MUX_ii", 2, -128, 127, -1},
+  {"MUX_ir", 2, -128, 127, Hexagon::MUX_rr},
+  {"MUX_ri", 3, -128, 127, Hexagon::MUX_rr},
+  {"MUX_rr", -1, 0, 0, -1},
+  {"NEG", -1, 0, 0, -1},
+  {"NOP", -1, 0, 0, -1},
+  {"NOT_p", -1, 0, 0, -1},
+  {"NOT_rr", -1, 0, 0, -1},
+  {"NOT_rr64", -1, 0, 0, -1},
+  {"OR_pp", -1, 0, 0, -1},
+  {"OR_ri", 2, -512, 511, Hexagon::OR_rr},
+  {"OR_rr", -1, 0, 0, -1},
+  {"OR_rr64", -1, 0, 0, -1},
+  {"OR_rr_cNotPt", -1, 0, 0, -1},
+  {"OR_rr_cPt", -1, 0, 0, -1},
+  {"OR_rr_cdnNotPt", -1, 0, 0, -1},
+  {"OR_rr_cdnPt", -1, 0, 0, -1},
+  {"ORd_NOTd_V4", -1, 0, 0, -1},
+  {"ORi_ASLri_V4", 1, 0, 255, -1},
+  {"ORi_LSRri_V4", 1, 0, 255, -1},
+  {"ORr_ANDr_NOTr_V4", -1, 0, 0, -1},
+  {"ORr_ANDri2_V4", 3, -512, 511, Hexagon::ORr_ANDrr_V4},
+  {"ORr_ANDri_V4", 3, -512, 511, -1},
+  {"ORr_ANDrr_V4", -1, 0, 0, -1},
+  {"ORr_ORri_V4", 3, -512, 511, Hexagon::ORr_ORrr_V4},
+  {"ORr_ORrr_V4", -1, 0, 0, -1},
+  {"ORr_XORrr_V4", -1, 0, 0, -1},
+  {"POST_LDrib", -1, 0, 0, -1},
+  {"POST_LDrib_cNotPt", -1, 0, 0, -1},
+  {"POST_LDrib_cPt", -1, 0, 0, -1},
+  {"POST_LDrib_cdnNotPt_V4", -1, 0, 0, -1},
+  {"POST_LDrib_cdnPt_V4", -1, 0, 0, -1},
+  {"POST_LDrid", -1, 0, 0, -1},
+  {"POST_LDrid_cNotPt", -1, 0, 0, -1},
+  {"POST_LDrid_cPt", -1, 0, 0, -1},
+  {"POST_LDrid_cdnNotPt_V4", -1, 0, 0, -1},
+  {"POST_LDrid_cdnPt_V4", -1, 0, 0, -1},
+  {"POST_LDrih", -1, 0, 0, -1},
+  {"POST_LDrih_cNotPt", -1, 0, 0, -1},
+  {"POST_LDrih_cPt", -1, 0, 0, -1},
+  {"POST_LDrih_cdnNotPt_V4", -1, 0, 0, -1},
+  {"POST_LDrih_cdnPt_V4", -1, 0, 0, -1},
+  {"POST_LDriub", -1, 0, 0, -1},
+  {"POST_LDriub_cNotPt", -1, 0, 0, -1},
+  {"POST_LDriub_cPt", -1, 0, 0, -1},
+  {"POST_LDriub_cdnNotPt_V4", -1, 0, 0, -1},
+  {"POST_LDriub_cdnPt_V4", -1, 0, 0, -1},
+  {"POST_LDriuh", -1, 0, 0, -1},
+  {"POST_LDriuh_cNotPt", -1, 0, 0, -1},
+  {"POST_LDriuh_cPt", -1, 0, 0, -1},
+  {"POST_LDriuh_cdnNotPt_V4", -1, 0, 0, -1},
+  {"POST_LDriuh_cdnPt_V4", -1, 0, 0, -1},
+  {"POST_LDriw", -1, 0, 0, -1},
+  {"POST_LDriw_cNotPt", -1, 0, 0, -1},
+  {"POST_LDriw_cPt", -1, 0, 0, -1},
+  {"POST_LDriw_cdnNotPt_V4", -1, 0, 0, -1},
+  {"POST_LDriw_cdnPt_V4", -1, 0, 0, -1},
+  {"POST_STbri", -1, 0, 0, -1},
+  {"POST_STbri_cNotPt", -1, 0, 0, -1},
+  {"POST_STbri_cNotPt_nv_V4", -1, 0, 0, -1},
+  {"POST_STbri_cPt", -1, 0, 0, -1},
+  {"POST_STbri_cPt_nv_V4", -1, 0, 0, -1},
+  {"POST_STbri_cdnNotPt_V4", -1, 0, 0, -1},
+  {"POST_STbri_cdnNotPt_nv_V4", -1, 0, 0, -1},
+  {"POST_STbri_cdnPt_V4", -1, 0, 0, -1},
+  {"POST_STbri_cdnPt_nv_V4", -1, 0, 0, -1},
+  {"POST_STbri_nv_V4", -1, 0, 0, -1},
+  {"POST_STdri", -1, 0, 0, -1},
+  {"POST_STdri_cNotPt", -1, 0, 0, -1},
+  {"POST_STdri_cPt", -1, 0, 0, -1},
+  {"POST_STdri_cdnNotPt_V4", -1, 0, 0, -1},
+  {"POST_STdri_cdnPt_V4", -1, 0, 0, -1},
+  {"POST_SThri", -1, 0, 0, -1},
+  {"POST_SThri_cNotPt", -1, 0, 0, -1},
+  {"POST_SThri_cNotPt_nv_V4", -1, 0, 0, -1},
+  {"POST_SThri_cPt", -1, 0, 0, -1},
+  {"POST_SThri_cPt_nv_V4", -1, 0, 0, -1},
+  {"POST_SThri_cdnNotPt_V4", -1, 0, 0, -1},
+  {"POST_SThri_cdnNotPt_nv_V4", -1, 0, 0, -1},
+  {"POST_SThri_cdnPt_V4", -1, 0, 0, -1},
+  {"POST_SThri_cdnPt_nv_V4", -1, 0, 0, -1},
+  {"POST_SThri_nv_V4", -1, 0, 0, -1},
+  {"POST_STwri", -1, 0, 0, -1},
+  {"POST_STwri_cNotPt", -1, 0, 0, -1},
+  {"POST_STwri_cNotPt_nv_V4", -1, 0, 0, -1},
+  {"POST_STwri_cPt", -1, 0, 0, -1},
+  {"POST_STwri_cPt_nv_V4", -1, 0, 0, -1},
+  {"POST_STwri_cdnNotPt_V4", -1, 0, 0, -1},
+  {"POST_STwri_cdnNotPt_nv_V4", -1, 0, 0, -1},
+  {"POST_STwri_cdnPt_V4", -1, 0, 0, -1},
+  {"POST_STwri_cdnPt_nv_V4", -1, 0, 0, -1},
+  {"POST_STwri_nv_V4", -1, 0, 0, -1},
+  {"RESTORE_DEALLOC_BEFORE_TAILCALL_V4", -1, 0, 0, -1},
+  {"RESTORE_DEALLOC_RET_JMP_V4", -1, 0, 0, -1},
+  {"SAVE_REGISTERS_CALL_V4", -1, 0, 0, -1},
+  {"SETBIT", -1, 0, 0, -1},
+  {"SETBIT_31", -1, 0, 0, -1},
+  {"SI_to_SXTHI_asrh", -1, 0, 0, -1},
+  {"STb_GP", -1, 0, 0, -1},
+  {"STb_GP_V4", -1, 0, 0, -1},
+  {"STb_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"STb_GP_cNotPt_nv_V4", -1, 0, 0, -1},
+  {"STb_GP_cPt_V4", -1, 0, 0, -1},
+  {"STb_GP_cPt_nv_V4", -1, 0, 0, -1},
+  {"STb_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"STb_GP_cdnNotPt_nv_V4", -1, 0, 0, -1},
+  {"STb_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"STb_GP_cdnPt_nv_V4", -1, 0, 0, -1},
+  {"STb_GP_nv_V4", -1, 0, 0, -1},
+  {"STd_GP", -1, 0, 0, -1},
+  {"STd_GP_V4", -1, 0, 0, -1},
+  {"STd_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"STd_GP_cPt_V4", -1, 0, 0, -1},
+  {"STd_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"STd_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"STh_GP", -1, 0, 0, -1},
+  {"STh_GP_V4", -1, 0, 0, -1},
+  {"STh_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"STh_GP_cNotPt_nv_V4", -1, 0, 0, -1},
+  {"STh_GP_cPt_V4", -1, 0, 0, -1},
+  {"STh_GP_cPt_nv_V4", -1, 0, 0, -1},
+  {"STh_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"STh_GP_cdnNotPt_nv_V4", -1, 0, 0, -1},
+  {"STh_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"STh_GP_cdnPt_nv_V4", -1, 0, 0, -1},
+  {"STh_GP_nv_V4", -1, 0, 0, -1},
+  {"STrib", 1, -1024, 1023, Hexagon::STrib_indexed_shl_V4},
+  {"STrib_GP", -1, 0, 0, -1},
+  {"STrib_GP_V4", -1, 0, 0, -1},
+  {"STrib_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"STrib_GP_cNotPt_nv_V4", -1, 0, 0, -1},
+  {"STrib_GP_cPt_V4", -1, 0, 0, -1},
+  {"STrib_GP_cPt_nv_V4", -1, 0, 0, -1},
+  {"STrib_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"STrib_GP_cdnNotPt_nv_V4", -1, 0, 0, -1},
+  {"STrib_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"STrib_GP_cdnPt_nv_V4", -1, 0, 0, -1},
+  {"STrib_GP_nv_V4", -1, 0, 0, -1},
+  {"STrib_abs_V4", 0, 0, 0, Hexagon::STrib_indexed},
+  {"STrib_abs_cNotPt_V4", 1, 0, 0, Hexagon::STrib_indexed_cNotPt},
+  {"STrib_abs_cNotPt_nv_V4", 1, 0, 0, Hexagon::STrib_indexed_cNotPt_nv_V4},
+  {"STrib_abs_cPt_V4", 1, 0, 0, Hexagon::STrib_indexed_cPt},
+  {"STrib_abs_cPt_nv_V4", 1, 0, 0, Hexagon::STrib_indexed_cPt_nv_V4},
+  {"STrib_abs_cdnNotPt_V4", 1, 0, 0, Hexagon::STrib_indexed_cdnNotPt_V4},
+  {"STrib_abs_cdnNotPt_nv_V4", 1, 0, 0, Hexagon::STrib_indexed_cdnNotPt_nv_V4},
+  {"STrib_abs_cdnPt_V4", 1, 0, 0, Hexagon::STrib_indexed_cdnPt_V4},
+  {"STrib_abs_cdnPt_nv_V4", 1, 0, 0, Hexagon::STrib_indexed_cdnPt_nv_V4},
+  {"STrib_abs_nv_V4", 0, 0, 0, Hexagon::STrib_indexed_nv_V4},
+  {"STrib_abs_set_V4", 2, 0, 0, -1},
+  {"STrib_abs_setimm_V4", 2, 0, 63, -1},
+  {"STrib_cNotPt", 2, -1024, 1023, Hexagon::STrib_indexed_shl_cNotPt_V4},
+  {"STrib_cNotPt_nv_V4", 2, -1024, 1023,
+                                       Hexagon::STrib_indexed_shl_cNotPt_nv_V4},
+  {"STrib_cPt", 2, -1024, 1023, Hexagon::STrib_indexed_shl_cPt_V4},
+  {"STrib_cPt_nv_V4", 2, -1024, 1023, Hexagon::STrib_indexed_shl_cPt_nv_V4},
+  {"STrib_cdnNotPt_V4", 2, -1024, 1023, Hexagon::STrib_indexed_shl_cdnNotPt_V4},
+  {"STrib_cdnNotPt_nv_V4", 2, -1024, 1023,
+                                     Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4},
+  {"STrib_cdnPt_V4", 2, -1024, 1023, Hexagon::STrib_indexed_shl_cdnPt_V4},
+  {"STrib_cdnPt_nv_V4", 2, -1024, 1023, Hexagon::STrib_indexed_shl_cdnPt_nv_V4},
+  {"STrib_imm_V4", 2, -128, 127, Hexagon::STrib_indexed},
+  {"STrib_imm_abs_V4", 0, 0, 63, Hexagon::STrib_indexed},
+  {"STrib_imm_abs_cNotPt_V4", 1, 0, 63, Hexagon::STrib_indexed_cNotPt},
+  {"STrib_imm_abs_cNotPt_nv_V4", 1, 0, 63, Hexagon::STrib_indexed_cNotPt_nv_V4},
+  {"STrib_imm_abs_cPt_V4", 1, 0, 63, Hexagon::STrib_indexed_cPt},
+  {"STrib_imm_abs_cPt_nv_V4", 1, 0, 63, Hexagon::STrib_indexed_cPt_nv_V4},
+  {"STrib_imm_abs_cdnNotPt_V4", 1, 0, 63, Hexagon::STrib_indexed_cdnNotPt_V4},
+  {"STrib_imm_abs_cdnNotPt_nv_V4", 1, 0, 63,
+                                         Hexagon::STrib_indexed_cdnNotPt_nv_V4},
+  {"STrib_imm_abs_cdnPt_V4", 1, 0, 63, Hexagon::STrib_indexed_cdnPt_V4},
+  {"STrib_imm_abs_cdnPt_nv_V4", 1, 0, 63, Hexagon::STrib_indexed_cdnPt_nv_V4},
+  {"STrib_imm_abs_nv_V4", 0, 0, 63, Hexagon::STrib_indexed_nv_V4},
+  {"STrib_imm_cNotPt_V4", 3, -32, 31, Hexagon::STrib_indexed_cNotPt},
+  {"STrib_imm_cPt_V4", 3, -32, 31, Hexagon::STrib_indexed_cPt},
+  {"STrib_imm_cdnNotPt_V4", 3, -32, 31, Hexagon::STrib_indexed_cdnNotPt_V4},
+  {"STrib_imm_cdnPt_V4", 3, -32, 31, Hexagon::STrib_indexed_cdnPt_V4},
+  {"STrib_ind_lo_V4", 2, 0, 0, -1},
+  {"STrib_indexed", 1, -1024, 1023, Hexagon::STrib_indexed_shl_V4},
+  {"STrib_indexed_cNotPt", 2, 0, 63, Hexagon::STrib_indexed_shl_cNotPt_V4},
+  {"STrib_indexed_cNotPt_nv_V4", 2, 0, 63,
+                                       Hexagon::STrib_indexed_shl_cNotPt_nv_V4},
+  {"STrib_indexed_cPt", 2, 0, 63, Hexagon::STrib_indexed_shl_cPt_V4},
+  {"STrib_indexed_cPt_nv_V4", 2, 0, 63, Hexagon::STrib_indexed_shl_cPt_nv_V4},
+  {"STrib_indexed_cdnNotPt_V4", 2, 0, 63,
+                                        Hexagon::STrib_indexed_shl_cdnNotPt_V4},
+  {"STrib_indexed_cdnNotPt_nv_V4", 2, 0, 63,
+                                     Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4},
+  {"STrib_indexed_cdnPt_V4", 2, 0, 63, Hexagon::STrib_indexed_shl_cdnPt_V4},
+  {"STrib_indexed_cdnPt_nv_V4", 2, 0, 63,
+                                        Hexagon::STrib_indexed_shl_cdnPt_nv_V4},
+  {"STrib_indexed_nv_V4", 1, -1024, 1023, Hexagon::STrib_indexed_shl_nv_V4},
+  {"STrib_indexed_shl_V4", -1, 0, 0, -1},
+  {"STrib_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
+  {"STrib_indexed_shl_cNotPt_nv_V4", -1, 0, 0, -1},
+  {"STrib_indexed_shl_cPt_V4", -1, 0, 0, -1},
+  {"STrib_indexed_shl_cPt_nv_V4", -1, 0, 0, -1},
+  {"STrib_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
+  {"STrib_indexed_shl_cdnNotPt_nv_V4", -1, 0, 0, -1},
+  {"STrib_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
+  {"STrib_indexed_shl_cdnPt_nv_V4", -1, 0, 0, -1},
+  {"STrib_indexed_shl_nv_V4", -1, 0, 0, -1},
+  {"STrib_nv_V4", 1, -1024, 1023, Hexagon::STrib_indexed_shl_nv_V4},
+  {"STrib_shl_V4", 2, 0, 63, -1},
+  {"STrib_shl_nv_V4", 2, 0, 63, -1},
+  {"STrid", 1, -8192, 8184, Hexagon::STrid_indexed_shl_V4},
+  {"STrid_GP", -1, 0, 0, -1},
+  {"STrid_GP_V4", -1, 0, 0, -1},
+  {"STrid_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"STrid_GP_cPt_V4", -1, 0, 0, -1},
+  {"STrid_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"STrid_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"STrid_abs_V4", 0, 0, 0, Hexagon::STrid_indexed},
+  {"STrid_abs_cNotPt_V4", 1, 0, 0, Hexagon::STrid_indexed_cNotPt},
+  {"STrid_abs_cPt_V4", 1, 0, 0, Hexagon::STrid_indexed_cPt},
+  {"STrid_abs_cdnNotPt_V4", 1, 0, 0, Hexagon::STrid_indexed_cdnNotPt_V4},
+  {"STrid_abs_cdnPt_V4", 1, 0, 0, Hexagon::STrid_indexed_cdnPt_V4},
+  {"STrid_abs_set_V4", 2, 0, 0, -1},
+  {"STrid_abs_setimm_V4", 2, 0, 63, -1},
+  {"STrid_cNotPt", 2, -8192, 8184, Hexagon::STrid_indexed_shl_cNotPt_V4},
+  {"STrid_cPt", 2, -8192, 8184, Hexagon::STrid_indexed_shl_cPt_V4},
+  {"STrid_cdnNotPt_V4", 2, -8192, 8184, Hexagon::STrid_indexed_shl_cdnNotPt_V4},
+  {"STrid_cdnPt_V4", 2, -8192, 8184, Hexagon::STrid_indexed_shl_cdnPt_V4},
+  {"STrid_f", 1, -8192, 8184, Hexagon::STrid_indexed_shl_V4},
+  {"STrid_ind_lo_V4", 2, 0, 0, -1},
+  {"STrid_indexed", 1, -8192, 8184, Hexagon::STrid_indexed_shl_V4},
+  {"STrid_indexed_cNotPt", 2, 0, 504, Hexagon::STrid_indexed_shl_cNotPt_V4},
+  {"STrid_indexed_cPt", 2, 0, 504, Hexagon::STrid_indexed_shl_cPt_V4},
+  {"STrid_indexed_cdnNotPt_V4", 2, 0, 504,
+                                        Hexagon::STrid_indexed_shl_cdnNotPt_V4},
+  {"STrid_indexed_cdnPt_V4", 2, 0, 504, Hexagon::STrid_indexed_shl_cdnPt_V4},
+  {"STrid_indexed_f", 1, -8192, 8184, Hexagon::STrid_indexed_shl_V4},
+  {"STrid_indexed_shl_V4", -1, 0, 0, -1},
+  {"STrid_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
+  {"STrid_indexed_shl_cPt_V4", -1, 0, 0, -1},
+  {"STrid_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
+  {"STrid_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
+  {"STrid_shl_V4", 2, 0, 63, -1},
+  {"STrih", 1, -2048, 2046, Hexagon::STrih_indexed_shl_V4},
+  {"STrih_GP", -1, 0, 0, -1},
+  {"STrih_GP_V4", -1, 0, 0, -1},
+  {"STrih_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"STrih_GP_cNotPt_nv_V4", -1, 0, 0, -1},
+  {"STrih_GP_cPt_V4", -1, 0, 0, -1},
+  {"STrih_GP_cPt_nv_V4", -1, 0, 0, -1},
+  {"STrih_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"STrih_GP_cdnNotPt_nv_V4", -1, 0, 0, -1},
+  {"STrih_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"STrih_GP_cdnPt_nv_V4", -1, 0, 0, -1},
+  {"STrih_GP_nv_V4", -1, 0, 0, -1},
+  {"STrih_abs_V4", 0, 0, 0, Hexagon::STrih_indexed},
+  {"STrih_abs_cNotPt_V4", 1, 0, 0, Hexagon::STrih_indexed_cNotPt},
+  {"STrih_abs_cNotPt_nv_V4", 1, 0, 0, Hexagon::STrih_indexed_cNotPt_nv_V4},
+  {"STrih_abs_cPt_V4", 1, 0, 0, Hexagon::STrih_indexed_cPt},
+  {"STrih_abs_cPt_nv_V4", 1, 0, 0, Hexagon::STrih_indexed_cPt_nv_V4},
+  {"STrih_abs_cdnNotPt_V4", 1, 0, 0, Hexagon::STrih_indexed_cdnNotPt_V4},
+  {"STrih_abs_cdnNotPt_nv_V4", 1, 0, 0, Hexagon::STrih_indexed_cdnNotPt_nv_V4},
+  {"STrih_abs_cdnPt_V4", 1, 0, 0, Hexagon::STrih_indexed_cdnPt_V4},
+  {"STrih_abs_cdnPt_nv_V4", 1, 0, 0, Hexagon::STrih_indexed_cdnPt_nv_V4},
+  {"STrih_abs_nv_V4", 0, 0, 0, Hexagon::STrih_indexed_nv_V4},
+  {"STrih_abs_set_V4", 2, 0, 0, -1},
+  {"STrih_abs_setimm_V4", 2, 0, 63, -1},
+  {"STrih_cNotPt", 2, -2048, 2046, Hexagon::STrih_indexed_shl_cNotPt_V4},
+  {"STrih_cNotPt_nv_V4", 2, -2048, 2046,
+                                       Hexagon::STrih_indexed_shl_cNotPt_nv_V4},
+  {"STrih_cPt", 2, -2048, 2046, Hexagon::STrih_indexed_shl_cPt_V4},
+  {"STrih_cPt_nv_V4", 2, -2048, 2046, Hexagon::STrih_indexed_shl_cPt_nv_V4},
+  {"STrih_cdnNotPt_V4", 2, -2048, 2046, Hexagon::STrih_indexed_shl_cdnNotPt_V4},
+  {"STrih_cdnNotPt_nv_V4", 2, -2048, 2046,
+                                     Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4},
+  {"STrih_cdnPt_V4", 2, -2048, 2046, Hexagon::STrih_indexed_shl_cdnPt_V4},
+  {"STrih_cdnPt_nv_V4", 2, -2048, 2046, Hexagon::STrih_indexed_shl_cdnPt_nv_V4},
+  {"STrih_imm_V4", 2, -128, 127, Hexagon::STrih_indexed},
+  {"STrih_imm_abs_V4", 0, 0, 63, Hexagon::STrih_indexed},
+  {"STrih_imm_abs_cNotPt_V4", 1, 0, 63, Hexagon::STrih_indexed_cNotPt},
+  {"STrih_imm_abs_cNotPt_nv_V4", 1, 0, 63, Hexagon::STrih_indexed_cNotPt_nv_V4},
+  {"STrih_imm_abs_cPt_V4", 1, 0, 63, Hexagon::STrih_indexed_cPt},
+  {"STrih_imm_abs_cPt_nv_V4", 1, 0, 63, Hexagon::STrih_indexed_cPt_nv_V4},
+  {"STrih_imm_abs_cdnNotPt_V4", 1, 0, 63, Hexagon::STrih_indexed_cdnNotPt_V4},
+  {"STrih_imm_abs_cdnNotPt_nv_V4", 1, 0, 63,
+                                         Hexagon::STrih_indexed_cdnNotPt_nv_V4},
+  {"STrih_imm_abs_cdnPt_V4", 1, 0, 63, Hexagon::STrih_indexed_cdnPt_V4},
+  {"STrih_imm_abs_cdnPt_nv_V4", 1, 0, 63, Hexagon::STrih_indexed_cdnPt_nv_V4},
+  {"STrih_imm_abs_nv_V4", 0, 0, 63, Hexagon::STrih_indexed_nv_V4},
+  {"STrih_imm_cNotPt_V4", 3, -32, 31, Hexagon::STrih_indexed_cNotPt},
+  {"STrih_imm_cPt_V4", 3, -32, 31, Hexagon::STrih_indexed_cPt},
+  {"STrih_imm_cdnNotPt_V4", 3, -32, 31, Hexagon::STrih_indexed_cdnNotPt_V4},
+  {"STrih_imm_cdnPt_V4", 3, -32, 31, Hexagon::STrih_indexed_cdnPt_V4},
+  {"STrih_ind_lo_V4", 2, 0, 0, -1},
+  {"STrih_indexed", 1, -2048, 2046, Hexagon::STrih_indexed_shl_V4},
+  {"STrih_indexed_cNotPt", 2, 0, 126, Hexagon::STrih_indexed_shl_cNotPt_V4},
+  {"STrih_indexed_cNotPt_nv_V4", 2, 0, 126,
+                                       Hexagon::STrih_indexed_shl_cNotPt_nv_V4},
+  {"STrih_indexed_cPt", 2, 0, 126, Hexagon::STrih_indexed_shl_cPt_V4},
+  {"STrih_indexed_cPt_nv_V4", 2, 0, 126, Hexagon::STrih_indexed_shl_cPt_nv_V4},
+  {"STrih_indexed_cdnNotPt_V4", 2, 0, 126,
+                                        Hexagon::STrih_indexed_shl_cdnNotPt_V4},
+  {"STrih_indexed_cdnNotPt_nv_V4", 2, 0, 126,
+                                     Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4},
+  {"STrih_indexed_cdnPt_V4", 2, 0, 126, Hexagon::STrih_indexed_shl_cdnPt_V4},
+  {"STrih_indexed_cdnPt_nv_V4", 2, 0, 126,
+                                        Hexagon::STrih_indexed_shl_cdnPt_nv_V4},
+  {"STrih_indexed_nv_V4", 1, -2048, 2046, Hexagon::STrih_indexed_shl_nv_V4},
+  {"STrih_indexed_shl_V4", -1, 0, 0, -1},
+  {"STrih_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
+  {"STrih_indexed_shl_cNotPt_nv_V4", -1, 0, 0, -1},
+  {"STrih_indexed_shl_cPt_V4", -1, 0, 0, -1},
+  {"STrih_indexed_shl_cPt_nv_V4", -1, 0, 0, -1},
+  {"STrih_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
+  {"STrih_indexed_shl_cdnNotPt_nv_V4", -1, 0, 0, -1},
+  {"STrih_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
+  {"STrih_indexed_shl_cdnPt_nv_V4", -1, 0, 0, -1},
+  {"STrih_indexed_shl_nv_V4", -1, 0, 0, -1},
+  {"STrih_nv_V4", 1, -2048, 2046, Hexagon::STrih_indexed_shl_nv_V4},
+  {"STrih_offset_ext_V4", 2, 0, 0, Hexagon::STrih_indexed},
+  {"STrih_shl_V4", 2, 0, 63, -1},
+  {"STrih_shl_nv_V4", 2, 0, 63, -1},
+  {"STriw", 1, -4096, 4092, Hexagon::STriw_indexed_shl_V4},
+  {"STriw_GP", -1, 0, 0, -1},
+  {"STriw_GP_V4", -1, 0, 0, -1},
+  {"STriw_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"STriw_GP_cNotPt_nv_V4", -1, 0, 0, -1},
+  {"STriw_GP_cPt_V4", -1, 0, 0, -1},
+  {"STriw_GP_cPt_nv_V4", -1, 0, 0, -1},
+  {"STriw_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"STriw_GP_cdnNotPt_nv_V4", -1, 0, 0, -1},
+  {"STriw_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"STriw_GP_cdnPt_nv_V4", -1, 0, 0, -1},
+  {"STriw_GP_nv_V4", -1, 0, 0, -1},
+  {"STriw_abs_V4", 0, 0, 0, Hexagon::STriw_indexed},
+  {"STriw_abs_cNotPt_V4", 1, 0, 0, Hexagon::STriw_indexed_cNotPt},
+  {"STriw_abs_cNotPt_nv_V4", 1, 0, 0, Hexagon::STriw_indexed_cNotPt_nv_V4},
+  {"STriw_abs_cPt_V4", 1, 0, 0, Hexagon::STriw_indexed_cPt},
+  {"STriw_abs_cPt_nv_V4", 1, 0, 0, Hexagon::STriw_indexed_cPt_nv_V4},
+  {"STriw_abs_cdnNotPt_V4", 1, 0, 0, Hexagon::STriw_indexed_cdnNotPt_V4},
+  {"STriw_abs_cdnNotPt_nv_V4", 1, 0, 0, Hexagon::STriw_indexed_cdnNotPt_nv_V4},
+  {"STriw_abs_cdnPt_V4", 1, 0, 0, Hexagon::STriw_indexed_cdnPt_V4},
+  {"STriw_abs_cdnPt_nv_V4", 1, 0, 0, Hexagon::STriw_indexed_cdnPt_nv_V4},
+  {"STriw_abs_nv_V4", 0, 0, 0, Hexagon::STriw_indexed_nv_V4},
+  {"STriw_abs_set_V4", 2, 0, 0, -1},
+  {"STriw_abs_setimm_V4", 2, 0, 63, -1},
+  {"STriw_cNotPt", 2, -4096, 4092, Hexagon::STriw_indexed_shl_cNotPt_V4},
+  {"STriw_cNotPt_nv_V4", 2, -4096, 4092,
+                                       Hexagon::STriw_indexed_shl_cNotPt_nv_V4},
+  {"STriw_cPt", 2, -4096, 4092, Hexagon::STriw_indexed_shl_cPt_V4},
+  {"STriw_cPt_nv_V4", 2, -4096, 4092, Hexagon::STriw_indexed_shl_cPt_nv_V4},
+  {"STriw_cdnNotPt_V4", 2, -4096, 4092, Hexagon::STriw_indexed_shl_cdnNotPt_V4},
+  {"STriw_cdnNotPt_nv_V4", 2, -4096, 4092,
+                                     Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4},
+  {"STriw_cdnPt_V4", 2, -4096, 4092, Hexagon::STriw_indexed_shl_cdnPt_V4},
+  {"STriw_cdnPt_nv_V4", 2, -4096, 4092, Hexagon::STriw_indexed_shl_cdnPt_nv_V4},
+  {"STriw_f", 1, -4096, 4092, Hexagon::STriw_indexed_shl_V4},
+  {"STriw_imm_V4", 2, -128, 127, Hexagon::STriw_indexed},
+  {"STriw_imm_abs_V4", 0, 0, 63, Hexagon::STriw_indexed},
+  {"STriw_imm_abs_cNotPt_V4", 1, 0, 63, Hexagon::STriw_indexed_cNotPt},
+  {"STriw_imm_abs_cNotPt_nv_V4", 1, 0, 63, Hexagon::STriw_indexed_cNotPt_nv_V4},
+  {"STriw_imm_abs_cPt_V4", 1, 0, 63, Hexagon::STriw_indexed_cPt},
+  {"STriw_imm_abs_cPt_nv_V4", 1, 0, 63, Hexagon::STriw_indexed_cPt_nv_V4},
+  {"STriw_imm_abs_cdnNotPt_V4", 1, 0, 63, Hexagon::STriw_indexed_cdnNotPt_V4},
+  {"STriw_imm_abs_cdnNotPt_nv_V4", 1, 0, 63,
+                                         Hexagon::STriw_indexed_cdnNotPt_nv_V4},
+  {"STriw_imm_abs_cdnPt_V4", 1, 0, 63, Hexagon::STriw_indexed_cdnPt_V4},
+  {"STriw_imm_abs_cdnPt_nv_V4", 1, 0, 63, Hexagon::STriw_indexed_cdnPt_nv_V4},
+  {"STriw_imm_abs_nv_V4", 0, 0, 63, Hexagon::STriw_indexed_nv_V4},
+  {"STriw_imm_cNotPt_V4", 3, -32, 31, Hexagon::STriw_indexed_cNotPt},
+  {"STriw_imm_cPt_V4", 3, -32, 31, Hexagon::STriw_indexed_cPt},
+  {"STriw_imm_cdnNotPt_V4", 3, -32, 31, Hexagon::STriw_indexed_cdnNotPt_V4},
+  {"STriw_imm_cdnPt_V4", 3, -32, 31, Hexagon::STriw_indexed_cdnPt_V4},
+  {"STriw_ind_lo_V4", 2, 0, 0, -1},
+  {"STriw_indexed", 1, -4096, 4092, Hexagon::STriw_indexed_shl_V4},
+  {"STriw_indexed_cNotPt", 2, 0, 252, Hexagon::STriw_indexed_shl_cNotPt_V4},
+  {"STriw_indexed_cNotPt_nv_V4", 2, 0, 252,
+                                       Hexagon::STriw_indexed_shl_cNotPt_nv_V4},
+  {"STriw_indexed_cPt", 2, 0, 252, Hexagon::STriw_indexed_shl_cPt_V4},
+  {"STriw_indexed_cPt_nv_V4", 2, 0, 252, Hexagon::STriw_indexed_shl_cPt_nv_V4},
+  {"STriw_indexed_cdnNotPt_V4", 2, 0, 252,
+                                        Hexagon::STriw_indexed_shl_cdnNotPt_V4},
+  {"STriw_indexed_cdnNotPt_nv_V4", 2, 0, 252,
+                                     Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4},
+  {"STriw_indexed_cdnPt_V4", 2, 0, 252, Hexagon::STriw_indexed_shl_cdnPt_V4},
+  {"STriw_indexed_cdnPt_nv_V4", 2, 0, 252,
+                                        Hexagon::STriw_indexed_shl_cdnPt_nv_V4},
+  {"STriw_indexed_f", 1, -4096, 4092, Hexagon::STriw_indexed_shl_V4},
+  {"STriw_indexed_nv_V4", 1, -4096, 4092, Hexagon::STriw_indexed_shl_nv_V4},
+  {"STriw_indexed_shl_V4", -1, 0, 0, -1},
+  {"STriw_indexed_shl_cNotPt_V4", -1, 0, 0, -1},
+  {"STriw_indexed_shl_cNotPt_nv_V4", -1, 0, 0, -1},
+  {"STriw_indexed_shl_cPt_V4", -1, 0, 0, -1},
+  {"STriw_indexed_shl_cPt_nv_V4", -1, 0, 0, -1},
+  {"STriw_indexed_shl_cdnNotPt_V4", -1, 0, 0, -1},
+  {"STriw_indexed_shl_cdnNotPt_nv_V4", -1, 0, 0, -1},
+  {"STriw_indexed_shl_cdnPt_V4", -1, 0, 0, -1},
+  {"STriw_indexed_shl_cdnPt_nv_V4", -1, 0, 0, -1},
+  {"STriw_indexed_shl_nv_V4", -1, 0, 0, -1},
+  {"STriw_nv_V4", 1, -4096, 4092, Hexagon::STriw_indexed_shl_nv_V4},
+  {"STriw_offset_ext_V4", 2, 0, 0, Hexagon::STriw_indexed},
+  {"STriw_pred", 1, -4096, 4092, -1},
+  {"STriw_pred_V4", 1, -4096, 4092, -1},
+  {"STriw_shl_V4", 2, 0, 63, -1},
+  {"STriw_shl_nv_V4", 2, 0, 63, -1},
+  {"STw_GP", -1, 0, 0, -1},
+  {"STw_GP_V4", -1, 0, 0, -1},
+  {"STw_GP_cNotPt_V4", -1, 0, 0, -1},
+  {"STw_GP_cNotPt_nv_V4", -1, 0, 0, -1},
+  {"STw_GP_cPt_V4", -1, 0, 0, -1},
+  {"STw_GP_cPt_nv_V4", -1, 0, 0, -1},
+  {"STw_GP_cdnNotPt_V4", -1, 0, 0, -1},
+  {"STw_GP_cdnNotPt_nv_V4", -1, 0, 0, -1},
+  {"STw_GP_cdnPt_V4", -1, 0, 0, -1},
+  {"STw_GP_cdnPt_nv_V4", -1, 0, 0, -1},
+  {"STw_GP_nv_V4", -1, 0, 0, -1},
+  {"SUB64_rr", -1, 0, 0, -1},
+  {"SUB_ri", 1, -512, 511, Hexagon::SUB_rr},
+  {"SUB_rr", -1, 0, 0, -1},
+  {"SUB_rr_cNotPt", -1, 0, 0, -1},
+  {"SUB_rr_cPt", -1, 0, 0, -1},
+  {"SUB_rr_cdnNotPt", -1, 0, 0, -1},
+  {"SUB_rr_cdnPt", -1, 0, 0, -1},
+  {"SUBi_ASLri_V4", 1, 0, 255, -1},
+  {"SUBi_LSRri_V4", 1, 0, 255, -1},
+  {"SUBri_acc", 3, -128, 127, Hexagon::SUBrr_acc},
+  {"SUBrr_acc", -1, 0, 0, -1},
+  {"SXTB", -1, 0, 0, -1},
+  {"SXTB_cNotPt_V4", -1, 0, 0, -1},
+  {"SXTB_cPt_V4", -1, 0, 0, -1},
+  {"SXTB_cdnNotPt_V4", -1, 0, 0, -1},
+  {"SXTB_cdnPt_V4", -1, 0, 0, -1},
+  {"SXTH", -1, 0, 0, -1},
+  {"SXTH_cNotPt_V4", -1, 0, 0, -1},
+  {"SXTH_cPt_V4", -1, 0, 0, -1},
+  {"SXTH_cdnNotPt_V4", -1, 0, 0, -1},
+  {"SXTH_cdnPt_V4", -1, 0, 0, -1},
+  {"SXTW", -1, 0, 0, -1},
+  {"TCRETURNR", -1, 0, 0, -1},
+  {"TCRETURNtext", -1, 0, 0, -1},
+  {"TCRETURNtg", -1, 0, 0, -1},
+  {"TFCR", -1, 0, 0, -1},
+  {"TFR", -1, 0, 0, -1},
+  {"TFR64", -1, 0, 0, -1},
+  {"TFR64_cNotPt", -1, 0, 0, -1},
+  {"TFR64_cPt", -1, 0, 0, -1},
+  {"TFRI", 1, -32768, 32767, Hexagon::TFR},
+  {"TFRI64", -1, 0, 0, -1},
+  {"TFRI_V4", 1, 0, 0, -1},
+  {"TFRI_cNotPt", 2, -2048, 2047, Hexagon::TFR_cNotPt},
+  {"TFRI_cNotPt_V4", 2, 0, 0, -1},
+  {"TFRI_cNotPt_f", 2, 0, 0, -1},
+  {"TFRI_cPt", 2, -2048, 2047, Hexagon::TFR_cPt},
+  {"TFRI_cPt_V4", 2, 0, 0, -1},
+  {"TFRI_cPt_f", 2, 0, 0, -1},
+  {"TFRI_cdnNotPt", 2, -2048, 2047, Hexagon::TFR_cdnNotPt},
+  {"TFRI_cdnNotPt_V4", 2, 0, 0, -1},
+  {"TFRI_cdnPt", 2, -2048, 2047, Hexagon::TFR_cdnPt},
+  {"TFRI_cdnPt_V4", 2, 0, 0, -1},
+  {"TFRI_f", 1, 0, 0, -1},
+  {"TFR_64", -1, 0, 0, -1},
+  {"TFR_FI", -1, 0, 0, -1},
+  {"TFR_FI_immext_V4", -1, 0, 0, -1},
+  {"TFR_PdFalse", -1, 0, 0, -1},
+  {"TFR_PdRs", -1, 0, 0, -1},
+  {"TFR_RsPd", -1, 0, 0, -1},
+  {"TFR_cNotPt", -1, 0, 0, -1},
+  {"TFR_cPt", -1, 0, 0, -1},
+  {"TFR_cdnNotPt", -1, 0, 0, -1},
+  {"TFR_cdnPt", -1, 0, 0, -1},
+  {"TFR_condset_ii", -1, 0, 0, -1},
+  {"TFR_condset_ii_f", -1, 0, 0, -1},
+  {"TFR_condset_ir", -1, 0, 0, -1},
+  {"TFR_condset_ir_f", -1, 0, 0, -1},
+  {"TFR_condset_ri", -1, 0, 0, -1},
+  {"TFR_condset_ri_f", -1, 0, 0, -1},
+  {"TFR_condset_rr", -1, 0, 0, -1},
+  {"TFR_condset_rr64_f", -1, 0, 0, -1},
+  {"TFR_condset_rr_f", -1, 0, 0, -1},
+  {"TOGBIT", -1, 0, 0, -1},
+  {"TOGBIT_31", -1, 0, 0, -1},
+  {"VALIGN_rrp", -1, 0, 0, -1},
+  {"VITPACK_pp", -1, 0, 0, -1},
+  {"VMUX_prr64", -1, 0, 0, -1},
+  {"VSPLICE_rrp", -1, 0, 0, -1},
+  {"XOR_pp", -1, 0, 0, -1},
+  {"XOR_rr", -1, 0, 0, -1},
+  {"XOR_rr64", -1, 0, 0, -1},
+  {"XOR_rr_cNotPt", -1, 0, 0, -1},
+  {"XOR_rr_cPt", -1, 0, 0, -1},
+  {"XOR_rr_cdnNotPt", -1, 0, 0, -1},
+  {"XOR_rr_cdnPt", -1, 0, 0, -1},
+  {"XORd_XORdd", -1, 0, 0, -1},
+  {"XORr_ANDr_NOTr_V4", -1, 0, 0, -1},
+  {"XORr_ANDrr_V4", -1, 0, 0, -1},
+  {"XORr_ORrr_V4", -1, 0, 0, -1},
+  {"XORr_XORrr_V4", -1, 0, 0, -1},
+  {"ZXTB", -1, 0, 0, -1},
+  {"ZXTB_cNotPt_V4", -1, 0, 0, -1},
+  {"ZXTB_cPt_V4", -1, 0, 0, -1},
+  {"ZXTB_cdnNotPt_V4", -1, 0, 0, -1},
+  {"ZXTB_cdnPt_V4", -1, 0, 0, -1},
+  {"ZXTH", -1, 0, 0, -1},
+  {"ZXTH_cNotPt_V4", -1, 0, 0, -1},
+  {"ZXTH_cPt_V4", -1, 0, 0, -1},
+  {"ZXTH_cdnNotPt_V4", -1, 0, 0, -1},
+  {"ZXTH_cdnPt_V4", -1, 0, 0, -1},
+  {"fADD64_rr", -1, 0, 0, -1},
+  {"fADD_rr", -1, 0, 0, -1},
+  {"fMUL64_rr", -1, 0, 0, -1},
+  {"fMUL_rr", -1, 0, 0, -1},
+  {"fSUB64_rr", -1, 0, 0, -1},
+  {"fSUB_rr", -1, 0, 0, -1},
+  {"INSTRUCTION_LIST_END", -1, 0, 0, -1},
+};
+
+#endif

diff --git a/lib/Target/Hexagon/HexagonConstExtInfo.h b/lib/Target/Hexagon/HexagonConstExtInfo.h
new file mode 100644 (file)
index 0000000..9b6a2da
--- /dev/null
+++ b/lib/Target/Hexagon/HexagonConstExtInfo.h
@@ -0,0 +1,41 @@
+//===--- HexagonConstExtInfo.h - Provides constant extender information ---===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains helper functions that extract constant extender
+// information for a specified instruction from the HexagonConstExtInfo table.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef HEXAGONCONSTEXT_H
+#define HEXAGONCONSTEXT_H
+namespace llvm {
+namespace HexagonConstExt {
+  typedef struct {
+    const char * Name;
+    const short CExtOpNum;
+    const int MinValue;
+    const int MaxValue;
+    const int NonExtOpcode;
+  } HexagonConstExtInfo;
+
+#include "HexagonCExtTable.h"
+
+/// HexagonConstExt - This namespace holds the constant extension related
+/// information.
+
+  bool isOperandExtended(unsigned short Opcode, unsigned short OperandNum);
+  unsigned short getCExtOpNum(unsigned short Opcode);
+  int getMinValue(unsigned short Opcode);
+  int getMaxValue(unsigned short Opcode);
+  bool NonExtEquivalentExists (unsigned short Opcode);
+  int getNonExtOpcode (unsigned short Opcode);
+}
+
+}
+#endif

diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index 5499134eb98b0e333669369690ff845562abffce..a22555d8b64ee48cb6e317bf158ab3b198c5731e 100644 (file)
--- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -94,6 +94,7 @@ public:
   SDNode *SelectConstant(SDNode *N);
   SDNode *SelectConstantFP(SDNode *N);
   SDNode *SelectAdd(SDNode *N);
+  bool isConstExtProfitable(SDNode *N) const;
 
   // Include the pieces autogenerated from the target description.
 #include "HexagonGenDAGISel.inc"
@@ -312,9 +313,13 @@ SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, DebugLoc dl) {
         cast<GlobalAddressSDNode>(Base)->getGlobal();
       SDValue TargAddr =
         CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
-      SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
-                                               dl, PointerTy,
-                                               TargAddr);
+      SDNode* NewBase;
+      if (Subtarget.hasV4TOps())
+        NewBase = CurDAG->getMachineNode(Hexagon::TFRI_V4,
+                                                  dl, PointerTy, TargAddr);
+      else
+        NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
+                                                  dl, PointerTy, TargAddr);
       // Figure out base + offset opcode
       if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed;
       else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed;
@@ -686,9 +691,13 @@ SDNode *HexagonDAGToDAGISel::SelectBaseOffsetStore(StoreSDNode *ST,
           cast<GlobalAddressSDNode>(Base)->getGlobal();
         SDValue TargAddr =
           CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
-        SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
-                                                 dl, PointerTy,
-                                                 TargAddr);
+        SDNode* NewBase;
+        if (Subtarget.hasV4TOps())
+          NewBase = CurDAG->getMachineNode(Hexagon::TFRI_V4,
+                                                    dl, PointerTy, TargAddr);
+        else
+          NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
+                                                    dl, PointerTy, TargAddr);
 
         // Figure out base + offset opcode
         if (StoredVT == MVT::i64) Opcode = Hexagon::STrid_indexed;
@@ -1507,3 +1516,13 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
   OutOps.push_back(Op1);
   return false;
 }
+
+bool HexagonDAGToDAGISel::isConstExtProfitable(SDNode *N) const {
+  unsigned UseCount = 0;
+  for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
+    UseCount++;
+  }
+
+  return (UseCount <= 1);
+
+}

diff --git a/lib/Target/Hexagon/HexagonImmediates.td b/lib/Target/Hexagon/HexagonImmediates.td
index e78bb790ae7d3cf88cbddbbffaa34d91f58fdb34..f0ea6b7a77f95baf145b762daf74eb9a174995ff 100644 (file)
--- a/lib/Target/Hexagon/HexagonImmediates.td
+++ b/lib/Target/Hexagon/HexagonImmediates.td
@@ -13,6 +13,12 @@ def s32Imm : Operand<i32> {
   let PrintMethod = "printImmOperand";
 }
 
+// f32Ext type is used to identify constant extended floating point
+// Immediate operands.
+def f32Ext : Operand<f32> {
+  let PrintMethod = "printImmOperand";
+}
+
 def s16Imm : Operand<i32> {
   let PrintMethod = "printImmOperand";
 }
@@ -506,3 +512,412 @@ def nOneImmPred  : PatLeaf<(i32 imm), [{
   return (-1 == v);
 }]>;
 
+// Operand types for constant extendable operands
+def s16Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def s12Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def s10Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def s9Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def s8Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def s6Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def s11_0Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def s11_1Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def s11_2Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def s11_3Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def u6Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def u7Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def u8Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def u9Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def u10Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def u6_0Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def u6_1Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def u6_2Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+def u6_3Ext : Operand<i32> {
+  let PrintMethod = "printExtOperand";
+}
+
+// Predicates for constant extendable operands
+def s16ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 16-bit sign extended field.
+    return isInt<16>(v);
+  else {
+    if (isInt<16>(v))
+      return true;
+
+    // Return true if extending this immediate is profitable and the value
+    // can fit in a 32-bit signed field.
+    if (isConstExtProfitable(Node) && isInt<32>(v))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def s10ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 10-bit sign extended field.
+    return isInt<10>(v);
+  else {
+    if (isInt<10>(v))
+      return true;
+
+    // Return true if extending this immediate is profitable and the value
+    // can fit in a 32-bit signed field.
+    if (isConstExtProfitable(Node) && isInt<32>(v))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def s9ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 9-bit sign extended field.
+    return isInt<9>(v);
+  else {
+    if (isInt<9>(v))
+      return true;
+
+    // Return true if extending this immediate is profitable and the value
+    // can fit in a 32-bit unsigned field.
+    if (isConstExtProfitable(Node) && isInt<32>(v))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def s8ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 8-bit sign extended field.
+    return isInt<8>(v);
+  else {
+    if (isInt<8>(v))
+      return true;
+
+    // Return true if extending this immediate is profitable and the value
+    // can fit in a 32-bit signed field.
+    if (isConstExtProfitable(Node) && isInt<32>(v))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def s8_16ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate fits in a 8-bit sign extended field.
+    return isInt<8>(v);
+  else {
+    if (isInt<8>(v))
+      return true;
+
+    // Return true if extending this immediate is profitable and the value
+    // can't fit in a 16-bit signed field. This is required to avoid
+    // unnecessary constant extenders.
+    if (isConstExtProfitable(Node) && !isInt<16>(v))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def s6ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 6-bit sign extended field.
+    return isInt<6>(v);
+  else {
+    if (isInt<6>(v))
+      return true;
+
+    // Return true if extending this immediate is profitable and the value
+    // can fit in a 32-bit unsigned field.
+    if (isConstExtProfitable(Node) && isInt<32>(v))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def s6_16ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate fits in a 6-bit sign extended field.
+    return isInt<6>(v);
+  else {
+    if (isInt<6>(v))
+      return true;
+
+    // Return true if extending this immediate is profitable and the value
+    // can't fit in a 16-bit signed field. This is required to avoid
+    // unnecessary constant extenders.
+    if (isConstExtProfitable(Node) && !isInt<16>(v))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def s6_10ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 6-bit sign extended field.
+    return isInt<6>(v);
+  else {
+    if (isInt<6>(v))
+      return true;
+
+    // Return true if extending this immediate is profitable and the value
+    // can't fit in a 10-bit signed field. This is required to avoid
+    // unnecessary constant extenders.
+    if (isConstExtProfitable(Node) && !isInt<10>(v))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def s11_0ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 11-bit sign extended field.
+    return isShiftedInt<11,0>(v);
+  else {
+    if (isInt<11>(v))
+      return true;
+
+    // Return true if extending this immediate is profitable and the value
+    // can fit in a 32-bit signed field.
+    if (isConstExtProfitable(Node) && isInt<32>(v))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def s11_1ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 12-bit sign extended field and
+    // is 2 byte aligned.
+    return isShiftedInt<11,1>(v);
+  else {
+    if (isInt<12>(v))
+      return isShiftedInt<11,1>(v);
+
+    // Return true if extending this immediate is profitable and the low 1 bit
+    // is zero (2-byte aligned).
+    if (isConstExtProfitable(Node) && isInt<32>(v) && ((v % 2) == 0))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def s11_2ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 13-bit sign extended field and
+    // is 4-byte aligned.
+    return isShiftedInt<11,2>(v);
+  else {
+    if (isInt<13>(v))
+      return isShiftedInt<11,2>(v);
+
+    // Return true if extending this immediate is profitable and the low 2-bits
+    // are zero (4-byte aligned).
+    if (isConstExtProfitable(Node)  && isInt<32>(v) && ((v % 4) == 0))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def s11_3ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 14-bit sign extended field and
+    // is 8-byte aligned.
+    return isShiftedInt<11,3>(v);
+  else {
+    if (isInt<14>(v))
+     return isShiftedInt<11,3>(v);
+
+    // Return true if extending this immediate is profitable and the low 3-bits
+    // are zero (8-byte aligned).
+    if (isConstExtProfitable(Node)  && isInt<32>(v) && ((v % 8) == 0))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def u6ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 6-bit unsigned field.
+    return isUInt<6>(v);
+  else {
+    if (isUInt<6>(v))
+      return true;
+
+    // Return true if extending this immediate is profitable and the value
+    // can fit in a 32-bit unsigned field.
+    if (isConstExtProfitable(Node) && isUInt<32>(v))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def u7ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 7-bit unsigned field.
+    return isUInt<7>(v);
+  else {
+    if (isUInt<7>(v))
+      return true;
+
+    // Return true if extending this immediate is profitable and the value
+    // can fit in a 32-bit unsigned field.
+    if (isConstExtProfitable(Node) && isUInt<32>(v))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def u8ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 8-bit unsigned field.
+    return isUInt<8>(v);
+  else {
+    if (isUInt<8>(v))
+      return true;
+
+    // Return true if extending this immediate is profitable and the value
+    // can fit in a 32-bit unsigned field.
+    if (isConstExtProfitable(Node) && isUInt<32>(v))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def u9ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 9-bit unsigned field.
+    return isUInt<9>(v);
+  else {
+    if (isUInt<9>(v))
+      return true;
+
+    // Return true if extending this immediate is profitable and the value
+    // can fit in a 32-bit unsigned field.
+    if (isConstExtProfitable(Node) && isUInt<32>(v))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def u6_2ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 8-bit unsigned field and
+    // is 4-byte aligned.
+    return isShiftedUInt<6,2>(v);
+  else {
+    if (isUInt<9>(v))
+      return isShiftedUInt<6,2>(v);
+
+    // Return true if extending this immediate is profitable and the value
+    // can fit in a 32-bit unsigned field.
+    if (isConstExtProfitable(Node) && isUInt<32>(v) && ((v % 4) == 0))
+      return true;
+    else
+      return false;
+  }
+}]>;
+
+def u6_3ExtPred  : PatLeaf<(i32 imm), [{
+  int64_t v = (int64_t)N->getSExtValue();
+  if (!Subtarget.hasV4TOps())
+    // Return true if the immediate can fit in a 9-bit unsigned field and
+    // is 8-byte aligned.
+    return isShiftedUInt<6,3>(v);
+  else {
+    if (isUInt<9>(v))
+      return isShiftedUInt<6,3>(v);
+
+    // Return true if extending this immediate is profitable and the value
+    // can fit in a 32-bit unsigned field.
+    if (isConstExtProfitable(Node) && isUInt<32>(v) && ((v % 8) == 0))
+      return true;
+    else
+      return false;
+  }
+}]>;

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 8286ca93f2d534882fc321b35c49f2b0bc3e530c..2448b688f5f370697b397683b112e7f6e01b45d1 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -27,6 +27,7 @@
 #define GET_INSTRINFO_CTOR
 #include "HexagonGenInstrInfo.inc"
 #include "HexagonGenDFAPacketizer.inc"
+#include "HexagonConstExtInfo.h"
 
 using namespace llvm;
 
@@ -95,6 +96,7 @@ unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
                                             int &FrameIndex) const {
   switch (MI->getOpcode()) {
   default: break;
+  case Hexagon::STriw_indexed:
   case Hexagon::STriw:
   case Hexagon::STrid:
   case Hexagon::STrih:
@@ -364,7 +366,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                       Align);
 
   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
-    BuildMI(MBB, I, DL, get(Hexagon::STriw))
+    BuildMI(MBB, I, DL, get(Hexagon::STriw_indexed))
           .addFrameIndex(FI).addImm(0)
           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
@@ -1312,72 +1314,85 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
     return false;
 
   const int Opc = MI->getOpcode();
+  int NumOperands = MI->getNumOperands();
+
+  // Keep a flag for upto 4 operands in the instructions, to indicate if
+  // that operand has been constant extended.
+  bool OpCExtended[4];
+  if (NumOperands > 4)
+    NumOperands = 4;
+
+  for (int i=0; i<NumOperands; i++)
+    OpCExtended[i] = (HexagonConstExt::isOperandExtended(Opc, 1) &&
+                      isConstExtended(MI));
 
   switch(Opc) {
   case Hexagon::TFRI:
-    return isInt<12>(MI->getOperand(1).getImm());
+   // Return true if MI is constant extended as predicated form will also be
+   // extended so immediate value doesn't have to fit within range.
+   return OpCExtended[1] ||  isInt<12>(MI->getOperand(1).getImm());
 
   case Hexagon::STrid:
   case Hexagon::STrid_indexed:
-    return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
+    return OpCExtended[1] || isShiftedUInt<6,3>(MI->getOperand(1).getImm());
 
   case Hexagon::STriw:
   case Hexagon::STriw_indexed:
   case Hexagon::STriw_nv_V4:
-    return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
+    return OpCExtended[1] || isShiftedUInt<6,2>(MI->getOperand(1).getImm());
 
   case Hexagon::STrih:
   case Hexagon::STrih_indexed:
   case Hexagon::STrih_nv_V4:
-    return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
+    return OpCExtended[1] || isShiftedUInt<6,1>(MI->getOperand(1).getImm());
 
   case Hexagon::STrib:
   case Hexagon::STrib_indexed:
   case Hexagon::STrib_nv_V4:
-    return isUInt<6>(MI->getOperand(1).getImm());
+    return OpCExtended[1] || isUInt<6>(MI->getOperand(1).getImm());
 
   case Hexagon::LDrid:
   case Hexagon::LDrid_indexed:
-    return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
+    return OpCExtended[2] || isShiftedUInt<6,3>(MI->getOperand(2).getImm());
 
   case Hexagon::LDriw:
   case Hexagon::LDriw_indexed:
-    return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
+    return OpCExtended[2] || isShiftedUInt<6,2>(MI->getOperand(2).getImm());
 
   case Hexagon::LDrih:
   case Hexagon::LDriuh:
   case Hexagon::LDrih_indexed:
   case Hexagon::LDriuh_indexed:
-    return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
+    return OpCExtended[2] || isShiftedUInt<6,1>(MI->getOperand(2).getImm());
 
   case Hexagon::LDrib:
   case Hexagon::LDriub:
   case Hexagon::LDrib_indexed:
   case Hexagon::LDriub_indexed:
-    return isUInt<6>(MI->getOperand(2).getImm());
+    return OpCExtended[2] || isUInt<6>(MI->getOperand(2).getImm());
 
   case Hexagon::POST_LDrid:
-    return isShiftedInt<4,3>(MI->getOperand(3).getImm());
+    return OpCExtended[3] || isShiftedInt<4,3>(MI->getOperand(3).getImm());
 
   case Hexagon::POST_LDriw:
-    return isShiftedInt<4,2>(MI->getOperand(3).getImm());
+    return OpCExtended[3] || isShiftedInt<4,2>(MI->getOperand(3).getImm());
 
   case Hexagon::POST_LDrih:
   case Hexagon::POST_LDriuh:
-    return isShiftedInt<4,1>(MI->getOperand(3).getImm());
+    return OpCExtended[3] || isShiftedInt<4,1>(MI->getOperand(3).getImm());
 
   case Hexagon::POST_LDrib:
   case Hexagon::POST_LDriub:
-    return isInt<4>(MI->getOperand(3).getImm());
+    return OpCExtended[3] || isInt<4>(MI->getOperand(3).getImm());
 
   case Hexagon::STrib_imm_V4:
   case Hexagon::STrih_imm_V4:
   case Hexagon::STriw_imm_V4:
-    return (isUInt<6>(MI->getOperand(1).getImm()) &&
-            isInt<6>(MI->getOperand(2).getImm()));
+    return ((OpCExtended[1] || isUInt<6>(MI->getOperand(1).getImm())) &&
+            (OpCExtended[2] || isInt<6>(MI->getOperand(2).getImm())));
 
   case Hexagon::ADD_ri:
-    return isInt<8>(MI->getOperand(2).getImm());
+    return OpCExtended[2] || isInt<8>(MI->getOperand(2).getImm());
 
   case Hexagon::ASLH:
   case Hexagon::ASRH:
@@ -2190,6 +2205,73 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
   case Hexagon::DEALLOC_RET_V4:
     return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
                               Hexagon::DEALLOC_RET_cNotPt_V4;
+
+  // Load Absolute Addressing -- global address.
+  case Hexagon::LDrib_abs_V4:
+    return !invertPredicate ? Hexagon::LDrib_abs_cPt_V4 :
+                              Hexagon::LDrib_abs_cNotPt_V4;
+  case Hexagon::LDriub_abs_V4:
+    return !invertPredicate ? Hexagon::LDriub_abs_cPt_V4 :
+                              Hexagon::LDriub_abs_cNotPt_V4;
+  case Hexagon::LDrih_abs_V4:
+    return !invertPredicate ? Hexagon::LDrih_abs_cPt_V4 :
+                              Hexagon::LDrih_abs_cNotPt_V4;
+  case Hexagon::LDriuh_abs_V4:
+    return !invertPredicate ? Hexagon::LDriuh_abs_cPt_V4 :
+                              Hexagon::LDriuh_abs_cNotPt_V4;
+  case Hexagon::LDriw_abs_V4:
+    return !invertPredicate ? Hexagon::LDriw_abs_cPt_V4 :
+                              Hexagon::LDriw_abs_cNotPt_V4;
+  case Hexagon::LDrid_abs_V4:
+    return !invertPredicate ? Hexagon::LDrid_abs_cPt_V4 :
+                              Hexagon::LDrid_abs_cNotPt_V4;
+
+  // Load Absolute Addressing -- immediate value.
+  case Hexagon::LDrib_imm_abs_V4:
+    return !invertPredicate ? Hexagon::LDrib_imm_abs_cPt_V4 :
+                              Hexagon::LDrib_imm_abs_cNotPt_V4;
+  case Hexagon::LDriub_imm_abs_V4:
+    return !invertPredicate ? Hexagon::LDriub_imm_abs_cPt_V4 :
+                              Hexagon::LDriub_imm_abs_cNotPt_V4;
+  case Hexagon::LDrih_imm_abs_V4:
+    return !invertPredicate ? Hexagon::LDrih_imm_abs_cPt_V4 :
+                              Hexagon::LDrih_imm_abs_cNotPt_V4;
+  case Hexagon::LDriuh_imm_abs_V4:
+    return !invertPredicate ? Hexagon::LDriuh_imm_abs_cPt_V4 :
+                              Hexagon::LDriuh_imm_abs_cNotPt_V4;
+  case Hexagon::LDriw_imm_abs_V4:
+    return !invertPredicate ? Hexagon::LDriw_imm_abs_cPt_V4 :
+                              Hexagon::LDriw_imm_abs_cNotPt_V4;
+
+  // Store Absolute Addressing.
+  case Hexagon::STrib_abs_V4:
+    return !invertPredicate ? Hexagon::STrib_abs_cPt_V4 :
+                              Hexagon::STrib_abs_cNotPt_V4;
+  case Hexagon::STrih_abs_V4:
+    return !invertPredicate ? Hexagon::STrih_abs_cPt_V4 :
+                              Hexagon::STrih_abs_cNotPt_V4;
+  case Hexagon::STriw_abs_V4:
+    return !invertPredicate ? Hexagon::STriw_abs_cPt_V4 :
+                              Hexagon::STriw_abs_cNotPt_V4;
+  case Hexagon::STrid_abs_V4:
+    return !invertPredicate ? Hexagon::STrid_abs_cPt_V4 :
+                              Hexagon::STrid_abs_cNotPt_V4;
+
+  // Store Absolute Addressing - global address.
+  case Hexagon::STrib_imm_abs_V4:
+    return !invertPredicate ? Hexagon::STrib_imm_abs_cPt_V4 :
+                              Hexagon::STrib_imm_abs_cNotPt_V4;
+  case Hexagon::STrih_imm_abs_V4:
+    return !invertPredicate ? Hexagon::STrih_imm_abs_cPt_V4 :
+                              Hexagon::STrih_imm_abs_cNotPt_V4;
+  case Hexagon::STriw_imm_abs_V4:
+    return !invertPredicate ? Hexagon::STriw_imm_abs_cPt_V4 :
+                              Hexagon::STriw_imm_abs_cNotPt_V4;
+
+  // Transfer
+  case Hexagon::TFRI_V4:
+    return !invertPredicate ? Hexagon::TFRI_cPt_V4 :
+                              Hexagon::TFRI_cNotPt_V4;
   }
   llvm_unreachable("Unexpected predicable instruction");
 }
@@ -2340,6 +2422,7 @@ isValidOffset(const int Opcode, const int Offset) const {
 
   case Hexagon::LDriw:
   case Hexagon::LDriw_f:
+  case Hexagon::STriw_indexed:
   case Hexagon::STriw:
   case Hexagon::STriw_f:
     assert((Offset % 4 == 0) && "Offset has incorrect alignment");
@@ -2805,3 +2888,71 @@ bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
 
   return false;
 }
+
+bool HexagonInstrInfo::isExpr(unsigned OpType) const {
+  switch(OpType) {
+  case MachineOperand::MO_MachineBasicBlock:
+  case MachineOperand::MO_GlobalAddress:
+  case MachineOperand::MO_ExternalSymbol:
+  case MachineOperand::MO_JumpTableIndex:
+  case MachineOperand::MO_ConstantPoolIndex:
+  case MachineOperand::MO_BlockAddress:
+    return true;
+  default:
+    return false;
+  }
+}
+
+bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
+  unsigned short Opcode = MI->getOpcode();
+  short ExtOpNum = HexagonConstExt::getCExtOpNum(Opcode);
+
+  // Instruction has no constant extended operand.
+  if (ExtOpNum == -1)
+    return false;
+
+
+  int MinValue = HexagonConstExt::getMinValue(Opcode);
+  int MaxValue = HexagonConstExt::getMaxValue(Opcode);
+  const MachineOperand &MO = MI->getOperand(ExtOpNum);
+  if (!MO.isImm()) // no range check if the operand is non-immediate.
+    return true;
+
+  int ImmValue =MO.getImm();
+  return (ImmValue < MinValue || ImmValue > MaxValue);
+
+}
+
+// Returns true if a particular operand is extended for an instruction.
+bool HexagonConstExt::isOperandExtended(unsigned short Opcode,
+                                  unsigned short OperandNum) {
+  return HexagonCExt[Opcode].CExtOpNum == OperandNum;
+}
+
+// Returns Operand Index for the constant extended instruction.
+unsigned short HexagonConstExt::getCExtOpNum(unsigned short Opcode)  {
+  return HexagonCExt[Opcode].CExtOpNum;
+}
+
+// Returns the min value that doesn't need to be extended.
+int HexagonConstExt::getMinValue(unsigned short Opcode) {
+  return HexagonCExt[Opcode].MinValue;
+}
+
+// Returns the max value that doesn't need to be extended.
+int HexagonConstExt::getMaxValue(unsigned short Opcode) {
+  return HexagonCExt[Opcode].MaxValue;
+}
+
+// Returns true if an instruction can be converted into a non-extended
+// equivalent instruction.
+bool HexagonConstExt::NonExtEquivalentExists (unsigned short Opcode) {
+  if (HexagonCExt[Opcode].NonExtOpcode < 0 )
+    return false;
+  return true;
+}
+
+// Returns opcode of the non-extended equivalent instruction.
+int HexagonConstExt::getNonExtOpcode (unsigned short Opcode) {
+  return HexagonCExt[Opcode].NonExtOpcode;
+}

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h
index 6a45871b67e23a732ba0c320ddf4e915c13f5421..e2c63c394be58f6f2defddc85540b18885184453 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -174,6 +174,8 @@ public:
   bool isNewValueJump(const MachineInstr* MI) const;
   unsigned getImmExtForm(const MachineInstr* MI) const;
   unsigned getNormalBranchForm(const MachineInstr* MI) const;
+  bool isExpr(unsigned OpType) const;
+  bool isConstExtended(MachineInstr *MI) const;
 
 private:
   int getMatchingCondBranchOpcode(int Opc, bool sense) const;

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td
index 8eb6868fc70d439e33891328888cad5362bfd74d..3902e09a06ce803469898a961973badc08a0e5b2 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -67,10 +67,14 @@ def FrameIndex : Operand<i32> {
 let PrintMethod = "printGlobalOperand" in
   def globaladdress : Operand<i32>;
 
+let PrintMethod = "printGlobalOperand" in
+  def globaladdressExt : Operand<i32>;
+
 let PrintMethod = "printJumpTable" in
  def jumptablebase : Operand<i32>;
 
 def brtarget : Operand<OtherVT>;
+def brtargetExt : Operand<OtherVT>;
 def calltarget : Operand<i32>;
 
 def bblabel : Operand<i32>;
@@ -115,10 +119,10 @@ multiclass CMP32_rr_ri_s10<string OpcStr, PatFrag OpNode> {
                  !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
                  [(set (i1 PredRegs:$dst),
                        (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
-  def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Imm:$c),
+  def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Ext:$c),
                  !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
                  [(set (i1 PredRegs:$dst),
-                       (OpNode (i32 IntRegs:$b), s10ImmPred:$c))]>;
+                       (OpNode (i32 IntRegs:$b), s10ExtPred:$c))]>;
 }
 
 multiclass CMP32_rr_ri_u9<string OpcStr, PatFrag OpNode> {
@@ -126,24 +130,24 @@ multiclass CMP32_rr_ri_u9<string OpcStr, PatFrag OpNode> {
                  !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
                  [(set (i1 PredRegs:$dst),
                        (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
-  def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Imm:$c),
+  def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Ext:$c),
                  !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
                  [(set (i1 PredRegs:$dst),
-                       (OpNode (i32 IntRegs:$b), u9ImmPred:$c))]>;
+                       (OpNode (i32 IntRegs:$b), u9ExtPred:$c))]>;
 }
 
 multiclass CMP32_ri_u8<string OpcStr, PatFrag OpNode> {
-  def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Imm:$c),
+  def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Ext:$c),
                  !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
                  [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
-                                                   u8ImmPred:$c))]>;
+                                                   u8ExtPred:$c))]>;
 }
 
 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
-  def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Imm:$c),
+  def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Ext:$c),
                  !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
                  [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
-                                                   s8ImmPred:$c))]>;
+                                                   s8ExtPred:$c))]>;
 }
 }
 
@@ -160,10 +164,10 @@ def ADD_rr : ALU32_rr<(outs IntRegs:$dst),
 
 let isPredicable = 1 in
 def ADD_ri : ALU32_ri<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, s16Imm:$src2),
+            (ins IntRegs:$src1, s16Ext:$src2),
             "$dst = add($src1, #$src2)",
             [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
-                                           s16ImmPred:$src2))]>;
+                                           s16ExtPred:$src2))]>;
 
 // Logical operations.
 let isPredicable = 1 in
@@ -181,10 +185,10 @@ def AND_rr : ALU32_rr<(outs IntRegs:$dst),
                                            (i32 IntRegs:$src2)))]>;
 
 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, s10Imm:$src2),
+            (ins IntRegs:$src1, s10Ext:$src2),
             "$dst = or($src1, #$src2)",
             [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
-                                          s10ImmPred:$src2))]>;
+                                          s10ExtPred:$src2))]>;
 
 def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
             (ins IntRegs:$src1),
@@ -192,10 +196,10 @@ def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
             [(set (i32 IntRegs:$dst), (not (i32 IntRegs:$src1)))]>;
 
 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, s10Imm:$src2),
+            (ins IntRegs:$src1, s10Ext:$src2),
             "$dst = and($src1, #$src2)",
             [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
-                                           s10ImmPred:$src2))]>;
+                                           s10ExtPred:$src2))]>;
 
 let isCommutable = 1, isPredicable = 1 in
 def OR_rr : ALU32_rr<(outs IntRegs:$dst),
@@ -224,15 +228,15 @@ def SUB_rr : ALU32_rr<(outs IntRegs:$dst),
 
 // Rd32=sub(#s10,Rs32)
 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
-            (ins s10Imm:$src1, IntRegs:$src2),
+            (ins s10Ext:$src1, IntRegs:$src2),
             "$dst = sub(#$src1, $src2)",
-            [(set IntRegs:$dst, (sub s10ImmPred:$src1, IntRegs:$src2))]>;
+            [(set IntRegs:$dst, (sub s10ExtPred:$src1, IntRegs:$src2))]>;
 
 // Transfer immediate.
 let isMoveImm = 1, isReMaterializable = 1, isPredicable = 1 in
-def TFRI : ALU32_ri<(outs IntRegs:$dst), (ins s16Imm:$src1),
+def TFRI : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
            "$dst = #$src1",
-           [(set (i32 IntRegs:$dst), s16ImmPred:$src1)]>;
+           [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
 
 // Transfer register.
 let neverHasSideEffects = 1, isPredicable = 1 in
@@ -286,25 +290,25 @@ def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
                                                     (i32 IntRegs:$src2),
                                                     (i32 IntRegs:$src3))))]>;
 
-def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
+def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
                                                 IntRegs:$src3),
              "$dst = mux($src1, #$src2, $src3)",
              [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
-                                                    s8ImmPred:$src2,
+                                                    s8ExtPred:$src2,
                                                     (i32 IntRegs:$src3))))]>;
 
 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
-                                                s8Imm:$src3),
+                                                s8Ext:$src3),
              "$dst = mux($src1, $src2, #$src3)",
              [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
                                                     (i32 IntRegs:$src2),
-                                                    s8ImmPred:$src3)))]>;
+                                                    s8ExtPred:$src3)))]>;
 
-def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
+def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
                                                 s8Imm:$src3),
              "$dst = mux($src1, #$src2, #$src3)",
              [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
-                                                    s8ImmPred:$src2,
+                                                    s8ExtPred:$src2,
                                                     s8ImmPred:$src3)))]>;
 
 // Shift halfword.
@@ -351,25 +355,25 @@ def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
 // Conditional add.
 let neverHasSideEffects = 1, isPredicated = 1 in
 def ADD_ri_cPt : ALU32_ri<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, s8Ext:$src3),
             "if ($src1) $dst = add($src2, #$src3)",
             []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def ADD_ri_cNotPt : ALU32_ri<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, s8Ext:$src3),
             "if (!$src1) $dst = add($src2, #$src3)",
             []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def ADD_ri_cdnPt : ALU32_ri<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, s8Ext:$src3),
             "if ($src1.new) $dst = add($src2, #$src3)",
             []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def ADD_ri_cdnNotPt : ALU32_ri<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, s8Ext:$src3),
             "if (!$src1.new) $dst = add($src2, #$src3)",
             []>;
 
@@ -551,13 +555,13 @@ def TFR64_cNotPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
                  []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
-def TFRI_cPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Imm:$src2),
+def TFRI_cPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Ext:$src2),
                "if ($src1) $dst = #$src2",
                []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def TFRI_cNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
-                                                     s12Imm:$src2),
+                                                     s12Ext:$src2),
                   "if (!$src1) $dst = #$src2",
                   []>;
 
@@ -575,13 +579,13 @@ def TFR_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def TFRI_cdnPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
-                                                    s12Imm:$src2),
+                                                    s12Ext:$src2),
                  "if ($src1.new) $dst = #$src2",
                  []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def TFRI_cdnNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
-                                                       s12Imm:$src2),
+                                                       s12Ext:$src2),
                     "if (!$src1.new) $dst = #$src2",
                     []>;
 
@@ -923,6 +927,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
 /// increment operand.
 ///
 // Load doubleword.
+// Rdd=memd(Rs)"
 let isPredicable = 1 in
 def LDrid : LDInst<(outs DoubleRegs:$dst),
             (ins MEMri:$addr),
@@ -931,11 +936,11 @@ def LDrid : LDInst<(outs DoubleRegs:$dst),
 
 let isPredicable = 1, AddedComplexity = 20 in
 def LDrid_indexed : LDInst<(outs DoubleRegs:$dst),
-            (ins IntRegs:$src1, s11_3Imm:$offset),
+            (ins IntRegs:$src1, s11_3Ext:$offset),
             "$dst = memd($src1+#$offset)",
             [(set (i64 DoubleRegs:$dst),
                   (i64 (load (add (i32 IntRegs:$src1),
-                                  s11_3ImmPred:$offset))))]>;
+                                  s11_3ExtPred:$offset))))]>;
 
 let neverHasSideEffects = 1 in
 def LDrid_GP : LDInst2<(outs DoubleRegs:$dst),
@@ -974,13 +979,13 @@ def LDrid_cNotPt : LDInst2<(outs DoubleRegs:$dst),
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDrid_indexed_cPt : LDInst2<(outs DoubleRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_3Ext:$src3),
             "if ($src1) $dst = memd($src2+#$src3)",
             []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDrid_indexed_cNotPt : LDInst2<(outs DoubleRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_3Ext:$src3),
             "if (!$src1) $dst = memd($src2+#$src3)",
             []>;
 
@@ -1012,13 +1017,13 @@ def LDrid_cdnNotPt : LDInst2<(outs DoubleRegs:$dst),
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDrid_indexed_cdnPt : LDInst2<(outs DoubleRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_3Ext:$src3),
             "if ($src1.new) $dst = memd($src2+#$src3)",
             []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDrid_indexed_cdnNotPt : LDInst2<(outs DoubleRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_3Ext:$src3),
             "if (!$src1.new) $dst = memd($src2+#$src3)",
             []>;
 
@@ -1037,11 +1042,11 @@ def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
 // Indexed load byte.
 let isPredicable = 1, AddedComplexity = 20 in
 def LDrib_indexed : LDInst<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, s11_0Imm:$offset),
+            (ins IntRegs:$src1, s11_0Ext:$offset),
             "$dst = memb($src1+#$offset)",
             [(set (i32 IntRegs:$dst),
                   (i32 (sextloadi8 (add (i32 IntRegs:$src1),
-                                        s11_0ImmPred:$offset))))]>;
+                                        s11_0ExtPred:$offset))))]>;
 
 // Indexed load byte any-extend.
 let AddedComplexity = 20 in
@@ -1091,13 +1096,13 @@ def LDrib_cNotPt : LDInst2<(outs IntRegs:$dst),
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDrib_indexed_cPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3),
             "if ($src1) $dst = memb($src2+#$src3)",
             []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDrib_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3),
             "if (!$src1) $dst = memb($src2+#$src3)",
             []>;
 
@@ -1129,13 +1134,13 @@ def LDrib_cdnNotPt : LDInst2<(outs IntRegs:$dst),
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDrib_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3),
             "if ($src1.new) $dst = memb($src2+#$src3)",
             []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDrib_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3),
             "if (!$src1.new) $dst = memb($src2+#$src3)",
             []>;
 
@@ -1149,11 +1154,11 @@ def LDrih : LDInst<(outs IntRegs:$dst),
 
 let isPredicable = 1, AddedComplexity = 20 in
 def LDrih_indexed : LDInst<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, s11_1Imm:$offset),
+            (ins IntRegs:$src1, s11_1Ext:$offset),
             "$dst = memh($src1+#$offset)",
             [(set (i32 IntRegs:$dst),
                   (i32 (sextloadi16 (add (i32 IntRegs:$src1),
-                                         s11_1ImmPred:$offset))))]>;
+                                         s11_1ExtPred:$offset))))]>;
 
 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
             (i32 (LDrih ADDRriS11_1:$addr))>;
@@ -1205,13 +1210,13 @@ def LDrih_cNotPt : LDInst2<(outs IntRegs:$dst),
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDrih_indexed_cPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3),
             "if ($src1) $dst = memh($src2+#$src3)",
             []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDrih_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3),
             "if (!$src1) $dst = memh($src2+#$src3)",
             []>;
 
@@ -1243,13 +1248,13 @@ def LDrih_cdnNotPt : LDInst2<(outs IntRegs:$dst),
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDrih_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3),
             "if ($src1.new) $dst = memh($src2+#$src3)",
             []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDrih_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3),
             "if (!$src1.new) $dst = memh($src2+#$src3)",
             []>;
 
@@ -1265,11 +1270,11 @@ def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
 
 let isPredicable = 1, AddedComplexity = 20 in
 def LDriub_indexed : LDInst<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, s11_0Imm:$offset),
+            (ins IntRegs:$src1, s11_0Ext:$offset),
             "$dst = memub($src1+#$offset)",
             [(set (i32 IntRegs:$dst),
                   (i32 (zextloadi8 (add (i32 IntRegs:$src1),
-                                        s11_0ImmPred:$offset))))]>;
+                                        s11_0ExtPred:$offset))))]>;
 
 let AddedComplexity = 20 in
 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
@@ -1304,13 +1309,13 @@ def LDriub_cNotPt : LDInst2<(outs IntRegs:$dst),
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDriub_indexed_cPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3),
             "if ($src1) $dst = memub($src2+#$src3)",
             []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDriub_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3),
             "if (!$src1) $dst = memub($src2+#$src3)",
             []>;
 
@@ -1342,13 +1347,13 @@ def LDriub_cdnNotPt : LDInst2<(outs IntRegs:$dst),
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDriub_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3),
             "if ($src1.new) $dst = memub($src2+#$src3)",
             []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDriub_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3),
             "if (!$src1.new) $dst = memub($src2+#$src3)",
             []>;
 
@@ -1362,11 +1367,11 @@ def LDriuh : LDInst<(outs IntRegs:$dst),
 // Indexed load unsigned halfword.
 let isPredicable = 1, AddedComplexity = 20 in
 def LDriuh_indexed : LDInst<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, s11_1Imm:$offset),
+            (ins IntRegs:$src1, s11_1Ext:$offset),
             "$dst = memuh($src1+#$offset)",
             [(set (i32 IntRegs:$dst),
                   (i32 (zextloadi16 (add (i32 IntRegs:$src1),
-                                         s11_1ImmPred:$offset))))]>;
+                                         s11_1ExtPred:$offset))))]>;
 
 let neverHasSideEffects = 1 in
 def LDriuh_GP : LDInst2<(outs IntRegs:$dst),
@@ -1397,13 +1402,13 @@ def LDriuh_cNotPt : LDInst2<(outs IntRegs:$dst),
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDriuh_indexed_cPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3),
             "if ($src1) $dst = memuh($src2+#$src3)",
             []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDriuh_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3),
             "if (!$src1) $dst = memuh($src2+#$src3)",
             []>;
 
@@ -1435,13 +1440,13 @@ def LDriuh_cdnNotPt : LDInst2<(outs IntRegs:$dst),
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDriuh_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3),
             "if ($src1.new) $dst = memuh($src2+#$src3)",
             []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDriuh_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3),
             "if (!$src1.new) $dst = memuh($src2+#$src3)",
             []>;
 
@@ -1462,10 +1467,10 @@ def LDriw_pred : LDInst<(outs PredRegs:$dst),
 // Indexed load.
 let isPredicable = 1, AddedComplexity = 20 in
 def LDriw_indexed : LDInst<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, s11_2Imm:$offset),
+            (ins IntRegs:$src1, s11_2Ext:$offset),
             "$dst = memw($src1+#$offset)",
             [(set IntRegs:$dst, (i32 (load (add IntRegs:$src1,
-                                           s11_2ImmPred:$offset))))]>;
+                                           s11_2ExtPred:$offset))))]>;
 
 let neverHasSideEffects = 1 in
 def LDriw_GP : LDInst2<(outs IntRegs:$dst),
@@ -1504,13 +1509,13 @@ def LDriw_cNotPt : LDInst2<(outs IntRegs:$dst),
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDriw_indexed_cPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3),
             "if ($src1) $dst = memw($src2+#$src3)",
             []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDriw_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3),
             "if (!$src1) $dst = memw($src2+#$src3)",
             []>;
 
@@ -1542,13 +1547,13 @@ def LDriw_cdnNotPt : LDInst2<(outs IntRegs:$dst),
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDriw_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3),
             "if ($src1.new) $dst = memw($src2+#$src3)",
             []>;
 
 let neverHasSideEffects = 1, isPredicated = 1 in
 def LDriw_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3),
             "if (!$src1.new) $dst = memw($src2+#$src3)",
             []>;
 
@@ -1583,10 +1588,10 @@ let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
 //===----------------------------------------------------------------------===//
 // Multiply and use lower result.
 // Rd=+mpyi(Rs,#u8)
-def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
+def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Ext:$src2),
               "$dst =+ mpyi($src1, #$src2)",
               [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
-                                             u8ImmPred:$src2))]>;
+                                             u8ExtPred:$src2))]>;
 
 // Rd=-mpyi(Rs,#u8)
 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, n8Imm:$src2),
@@ -1598,10 +1603,10 @@ def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, n8Imm:$src2),
 // s9 is NOT the same as m9 - but it works.. so far.
 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
 // depending on the value of m9. See Arch Spec.
-def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
+def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
               "$dst = mpyi($src1, #$src2)",
               [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
-                                             s9ImmPred:$src2))]>;
+                                             s9ExtPred:$src2))]>;
 
 // Rd=mpyi(Rs,Rt)
 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
@@ -1611,10 +1616,10 @@ def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 
 // Rx+=mpyi(Rs,#u8)
 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
+            (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
             "$dst += mpyi($src2, #$src3)",
             [(set (i32 IntRegs:$dst),
-                  (add (mul (i32 IntRegs:$src2), u8ImmPred:$src3),
+                  (add (mul (i32 IntRegs:$src2), u8ExtPred:$src3),
                        (i32 IntRegs:$src1)))],
             "$src1 = $dst">;
 
@@ -1629,11 +1634,11 @@ def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
 
 // Rx-=mpyi(Rs,#u8)
 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
+            (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
             "$dst -= mpyi($src2, #$src3)",
             [(set (i32 IntRegs:$dst),
                   (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
-                                                 u8ImmPred:$src3)))],
+                                                 u8ExtPred:$src3)))],
             "$src1 = $dst">;
 
 // Multiply and use upper result.
@@ -1719,10 +1724,10 @@ def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
              "$src1 = $dst">;
 
 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
-                            IntRegs:$src2, s8Imm:$src3),
+                            IntRegs:$src2, s8Ext:$src3),
              "$dst += add($src2, #$src3)",
              [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
-                                                 s8ImmPred:$src3),
+                                                 s8_16ExtPred:$src3),
                                             (i32 IntRegs:$src1)))],
              "$src1 = $dst">;
 
@@ -1735,11 +1740,11 @@ def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
              "$src1 = $dst">;
 
 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
-                            IntRegs:$src2, s8Imm:$src3),
+                            IntRegs:$src2, s8Ext:$src3),
              "$dst -= add($src2, #$src3)",
              [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
                                             (add (i32 IntRegs:$src2),
-                                                 s8ImmPred:$src3)))],
+                                                 s8_16ExtPred:$src3)))],
              "$src1 = $dst">;
 
 //===----------------------------------------------------------------------===//
@@ -1787,10 +1792,10 @@ def STrid : STInst<(outs),
 // Indexed store double word.
 let AddedComplexity = 10, isPredicable = 1 in
 def STrid_indexed : STInst<(outs),
-            (ins IntRegs:$src1, s11_3Imm:$src2,  DoubleRegs:$src3),
+            (ins IntRegs:$src1, s11_3Ext:$src2,  DoubleRegs:$src3),
             "memd($src1+#$src2) = $src3",
             [(store (i64 DoubleRegs:$src3),
-                    (add (i32 IntRegs:$src1), s11_3ImmPred:$src2))]>;
+                    (add (i32 IntRegs:$src1), s11_3ExtPred:$src2))]>;
 
 let neverHasSideEffects = 1 in
 def STrid_GP : STInst2<(outs),
@@ -1837,7 +1842,7 @@ def STrid_cNotPt : STInst2<(outs),
 let AddedComplexity = 10, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrid_indexed_cPt : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
+            (ins PredRegs:$src1, IntRegs:$src2, u6_3Ext:$src3,
                  DoubleRegs:$src4),
             "if ($src1) memd($src2+#$src3) = $src4",
             []>;
@@ -1846,7 +1851,7 @@ def STrid_indexed_cPt : STInst2<(outs),
 let AddedComplexity = 10, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrid_indexed_cNotPt : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
+            (ins PredRegs:$src1, IntRegs:$src2, u6_3Ext:$src3,
                  DoubleRegs:$src4),
             "if (!$src1) memd($src2+#$src3) = $src4",
             []>;
@@ -1883,10 +1888,10 @@ def STrib : STInst<(outs),
 
 let AddedComplexity = 10, isPredicable = 1 in
 def STrib_indexed : STInst<(outs),
-            (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
+            (ins IntRegs:$src1, s11_0Ext:$src2, IntRegs:$src3),
             "memb($src1+#$src2) = $src3",
             [(truncstorei8 (i32 IntRegs:$src3), (add (i32 IntRegs:$src1),
-                                                     s11_0ImmPred:$src2))]>;
+                                                     s11_0ExtPred:$src2))]>;
 
 // memb(gp+#u16:0)=Rt
 let neverHasSideEffects = 1 in
@@ -1934,14 +1939,14 @@ def STrib_cNotPt : STInst2<(outs),
 // if (Pv) memb(Rs+#u6:0)=Rt
 let neverHasSideEffects = 1, isPredicated = 1 in
 def STrib_indexed_cPt : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3, IntRegs:$src4),
             "if ($src1) memb($src2+#$src3) = $src4",
             []>;
 
 // if (!Pv) memb(Rs+#u6:0)=Rt
 let neverHasSideEffects = 1, isPredicated = 1 in
 def STrib_indexed_cNotPt : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3, IntRegs:$src4),
             "if (!$src1) memb($src2+#$src3) = $src4",
             []>;
 
@@ -1972,10 +1977,10 @@ def STrih : STInst<(outs),
 
 let AddedComplexity = 10, isPredicable = 1 in
 def STrih_indexed : STInst<(outs),
-            (ins IntRegs:$src1, s11_1Imm:$src2,  IntRegs:$src3),
+            (ins IntRegs:$src1, s11_1Ext:$src2,  IntRegs:$src3),
             "memh($src1+#$src2) = $src3",
             [(truncstorei16 (i32 IntRegs:$src3), (add (i32 IntRegs:$src1),
-                                                      s11_1ImmPred:$src2))]>;
+                                                      s11_1ExtPred:$src2))]>;
 
 let neverHasSideEffects = 1 in
 def STrih_GP : STInst2<(outs),
@@ -2021,14 +2026,14 @@ def STrih_cNotPt : STInst2<(outs),
 // if (Pv) memh(Rs+#u6:1)=Rt
 let neverHasSideEffects = 1, isPredicated = 1 in
 def STrih_indexed_cPt : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3, IntRegs:$src4),
             "if ($src1) memh($src2+#$src3) = $src4",
             []>;
 
 // if (!Pv) memh(Rs+#u6:1)=Rt
 let neverHasSideEffects = 1, isPredicated = 1 in
 def STrih_indexed_cNotPt : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3, IntRegs:$src4),
             "if (!$src1) memh($src2+#$src3) = $src4",
             []>;
 
@@ -2065,10 +2070,10 @@ def STriw : STInst<(outs),
 
 let AddedComplexity = 10, isPredicable = 1 in
 def STriw_indexed : STInst<(outs),
-            (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
+            (ins IntRegs:$src1, s11_2Ext:$src2, IntRegs:$src3),
             "memw($src1+#$src2) = $src3",
             [(store (i32 IntRegs:$src3),
-                    (add (i32 IntRegs:$src1), s11_2ImmPred:$src2))]>;
+                    (add (i32 IntRegs:$src1), s11_2ExtPred:$src2))]>;
 
 let neverHasSideEffects = 1 in
 def STriw_GP : STInst2<(outs),
@@ -2112,14 +2117,14 @@ def STriw_cNotPt : STInst2<(outs),
 // if (Pv) memw(Rs+#u6:2)=Rt
 let neverHasSideEffects = 1, isPredicated = 1 in
 def STriw_indexed_cPt : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3, IntRegs:$src4),
             "if ($src1) memw($src2+#$src3) = $src4",
             []>;
 
 // if (!Pv) memw(Rs+#u6:2)=Rt
 let neverHasSideEffects = 1, isPredicated = 1 in
 def STriw_indexed_cNotPt : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3, IntRegs:$src4),
             "if (!$src1) memw($src2+#$src3) = $src4",
             []>;
 
@@ -2409,12 +2414,24 @@ def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
                       []>;
 }
 
+let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
+def LOOP0_iext : CRInst<(outs), (ins brtargetExt:$offset, u10Imm:$src2),
+                      "loop0(##$offset, #$src2)",
+                      []>;
+}
+
 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
                       "loop0($offset, $src2)",
                       []>;
 }
 
+let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
+def LOOP0_rext : CRInst<(outs), (ins brtargetExt:$offset, IntRegs:$src2),
+                      "loop0(##$offset, $src2)",
+                      []>;
+}
+
 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
     Defs = [PC, LC0], Uses = [SA0, LC0] in {
 def ENDLOOP0 : Marker<(outs), (ins brtarget:$offset),
@@ -3150,8 +3167,8 @@ def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
 
 // Map cmple -> cmpgt.
 // rs <= rt -> !(rs > rt).
-def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ImmPred:$src2)),
-      (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ImmPred:$src2)))>;
+def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
+      (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
 
 // rs <= rt -> !(rs > rt).
 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
@@ -3164,8 +3181,8 @@ def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
 // Map cmpne -> cmpeq.
 // Hexagon_TODO: We should improve on this.
 // rs != rt -> !(rs == rt).
-def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
-      (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2))))>;
+def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
+      (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
 
 // Map cmpne(Rs) -> !cmpeqe(Rs).
 // rs != rt -> !(rs == rt).
@@ -3187,8 +3204,8 @@ def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
       (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
 
-def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ImmPred:$src2)),
-      (i1 (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2))>;
+def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
+      (i1 (CMPGEri (i32 IntRegs:$src1), s8ExtPred:$src2))>;
 
 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
 // rss >= rtt -> !(rtt > rss).
@@ -3198,8 +3215,8 @@ def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
 
 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
 // rs < rt -> !(rs >= rt).
-def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
-      (i1 (NOT_p (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2)))>;
+def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
+      (i1 (NOT_p (CMPGEri (i32 IntRegs:$src1), s8ExtPred:$src2)))>;
 
 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
 // rs < rt -> rt > rs.
@@ -3224,12 +3241,12 @@ def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
       (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
 
 // Generate cmpgeu(Rs, #u8)
-def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ImmPred:$src2)),
-      (i1 (CMPGEUri (i32 IntRegs:$src1), u8ImmPred:$src2))>;
+def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
+      (i1 (CMPGEUri (i32 IntRegs:$src1), u8ExtPred:$src2))>;
 
 // Generate cmpgtu(Rs, #u9)
-def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)),
-      (i1 (CMPGTUri (i32 IntRegs:$src1), u9ImmPred:$src2))>;
+def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
+      (i1 (CMPGTUri (i32 IntRegs:$src1), u9ExtPred:$src2))>;
 
 // Map from Rs >= Rt -> !(Rt > Rs).
 // rs >= rt -> !(rt > rs).

diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td
index 9878503874cd4cdb6e5ff65fb88bce9a4bdf426a..83fc27476c2604bb07ac59cd1c304beb8e3b6d16 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfoV4.td
+++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td
@@ -302,7 +302,7 @@ def COMBINE_ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
 
 let neverHasSideEffects = 1 in
 def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
-            (ins u6Imm:$addr),
+            (ins u6Ext:$addr),
             "$dst1 = memd($dst2=#$addr)",
             []>,
             Requires<[HasV4T]>;
@@ -310,7 +310,7 @@ def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 // Rd=memb(Re=#U6)
 let neverHasSideEffects = 1 in
 def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
-            (ins u6Imm:$addr),
+            (ins u6Ext:$addr),
             "$dst1 = memb($dst2=#$addr)",
             []>,
             Requires<[HasV4T]>;
@@ -318,7 +318,7 @@ def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 // Rd=memh(Re=#U6)
 let neverHasSideEffects = 1 in
 def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
-            (ins u6Imm:$addr),
+            (ins u6Ext:$addr),
             "$dst1 = memh($dst2=#$addr)",
             []>,
             Requires<[HasV4T]>;
@@ -326,7 +326,7 @@ def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 // Rd=memub(Re=#U6)
 let neverHasSideEffects = 1 in
 def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
-            (ins u6Imm:$addr),
+            (ins u6Ext:$addr),
             "$dst1 = memub($dst2=#$addr)",
             []>,
             Requires<[HasV4T]>;
@@ -334,7 +334,7 @@ def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 // Rd=memuh(Re=#U6)
 let neverHasSideEffects = 1 in
 def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
-            (ins u6Imm:$addr),
+            (ins u6Ext:$addr),
             "$dst1 = memuh($dst2=#$addr)",
             []>,
             Requires<[HasV4T]>;
@@ -342,7 +342,7 @@ def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 // Rd=memw(Re=#U6)
 let neverHasSideEffects = 1 in
 def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
-            (ins u6Imm:$addr),
+            (ins u6Ext:$addr),
             "$dst1 = memw($dst2=#$addr)",
             []>,
             Requires<[HasV4T]>;
@@ -351,7 +351,7 @@ def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 // instruction which take global address as operand.
 let neverHasSideEffects = 1 in
 def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
-            (ins globaladdress:$addr),
+            (ins globaladdressExt:$addr),
             "$dst1 = memd($dst2=##$addr)",
             []>,
             Requires<[HasV4T]>;
@@ -359,7 +359,7 @@ def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 // Rd=memb(Re=#U6)
 let neverHasSideEffects = 1 in
 def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
-            (ins globaladdress:$addr),
+            (ins globaladdressExt:$addr),
             "$dst1 = memb($dst2=##$addr)",
             []>,
             Requires<[HasV4T]>;
@@ -367,7 +367,7 @@ def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 // Rd=memh(Re=#U6)
 let neverHasSideEffects = 1 in
 def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
-            (ins globaladdress:$addr),
+            (ins globaladdressExt:$addr),
             "$dst1 = memh($dst2=##$addr)",
             []>,
             Requires<[HasV4T]>;
@@ -375,7 +375,7 @@ def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 // Rd=memub(Re=#U6)
 let neverHasSideEffects = 1 in
 def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
-            (ins globaladdress:$addr),
+            (ins globaladdressExt:$addr),
             "$dst1 = memub($dst2=##$addr)",
             []>,
             Requires<[HasV4T]>;
@@ -383,7 +383,7 @@ def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 // Rd=memuh(Re=#U6)
 let neverHasSideEffects = 1 in
 def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
-            (ins globaladdress:$addr),
+            (ins globaladdressExt:$addr),
             "$dst1 = memuh($dst2=##$addr)",
             []>,
             Requires<[HasV4T]>;
@@ -391,7 +391,7 @@ def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 // Rd=memw(Re=#U6)
 let neverHasSideEffects = 1 in
 def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
-            (ins globaladdress:$addr),
+            (ins globaladdressExt:$addr),
             "$dst1 = memw($dst2=##$addr)",
             []>,
             Requires<[HasV4T]>;
@@ -1749,56 +1749,56 @@ def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
 
 // memd(Re=#U6)=Rtt
 def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
-            (ins DoubleRegs:$src1, u6Imm:$src2),
+            (ins DoubleRegs:$src1, u6Ext:$src2),
             "memd($dst1=#$src2) = $src1",
             []>,
             Requires<[HasV4T]>;
 
 // memb(Re=#U6)=Rs
 def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
-            (ins IntRegs:$src1, u6Imm:$src2),
+            (ins IntRegs:$src1, u6Ext:$src2),
             "memb($dst1=#$src2) = $src1",
             []>,
             Requires<[HasV4T]>;
 
 // memh(Re=#U6)=Rs
 def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
-            (ins IntRegs:$src1, u6Imm:$src2),
+            (ins IntRegs:$src1, u6Ext:$src2),
             "memh($dst1=#$src2) = $src1",
             []>,
             Requires<[HasV4T]>;
 
 // memw(Re=#U6)=Rs
 def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
-            (ins IntRegs:$src1, u6Imm:$src2),
+            (ins IntRegs:$src1, u6Ext:$src2),
             "memw($dst1=#$src2) = $src1",
             []>,
             Requires<[HasV4T]>;
 
 // memd(Re=#U6)=Rtt
 def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
-            (ins DoubleRegs:$src1, globaladdress:$src2),
+            (ins DoubleRegs:$src1, globaladdressExt:$src2),
             "memd($dst1=##$src2) = $src1",
             []>,
             Requires<[HasV4T]>;
 
 // memb(Re=#U6)=Rs
 def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
-            (ins IntRegs:$src1, globaladdress:$src2),
+            (ins IntRegs:$src1, globaladdressExt:$src2),
             "memb($dst1=##$src2) = $src1",
             []>,
             Requires<[HasV4T]>;
 
 // memh(Re=#U6)=Rs
 def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
-            (ins IntRegs:$src1, globaladdress:$src2),
+            (ins IntRegs:$src1, globaladdressExt:$src2),
             "memh($dst1=##$src2) = $src1",
             []>,
             Requires<[HasV4T]>;
 
 // memw(Re=#U6)=Rs
 def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
-            (ins IntRegs:$src1, globaladdress:$src2),
+            (ins IntRegs:$src1, globaladdressExt:$src2),
             "memw($dst1=##$src2) = $src1",
             []>,
             Requires<[HasV4T]>;
@@ -1816,11 +1816,11 @@ def STrid_indexed_shl_V4 : STInst<(outs),
 // memd(Ru<<#u2+#U6)=Rtt
 let AddedComplexity = 10 in
 def STrid_shl_V4 : STInst<(outs),
-            (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),
+            (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, DoubleRegs:$src4),
             "memd($src1<<#$src2+#$src3) = $src4",
             [(store (i64 DoubleRegs:$src4),
                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
-                         u6ImmPred:$src3))]>,
+                         u6ExtPred:$src3))]>,
             Requires<[HasV4T]>;
 
 // memd(Rx++#s4:3)=Rtt
@@ -1860,7 +1860,7 @@ def STrid_cdnNotPt_V4 : STInst2<(outs),
 let AddedComplexity = 10, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrid_indexed_cdnPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
+            (ins PredRegs:$src1, IntRegs:$src2, u6_3Ext:$src3,
                  DoubleRegs:$src4),
             "if ($src1.new) memd($src2+#$src3) = $src4",
             []>,
@@ -1871,7 +1871,7 @@ def STrid_indexed_cdnPt_V4 : STInst2<(outs),
 let AddedComplexity = 10, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrid_indexed_cdnNotPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
+            (ins PredRegs:$src1, IntRegs:$src2, u6_3Ext:$src3,
                  DoubleRegs:$src4),
             "if (!$src1.new) memd($src2+#$src3) = $src4",
             []>,
@@ -1946,9 +1946,9 @@ def POST_STdri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
 // memb(Rs+#u6:0)=#S8
 let AddedComplexity = 10, isPredicable = 1 in
 def STrib_imm_V4 : STInst<(outs),
-            (ins IntRegs:$src1, u6_0Imm:$src2, s8Imm:$src3),
+            (ins IntRegs:$src1, u6_0Imm:$src2, s8Ext:$src3),
             "memb($src1+#$src2) = #$src3",
-            [(truncstorei8 s8ImmPred:$src3, (add (i32 IntRegs:$src1),
+            [(truncstorei8 s8ExtPred:$src3, (add (i32 IntRegs:$src1),
                                                  u6_0ImmPred:$src2))]>,
             Requires<[HasV4T]>;
 
@@ -1966,11 +1966,11 @@ def STrib_indexed_shl_V4 : STInst<(outs),
 // memb(Ru<<#u2+#U6)=Rt
 let AddedComplexity = 10 in
 def STrib_shl_V4 : STInst<(outs),
-            (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
+            (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
             "memb($src1<<#$src2+#$src3) = $src4",
             [(truncstorei8 (i32 IntRegs:$src4),
                            (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
-                                u6ImmPred:$src3))]>,
+                                u6ExtPred:$src3))]>,
             Requires<[HasV4T]>;
 
 // memb(Rx++#s4:0:circ(Mu))=Rt
@@ -1987,7 +1987,7 @@ def STrib_shl_V4 : STInst<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrib_imm_cPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Ext:$src4),
             "if ($src1) memb($src2+#$src3) = #$src4",
             []>,
             Requires<[HasV4T]>;
@@ -1996,7 +1996,7 @@ def STrib_imm_cPt_V4 : STInst2<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrib_imm_cdnPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Ext:$src4),
             "if ($src1.new) memb($src2+#$src3) = #$src4",
             []>,
             Requires<[HasV4T]>;
@@ -2005,7 +2005,7 @@ def STrib_imm_cdnPt_V4 : STInst2<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrib_imm_cNotPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Ext:$src4),
             "if (!$src1) memb($src2+#$src3) = #$src4",
             []>,
             Requires<[HasV4T]>;
@@ -2014,7 +2014,7 @@ def STrib_imm_cNotPt_V4 : STInst2<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrib_imm_cdnNotPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Ext:$src4),
             "if (!$src1.new) memb($src2+#$src3) = #$src4",
             []>,
             Requires<[HasV4T]>;
@@ -2046,7 +2046,7 @@ def STrib_cdnNotPt_V4 : STInst2<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrib_indexed_cdnPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3, IntRegs:$src4),
             "if ($src1.new) memb($src2+#$src3) = $src4",
             []>,
             Requires<[HasV4T]>;
@@ -2055,7 +2055,7 @@ def STrib_indexed_cdnPt_V4 : STInst2<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrib_indexed_cdnNotPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3, IntRegs:$src4),
             "if (!$src1.new) memb($src2+#$src3) = $src4",
             []>,
             Requires<[HasV4T]>;
@@ -2130,9 +2130,9 @@ def POST_STbri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
 // memh(Rs+#u6:1)=#S8
 let AddedComplexity = 10, isPredicable = 1 in
 def STrih_imm_V4 : STInst<(outs),
-            (ins IntRegs:$src1, u6_1Imm:$src2, s8Imm:$src3),
+            (ins IntRegs:$src1, u6_1Imm:$src2, s8Ext:$src3),
             "memh($src1+#$src2) = #$src3",
-            [(truncstorei16 s8ImmPred:$src3, (add (i32 IntRegs:$src1),
+            [(truncstorei16 s8ExtPred:$src3, (add (i32 IntRegs:$src1),
                                                   u6_1ImmPred:$src2))]>,
             Requires<[HasV4T]>;
 
@@ -2154,11 +2154,11 @@ def STrih_indexed_shl_V4 : STInst<(outs),
 // memh(Ru<<#u2+#U6)=Rt
 let AddedComplexity = 10 in
 def STrih_shl_V4 : STInst<(outs),
-            (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
+            (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
             "memh($src1<<#$src2+#$src3) = $src4",
             [(truncstorei16 (i32 IntRegs:$src4),
                             (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
-                                 u6ImmPred:$src3))]>,
+                                 u6ExtPred:$src3))]>,
             Requires<[HasV4T]>;
 
 // memh(Rx++#s4:1:circ(Mu))=Rt.H
@@ -2178,7 +2178,7 @@ def STrih_shl_V4 : STInst<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrih_imm_cPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Ext:$src4),
             "if ($src1) memh($src2+#$src3) = #$src4",
             []>,
             Requires<[HasV4T]>;
@@ -2187,7 +2187,7 @@ def STrih_imm_cPt_V4 : STInst2<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrih_imm_cdnPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Ext:$src4),
             "if ($src1.new) memh($src2+#$src3) = #$src4",
             []>,
             Requires<[HasV4T]>;
@@ -2196,7 +2196,7 @@ def STrih_imm_cdnPt_V4 : STInst2<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrih_imm_cNotPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Ext:$src4),
             "if (!$src1) memh($src2+#$src3) = #$src4",
             []>,
             Requires<[HasV4T]>;
@@ -2205,7 +2205,7 @@ def STrih_imm_cNotPt_V4 : STInst2<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrih_imm_cdnNotPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Ext:$src4),
             "if (!$src1.new) memh($src2+#$src3) = #$src4",
             []>,
             Requires<[HasV4T]>;
@@ -2238,7 +2238,7 @@ def STrih_cdnNotPt_V4 : STInst2<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrih_indexed_cdnPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3, IntRegs:$src4),
             "if ($src1.new) memh($src2+#$src3) = $src4",
             []>,
             Requires<[HasV4T]>;
@@ -2247,7 +2247,7 @@ def STrih_indexed_cdnPt_V4 : STInst2<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrih_indexed_cdnNotPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3, IntRegs:$src4),
             "if (!$src1.new) memh($src2+#$src3) = $src4",
             []>,
             Requires<[HasV4T]>;
@@ -2335,9 +2335,9 @@ def STriw_pred_V4 : STInst2<(outs),
 // memw(Rs+#u6:2)=#S8
 let AddedComplexity = 10, isPredicable = 1 in
 def STriw_imm_V4 : STInst<(outs),
-            (ins IntRegs:$src1, u6_2Imm:$src2, s8Imm:$src3),
+            (ins IntRegs:$src1, u6_2Imm:$src2, s8Ext:$src3),
             "memw($src1+#$src2) = #$src3",
-            [(store s8ImmPred:$src3, (add (i32 IntRegs:$src1),
+            [(store s8ExtPred:$src3, (add (i32 IntRegs:$src1),
                                           u6_2ImmPred:$src2))]>,
             Requires<[HasV4T]>;
 
@@ -2354,11 +2354,11 @@ def STriw_indexed_shl_V4 : STInst<(outs),
 // memw(Ru<<#u2+#U6)=Rt
 let AddedComplexity = 10 in
 def STriw_shl_V4 : STInst<(outs),
-            (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
+            (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
             "memw($src1<<#$src2+#$src3) = $src4",
             [(store (i32 IntRegs:$src4),
                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
-                              u6ImmPred:$src3))]>,
+                              u6ExtPred:$src3))]>,
             Requires<[HasV4T]>;
 
 // memw(Rx++#s4:2)=Rt
@@ -2376,7 +2376,7 @@ def STriw_shl_V4 : STInst<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STriw_imm_cPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Ext:$src4),
             "if ($src1) memw($src2+#$src3) = #$src4",
             []>,
             Requires<[HasV4T]>;
@@ -2385,7 +2385,7 @@ def STriw_imm_cPt_V4 : STInst2<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STriw_imm_cdnPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Ext:$src4),
             "if ($src1.new) memw($src2+#$src3) = #$src4",
             []>,
             Requires<[HasV4T]>;
@@ -2394,7 +2394,7 @@ def STriw_imm_cdnPt_V4 : STInst2<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STriw_imm_cNotPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Ext:$src4),
             "if (!$src1) memw($src2+#$src3) = #$src4",
             []>,
             Requires<[HasV4T]>;
@@ -2403,7 +2403,7 @@ def STriw_imm_cNotPt_V4 : STInst2<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STriw_imm_cdnNotPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Ext:$src4),
             "if (!$src1.new) memw($src2+#$src3) = #$src4",
             []>,
             Requires<[HasV4T]>;
@@ -2435,7 +2435,7 @@ def STriw_cdnNotPt_V4 : STInst2<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STriw_indexed_cdnPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3, IntRegs:$src4),
             "if ($src1.new) memw($src2+#$src3) = $src4",
             []>,
             Requires<[HasV4T]>;
@@ -2444,7 +2444,7 @@ def STriw_indexed_cdnPt_V4 : STInst2<(outs),
 let neverHasSideEffects = 1,
     isPredicated = 1 in
 def STriw_indexed_cdnNotPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3, IntRegs:$src4),
             "if (!$src1.new) memw($src2+#$src3) = $src4",
             []>,
             Requires<[HasV4T]>;
@@ -2974,7 +2974,7 @@ def STrib_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
 
 let mayStore = 1, isPredicable = 1 in
 def STrib_indexed_nv_V4 : NVInst_V4<(outs),
-            (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
+            (ins IntRegs:$src1, s11_0Ext:$src2, IntRegs:$src3),
             "memb($src1+#$src2) = $src3.new",
             []>,
             Requires<[HasV4T]>;
@@ -2990,7 +2990,7 @@ def STrib_indexed_shl_nv_V4 : NVInst_V4<(outs),
 // memb(Ru<<#u2+#U6)=Nt.new
 let mayStore = 1, AddedComplexity = 10 in
 def STrib_shl_nv_V4 : NVInst_V4<(outs),
-            (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
+            (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
             "memb($src1<<#$src2+#$src3) = $src4.new",
             []>,
             Requires<[HasV4T]>;
@@ -3067,7 +3067,7 @@ def STrib_cdnNotPt_nv_V4 : NVInst_V4<(outs),
 let mayStore = 1, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrib_indexed_cPt_nv_V4 : NVInst_V4<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3, IntRegs:$src4),
             "if ($src1) memb($src2+#$src3) = $src4.new",
             []>,
             Requires<[HasV4T]>;
@@ -3076,7 +3076,7 @@ def STrib_indexed_cPt_nv_V4 : NVInst_V4<(outs),
 let mayStore = 1, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrib_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3, IntRegs:$src4),
             "if ($src1.new) memb($src2+#$src3) = $src4.new",
             []>,
             Requires<[HasV4T]>;
@@ -3085,7 +3085,7 @@ def STrib_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
 let mayStore = 1, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrib_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3, IntRegs:$src4),
             "if (!$src1) memb($src2+#$src3) = $src4.new",
             []>,
             Requires<[HasV4T]>;
@@ -3094,7 +3094,7 @@ def STrib_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
 let mayStore = 1, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrib_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_0Ext:$src3, IntRegs:$src4),
             "if (!$src1.new) memb($src2+#$src3) = $src4.new",
             []>,
             Requires<[HasV4T]>;
@@ -3190,7 +3190,7 @@ def STrih_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
 
 let mayStore = 1, isPredicable = 1 in
 def STrih_indexed_nv_V4 : NVInst_V4<(outs),
-            (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
+            (ins IntRegs:$src1, s11_1Ext:$src2, IntRegs:$src3),
             "memh($src1+#$src2) = $src3.new",
             []>,
             Requires<[HasV4T]>;
@@ -3206,7 +3206,7 @@ def STrih_indexed_shl_nv_V4 : NVInst_V4<(outs),
 // memh(Ru<<#u2+#U6)=Nt.new
 let mayStore = 1, AddedComplexity = 10 in
 def STrih_shl_nv_V4 : NVInst_V4<(outs),
-            (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
+            (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
             "memh($src1<<#$src2+#$src3) = $src4.new",
             []>,
             Requires<[HasV4T]>;
@@ -3287,7 +3287,7 @@ def STrih_cdnNotPt_nv_V4 : NVInst_V4<(outs),
 let mayStore = 1, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrih_indexed_cPt_nv_V4 : NVInst_V4<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3, IntRegs:$src4),
             "if ($src1) memh($src2+#$src3) = $src4.new",
             []>,
             Requires<[HasV4T]>;
@@ -3296,7 +3296,7 @@ def STrih_indexed_cPt_nv_V4 : NVInst_V4<(outs),
 let mayStore = 1, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrih_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3, IntRegs:$src4),
             "if ($src1.new) memh($src2+#$src3) = $src4.new",
             []>,
             Requires<[HasV4T]>;
@@ -3305,7 +3305,7 @@ def STrih_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
 let mayStore = 1, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrih_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3, IntRegs:$src4),
             "if (!$src1) memh($src2+#$src3) = $src4.new",
             []>,
             Requires<[HasV4T]>;
@@ -3314,7 +3314,7 @@ def STrih_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
 let mayStore = 1, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STrih_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_1Ext:$src3, IntRegs:$src4),
             "if (!$src1.new) memh($src2+#$src3) = $src4.new",
             []>,
             Requires<[HasV4T]>;
@@ -3411,7 +3411,7 @@ def STriw_nv_V4 : NVInst_V4<(outs),
 
 let mayStore = 1, isPredicable = 1 in
 def STriw_indexed_nv_V4 : NVInst_V4<(outs),
-            (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
+            (ins IntRegs:$src1, s11_2Ext:$src2, IntRegs:$src3),
             "memw($src1+#$src2) = $src3.new",
             []>,
             Requires<[HasV4T]>;
@@ -3427,7 +3427,7 @@ def STriw_indexed_shl_nv_V4 : NVInst_V4<(outs),
 // memw(Ru<<#u2+#U6)=Nt.new
 let mayStore = 1, AddedComplexity = 10 in
 def STriw_shl_nv_V4 : NVInst_V4<(outs),
-            (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
+            (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
             "memw($src1<<#$src2+#$src3) = $src4.new",
             []>,
             Requires<[HasV4T]>;
@@ -3505,7 +3505,7 @@ def STriw_cdnNotPt_nv_V4 : NVInst_V4<(outs),
 let mayStore = 1, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STriw_indexed_cPt_nv_V4 : NVInst_V4<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3, IntRegs:$src4),
             "if ($src1) memw($src2+#$src3) = $src4.new",
             []>,
             Requires<[HasV4T]>;
@@ -3514,7 +3514,7 @@ def STriw_indexed_cPt_nv_V4 : NVInst_V4<(outs),
 let mayStore = 1, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STriw_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3, IntRegs:$src4),
             "if ($src1.new) memw($src2+#$src3) = $src4.new",
             []>,
             Requires<[HasV4T]>;
@@ -3523,7 +3523,7 @@ def STriw_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
 let mayStore = 1, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STriw_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3, IntRegs:$src4),
             "if (!$src1) memw($src2+#$src3) = $src4.new",
             []>,
             Requires<[HasV4T]>;
@@ -3532,7 +3532,7 @@ def STriw_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
 let mayStore = 1, neverHasSideEffects = 1,
     isPredicated = 1 in
 def STriw_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
-            (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
+            (ins PredRegs:$src1, IntRegs:$src2, u6_2Ext:$src3, IntRegs:$src4),
             "if (!$src1.new) memw($src2+#$src3) = $src4.new",
             []>,
             Requires<[HasV4T]>;
@@ -3999,19 +3999,19 @@ let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
 //  Add and accumulate.
 //  Rd=add(Rs,add(Ru,#s6))
 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
-          (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
+          (ins IntRegs:$src1, IntRegs:$src2, s6Ext:$src3),
           "$dst = add($src1, add($src2, #$src3))",
           [(set (i32 IntRegs:$dst),
            (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
-                                          s6ImmPred:$src3)))]>,
+                                          s6_16ExtPred:$src3)))]>,
           Requires<[HasV4T]>;
 
 //  Rd=add(Rs,sub(#s6,Ru))
 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
-          (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
+          (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
           "$dst = add($src1, sub(#$src2, $src3))",
           [(set (i32 IntRegs:$dst),
-           (add (i32 IntRegs:$src1), (sub s6ImmPred:$src2,
+           (add (i32 IntRegs:$src1), (sub s6_10ExtPred:$src2,
                                           (i32 IntRegs:$src3))))]>,
           Requires<[HasV4T]>;
 
@@ -4019,10 +4019,10 @@ def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
 // pattern.
 //  Rd=add(Rs,sub(#s6,Ru))
 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
-          (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
+          (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
           "$dst = add($src1, sub(#$src2, $src3))",
           [(set (i32 IntRegs:$dst),
-                (sub (add (i32 IntRegs:$src1), s6ImmPred:$src2),
+                (sub (add (i32 IntRegs:$src1), s6_10ExtPred:$src2),
                      (i32 IntRegs:$src3)))]>,
           Requires<[HasV4T]>;
 
@@ -4067,11 +4067,11 @@ def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
 // Logical-logical words.
 // Rx=or(Ru,and(Rx,#s10))
 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
+            (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
             "$dst = or($src1, and($src2, #$src3))",
             [(set (i32 IntRegs:$dst),
                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
-                                                s10ImmPred:$src3)))],
+                                                s10ExtPred:$src3)))],
             "$src2 = $dst">,
             Requires<[HasV4T]>;
 
@@ -4201,21 +4201,21 @@ def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
 
 // Rx|=and(Rs,#s10)
 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
+            (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
             "$dst |= and($src2, #$src3)",
             [(set (i32 IntRegs:$dst),
                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
-                                                s10ImmPred:$src3)))],
+                                                s10ExtPred:$src3)))],
             "$src1 = $dst">,
             Requires<[HasV4T]>;
 
 // Rx|=or(Rs,#s10)
 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
+            (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
             "$dst |= or($src2, #$src3)",
             [(set (i32 IntRegs:$dst),
                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
-                                                s10ImmPred:$src3)))],
+                                                s10ExtPred:$src3)))],
             "$src1 = $dst">,
             Requires<[HasV4T]>;
 
@@ -4265,21 +4265,21 @@ def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
 // Multiply and user lower result.
 // Rd=add(#u6,mpyi(Rs,#U6))
 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
-            (ins u6Imm:$src1, IntRegs:$src2, u6Imm:$src3),
+            (ins u6Ext:$src1, IntRegs:$src2, u6Imm:$src3),
             "$dst = add(#$src1, mpyi($src2, #$src3))",
             [(set (i32 IntRegs:$dst),
                   (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
-                       u6ImmPred:$src1))]>,
+                       u6ExtPred:$src1))]>,
             Requires<[HasV4T]>;
 
 // Rd=add(#u6,mpyi(Rs,Rt))
 
 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
-            (ins u6Imm:$src1, IntRegs:$src2, IntRegs:$src3),
+            (ins u6Ext:$src1, IntRegs:$src2, IntRegs:$src3),
             "$dst = add(#$src1, mpyi($src2, $src3))",
             [(set (i32 IntRegs:$dst),
                   (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
-                       u6ImmPred:$src1))]>,
+                       u6ExtPred:$src1))]>,
             Requires<[HasV4T]>;
 
 // Rd=add(Ru,mpyi(#u6:2,Rs))
@@ -4293,11 +4293,11 @@ def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
 
 // Rd=add(Ru,mpyi(Rs,#u6))
 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, IntRegs:$src2, u6Imm:$src3),
+            (ins IntRegs:$src1, IntRegs:$src2, u6Ext:$src3),
             "$dst = add($src1, mpyi($src2, #$src3))",
             [(set (i32 IntRegs:$dst),
                   (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
-                                                 u6ImmPred:$src3)))]>,
+                                                 u6ExtPred:$src3)))]>,
             Requires<[HasV4T]>;
 
 // Rx=add(Ru,mpyi(Rx,Rs))
@@ -4352,41 +4352,41 @@ def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
 // Shift by immediate and accumulate.
 // Rx=add(#u8,asl(Rx,#U5))
 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
-            (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
+            (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
             "$dst = add(#$src1, asl($src2, #$src3))",
             [(set (i32 IntRegs:$dst),
                   (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
-                       u8ImmPred:$src1))],
+                       u8ExtPred:$src1))],
             "$src2 = $dst">,
             Requires<[HasV4T]>;
 
 // Rx=add(#u8,lsr(Rx,#U5))
 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
-            (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
+            (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
             "$dst = add(#$src1, lsr($src2, #$src3))",
             [(set (i32 IntRegs:$dst),
                   (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
-                       u8ImmPred:$src1))],
+                       u8ExtPred:$src1))],
             "$src2 = $dst">,
             Requires<[HasV4T]>;
 
 // Rx=sub(#u8,asl(Rx,#U5))
 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
-            (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
+            (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
             "$dst = sub(#$src1, asl($src2, #$src3))",
             [(set (i32 IntRegs:$dst),
                   (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
-                       u8ImmPred:$src1))],
+                       u8ExtPred:$src1))],
             "$src2 = $dst">,
             Requires<[HasV4T]>;
 
 // Rx=sub(#u8,lsr(Rx,#U5))
 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
-            (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
+            (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
             "$dst = sub(#$src1, lsr($src2, #$src3))",
             [(set (i32 IntRegs:$dst),
                   (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
-                       u8ImmPred:$src1))],
+                       u8ExtPred:$src1))],
             "$src2 = $dst">,
             Requires<[HasV4T]>;
 
@@ -4394,43 +4394,43 @@ def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
 //Shift by immediate and logical.
 //Rx=and(#u8,asl(Rx,#U5))
 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
-            (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
+            (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
             "$dst = and(#$src1, asl($src2, #$src3))",
             [(set (i32 IntRegs:$dst),
                   (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
-                       u8ImmPred:$src1))],
+                       u8ExtPred:$src1))],
             "$src2 = $dst">,
             Requires<[HasV4T]>;
 
 //Rx=and(#u8,lsr(Rx,#U5))
 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
-            (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
+            (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
             "$dst = and(#$src1, lsr($src2, #$src3))",
             [(set (i32 IntRegs:$dst),
                   (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
-                       u8ImmPred:$src1))],
+                       u8ExtPred:$src1))],
             "$src2 = $dst">,
             Requires<[HasV4T]>;
 
 //Rx=or(#u8,asl(Rx,#U5))
 let AddedComplexity = 30 in
 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
-            (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
+            (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
             "$dst = or(#$src1, asl($src2, #$src3))",
             [(set (i32 IntRegs:$dst),
                   (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
-                      u8ImmPred:$src1))],
+                      u8ExtPred:$src1))],
             "$src2 = $dst">,
             Requires<[HasV4T]>;
 
 //Rx=or(#u8,lsr(Rx,#U5))
 let AddedComplexity = 30 in
 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
-            (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
+            (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
             "$dst = or(#$src1, lsr($src2, #$src3))",
             [(set (i32 IntRegs:$dst),
                   (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
-                      u8ImmPred:$src1))],
+                      u8ExtPred:$src1))],
             "$src2 = $dst">,
             Requires<[HasV4T]>;
 
@@ -4535,7 +4535,7 @@ def MEMw_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
 // memw(Rs+#u6:2) += #U5
 let AddedComplexity = 30 in
 def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
-            (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend),
+            (ins IntRegs:$base, u6_2Ext:$offset, u5Imm:$addend),
             "memw($base+#$offset) += #$addend",
             []>,
             Requires<[HasV4T, UseMEMOP]>;
@@ -4543,7 +4543,7 @@ def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
 // memw(Rs+#u6:2) -= #U5
 let AddedComplexity = 30 in
 def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
-            (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend),
+            (ins IntRegs:$base, u6_2Ext:$offset, u5Imm:$subend),
             "memw($base+#$offset) -= #$subend",
             []>,
             Requires<[HasV4T, UseMEMOP]>;
@@ -4551,9 +4551,9 @@ def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
 // memw(Rs+#u6:2) += Rt
 let AddedComplexity = 30 in
 def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
-            (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend),
+            (ins IntRegs:$base, u6_2Ext:$offset, IntRegs:$addend),
             "memw($base+#$offset) += $addend",
-            [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
+            [(store (add (load (add (i32 IntRegs:$base), u6_2ExtPred:$offset)),
                          (i32 IntRegs:$addend)),
                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
             Requires<[HasV4T, UseMEMOP]>;
@@ -4561,9 +4561,9 @@ def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
 // memw(Rs+#u6:2) -= Rt
 let AddedComplexity = 30 in
 def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
-            (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend),
+            (ins IntRegs:$base, u6_2Ext:$offset, IntRegs:$subend),
             "memw($base+#$offset) -= $subend",
-            [(store (sub (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
+            [(store (sub (load (add (i32 IntRegs:$base), u6_2ExtPred:$offset)),
                          (i32 IntRegs:$subend)),
                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
             Requires<[HasV4T, UseMEMOP]>;
@@ -4571,9 +4571,9 @@ def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
 // memw(Rs+#u6:2) &= Rt
 let AddedComplexity = 30 in
 def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
-            (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend),
+            (ins IntRegs:$base, u6_2Ext:$offset, IntRegs:$andend),
             "memw($base+#$offset) &= $andend",
-            [(store (and (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
+            [(store (and (load (add (i32 IntRegs:$base), u6_2ExtPred:$offset)),
                          (i32 IntRegs:$andend)),
                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
             Requires<[HasV4T, UseMEMOP]>;
@@ -4581,9 +4581,9 @@ def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
 // memw(Rs+#u6:2) |= Rt
 let AddedComplexity = 30 in
 def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
-            (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend),
+            (ins IntRegs:$base, u6_2Ext:$offset, IntRegs:$orend),
             "memw($base+#$offset) |= $orend",
-            [(store (or (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
+            [(store (or (load (add (i32 IntRegs:$base), u6_2ExtPred:$offset)),
                         (i32 IntRegs:$orend)),
                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
             Requires<[HasV4T, UseMEMOP]>;
@@ -5033,10 +5033,10 @@ def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
 // Pd=cmpb.gtu(Rs,#u7)
 let isCompare = 1 in
 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
-            (ins IntRegs:$src1, u7Imm:$src2),
+            (ins IntRegs:$src1, u7Ext:$src2),
             "$dst = cmpb.gtu($src1, #$src2)",
             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
-                                              u7ImmPred:$src2))]>,
+                                              u7ExtPred:$src2))]>,
             Requires<[HasV4T]>;
 
 // Pd=cmpb.gtu(Rs,Rt)
@@ -5051,6 +5051,9 @@ def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
 // Following instruction is not being extended as it results into the incorrect
 // code for negative numbers.
 
+// Following instruction is not being extended as it results into the incorrect
+// code for negative numbers.
+
 // Signed half compare(.eq) ri.
 // Pd=cmph.eq(Rs,#s8)
 let isCompare = 1 in
@@ -5098,11 +5101,11 @@ used in the cmph.gt instruction.
 
 let isCompare = 1 in
 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
-            (ins IntRegs:$src1, s8Imm:$src2),
+            (ins IntRegs:$src1, s8Ext:$src2),
             "$dst = cmph.gt($src1, #$src2)",
             [(set (i1 PredRegs:$dst),
                   (setgt (shl (i32 IntRegs:$src1), (i32 16)),
-                         s8ImmPred:$src2))]>,
+                         s8ExtPred:$src2))]>,
             Requires<[HasV4T]>;
 */
 
@@ -5132,10 +5135,10 @@ def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
 // Pd=cmph.gtu(Rs,#u7)
 let isCompare = 1 in
 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
-            (ins IntRegs:$src1, u7Imm:$src2),
+            (ins IntRegs:$src1, u7Ext:$src2),
             "$dst = cmph.gtu($src1, #$src2)",
             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
-                                              u7ImmPred:$src2))]>,
+                                              u7ExtPred:$src2))]>,
             Requires<[HasV4T]>;
 
 //===----------------------------------------------------------------------===//
@@ -5255,14 +5258,14 @@ let isReturn = 1, isTerminator = 1,
 multiclass ST_abs<string OpcStr> {
   let isPredicable = 1 in
   def _abs_V4 : STInst2<(outs),
-            (ins globaladdress:$absaddr, IntRegs:$src),
+            (ins globaladdressExt:$absaddr, IntRegs:$src),
             !strconcat(OpcStr, "(##$absaddr) = $src"),
             []>,
             Requires<[HasV4T]>;
 
   let isPredicated = 1 in
   def _abs_cPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
+            (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
             !strconcat("if ($src1)",
             !strconcat(OpcStr, "(##$absaddr) = $src2")),
             []>,
@@ -5270,7 +5273,7 @@ multiclass ST_abs<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cNotPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
+            (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
             !strconcat("if (!$src1)",
             !strconcat(OpcStr, "(##$absaddr) = $src2")),
             []>,
@@ -5278,7 +5281,7 @@ multiclass ST_abs<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cdnPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
+            (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
             !strconcat("if ($src1.new)",
             !strconcat(OpcStr, "(##$absaddr) = $src2")),
             []>,
@@ -5286,21 +5289,21 @@ multiclass ST_abs<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cdnNotPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
+            (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
             !strconcat("if (!$src1.new)",
             !strconcat(OpcStr, "(##$absaddr) = $src2")),
             []>,
             Requires<[HasV4T]>;
 
   def _abs_nv_V4 : STInst2<(outs),
-            (ins globaladdress:$absaddr, IntRegs:$src),
+            (ins globaladdressExt:$absaddr, IntRegs:$src),
             !strconcat(OpcStr, "(##$absaddr) = $src.new"),
             []>,
             Requires<[HasV4T]>;
 
   let isPredicated = 1 in
   def _abs_cPt_nv_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
+            (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
             !strconcat("if ($src1)",
             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
             []>,
@@ -5308,7 +5311,7 @@ multiclass ST_abs<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cNotPt_nv_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
+            (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
             !strconcat("if (!$src1)",
             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
             []>,
@@ -5316,7 +5319,7 @@ multiclass ST_abs<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cdnPt_nv_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
+            (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
             !strconcat("if ($src1.new)",
             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
             []>,
@@ -5324,7 +5327,7 @@ multiclass ST_abs<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
+            (ins PredRegs:$src1, globaladdressExt:$absaddr, IntRegs:$src2),
             !strconcat("if (!$src1.new)",
             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
             []>,
@@ -5333,7 +5336,7 @@ multiclass ST_abs<string OpcStr> {
 
 let AddedComplexity = 30, isPredicable = 1 in
 def STrid_abs_V4 : STInst<(outs),
-          (ins globaladdress:$absaddr, DoubleRegs:$src),
+          (ins globaladdressExt:$absaddr, DoubleRegs:$src),
            "memd(##$absaddr) = $src",
           [(store (i64 DoubleRegs:$src),
                   (HexagonCONST32 tglobaladdr:$absaddr))]>,
@@ -5341,28 +5344,28 @@ def STrid_abs_V4 : STInst<(outs),
 
 let AddedComplexity = 30, isPredicated = 1 in
 def STrid_abs_cPt_V4 : STInst2<(outs),
-          (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
+          (ins PredRegs:$src1, globaladdressExt:$absaddr, DoubleRegs:$src2),
           "if ($src1) memd(##$absaddr) = $src2",
           []>,
           Requires<[HasV4T]>;
 
 let AddedComplexity = 30, isPredicated = 1 in
 def STrid_abs_cNotPt_V4 : STInst2<(outs),
-          (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
+          (ins PredRegs:$src1, globaladdressExt:$absaddr, DoubleRegs:$src2),
           "if (!$src1) memd(##$absaddr) = $src2",
           []>,
           Requires<[HasV4T]>;
 
 let AddedComplexity = 30, isPredicated = 1 in
 def STrid_abs_cdnPt_V4 : STInst2<(outs),
-          (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
+          (ins PredRegs:$src1, globaladdressExt:$absaddr, DoubleRegs:$src2),
           "if ($src1.new) memd(##$absaddr) = $src2",
           []>,
           Requires<[HasV4T]>;
 
 let AddedComplexity = 30, isPredicated = 1 in
 def STrid_abs_cdnNotPt_V4 : STInst2<(outs),
-          (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
+          (ins PredRegs:$src1, globaladdressExt:$absaddr, DoubleRegs:$src2),
           "if (!$src1.new) memd(##$absaddr) = $src2",
           []>,
           Requires<[HasV4T]>;
@@ -5389,14 +5392,14 @@ def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
 multiclass LD_abs<string OpcStr> {
   let isPredicable = 1 in
   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
-            (ins globaladdress:$absaddr),
+            (ins globaladdressExt:$absaddr),
             !strconcat("$dst = ", !strconcat(OpcStr, "(##$absaddr)")),
             []>,
             Requires<[HasV4T]>;
 
   let isPredicated = 1 in
   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, globaladdress:$absaddr),
+            (ins PredRegs:$src1, globaladdressExt:$absaddr),
             !strconcat("if ($src1) $dst = ",
             !strconcat(OpcStr, "(##$absaddr)")),
             []>,
@@ -5404,7 +5407,7 @@ multiclass LD_abs<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, globaladdress:$absaddr),
+            (ins PredRegs:$src1, globaladdressExt:$absaddr),
             !strconcat("if (!$src1) $dst = ",
             !strconcat(OpcStr, "(##$absaddr)")),
             []>,
@@ -5412,7 +5415,7 @@ multiclass LD_abs<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, globaladdress:$absaddr),
+            (ins PredRegs:$src1, globaladdressExt:$absaddr),
             !strconcat("if ($src1.new) $dst = ",
             !strconcat(OpcStr, "(##$absaddr)")),
             []>,
@@ -5420,7 +5423,7 @@ multiclass LD_abs<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, globaladdress:$absaddr),
+            (ins PredRegs:$src1, globaladdressExt:$absaddr),
             !strconcat("if (!$src1.new) $dst = ",
             !strconcat(OpcStr, "(##$absaddr)")),
             []>,
@@ -5429,7 +5432,7 @@ multiclass LD_abs<string OpcStr> {
 
 let AddedComplexity = 30 in
 def LDrid_abs_V4 : LDInst<(outs DoubleRegs:$dst),
-          (ins globaladdress:$absaddr),
+          (ins globaladdressExt:$absaddr),
           "$dst = memd(##$absaddr)",
           [(set (i64 DoubleRegs:$dst),
                 (load (HexagonCONST32 tglobaladdr:$absaddr)))]>,
@@ -5437,28 +5440,28 @@ def LDrid_abs_V4 : LDInst<(outs DoubleRegs:$dst),
 
 let AddedComplexity = 30, isPredicated = 1 in
 def LDrid_abs_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
-          (ins PredRegs:$src1, globaladdress:$absaddr),
+          (ins PredRegs:$src1, globaladdressExt:$absaddr),
           "if ($src1) $dst = memd(##$absaddr)",
           []>,
           Requires<[HasV4T]>;
 
 let AddedComplexity = 30, isPredicated = 1 in
 def LDrid_abs_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
-          (ins PredRegs:$src1, globaladdress:$absaddr),
+          (ins PredRegs:$src1, globaladdressExt:$absaddr),
           "if (!$src1) $dst = memd(##$absaddr)",
           []>,
           Requires<[HasV4T]>;
 
 let AddedComplexity = 30, isPredicated = 1 in
 def LDrid_abs_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
-          (ins PredRegs:$src1, globaladdress:$absaddr),
+          (ins PredRegs:$src1, globaladdressExt:$absaddr),
           "if ($src1.new) $dst = memd(##$absaddr)",
           []>,
           Requires<[HasV4T]>;
 
 let AddedComplexity = 30, isPredicated = 1 in
 def LDrid_abs_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
-          (ins PredRegs:$src1, globaladdress:$absaddr),
+          (ins PredRegs:$src1, globaladdressExt:$absaddr),
           "if (!$src1.new) $dst = memd(##$absaddr)",
           []>,
           Requires<[HasV4T]>;
@@ -5492,35 +5495,35 @@ def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
 
 // Transfer global address into a register
 let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
-def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
+def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdressExt:$src1),
            "$dst = ##$src1",
            [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
            Requires<[HasV4T]>;
 
 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
-                           (ins PredRegs:$src1, globaladdress:$src2),
+                           (ins PredRegs:$src1, globaladdressExt:$src2),
            "if($src1) $dst = ##$src2",
            []>,
            Requires<[HasV4T]>;
 
 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
-                              (ins PredRegs:$src1, globaladdress:$src2),
+                              (ins PredRegs:$src1, globaladdressExt:$src2),
            "if(!$src1) $dst = ##$src2",
            []>,
            Requires<[HasV4T]>;
 
 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
-                             (ins PredRegs:$src1, globaladdress:$src2),
+                             (ins PredRegs:$src1, globaladdressExt:$src2),
            "if($src1.new) $dst = ##$src2",
            []>,
            Requires<[HasV4T]>;
 
 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
-                                (ins PredRegs:$src1, globaladdress:$src2),
+                                (ins PredRegs:$src1, globaladdressExt:$src2),
            "if(!$src1.new) $dst = ##$src2",
            []>,
            Requires<[HasV4T]>;
@@ -5534,7 +5537,7 @@ def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
 // as an operand
 let AddedComplexity = 10 in
 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
-            (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
+            (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
             "$dst=memd($src1<<#$src2+##$offset)",
             [(set (i64 DoubleRegs:$dst),
                   (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
@@ -5544,7 +5547,7 @@ def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
 let AddedComplexity = 10 in
 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
   def _lo_V4 : LDInst<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
+            (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
             !strconcat("$dst = ",
             !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
             [(set IntRegs:$dst,
@@ -5563,7 +5566,7 @@ defm LDriw_ind : LD_indirect_lo<"memw", load>;
 // as an operand
 let AddedComplexity = 10 in
 def STrid_ind_lo_V4 : STInst<(outs),
-            (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
+            (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$src3,
                  DoubleRegs:$src4),
             "memd($src1<<#$src2+#$src3) = $src4",
             [(store (i64 DoubleRegs:$src4),
@@ -5574,7 +5577,7 @@ def STrid_ind_lo_V4 : STInst<(outs),
 let AddedComplexity = 10 in
 multiclass ST_indirect_lo<string OpcStr, PatFrag OpNode> {
   def _lo_V4 : STInst<(outs),
-            (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
+            (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$src3,
                  IntRegs:$src4),
             !strconcat(OpcStr, "($src1<<#$src2+##$src3) = $src4"),
             [(OpNode (i32 IntRegs:$src4),
@@ -5592,28 +5595,28 @@ defm STriw_ind : ST_indirect_lo<"memw", store>;
 multiclass ST_absimm<string OpcStr> {
   let isPredicable = 1 in
   def _abs_V4 : STInst2<(outs),
-            (ins u6Imm:$src1, IntRegs:$src2),
+            (ins u6Ext:$src1, IntRegs:$src2),
             !strconcat(OpcStr, "(#$src1) = $src2"),
             []>,
             Requires<[HasV4T]>;
 
   let isPredicated = 1 in
   def _abs_cPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
+            (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
             !strconcat("if ($src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
             []>,
             Requires<[HasV4T]>;
 
   let isPredicated = 1 in
   def _abs_cNotPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
+            (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
             !strconcat("if (!$src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
             []>,
             Requires<[HasV4T]>;
 
   let isPredicated = 1 in
   def _abs_cdnPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
+            (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
             !strconcat("if ($src1.new)",
             !strconcat(OpcStr, "(#$src2) = $src3")),
             []>,
@@ -5621,21 +5624,21 @@ multiclass ST_absimm<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cdnNotPt_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
+            (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
             !strconcat("if (!$src1.new)",
             !strconcat(OpcStr, "(#$src2) = $src3")),
             []>,
             Requires<[HasV4T]>;
 
   def _abs_nv_V4 : STInst2<(outs),
-            (ins u6Imm:$src1, IntRegs:$src2),
+            (ins u6Ext:$src1, IntRegs:$src2),
             !strconcat(OpcStr, "(#$src1) = $src2.new"),
             []>,
             Requires<[HasV4T]>;
 
   let isPredicated = 1 in
   def _abs_cPt_nv_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
+            (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
             !strconcat("if ($src1)",
             !strconcat(OpcStr, "(#$src2) = $src3.new")),
             []>,
@@ -5643,7 +5646,7 @@ multiclass ST_absimm<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cNotPt_nv_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
+            (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
             !strconcat("if (!$src1)",
             !strconcat(OpcStr, "(#$src2) = $src3.new")),
             []>,
@@ -5651,7 +5654,7 @@ multiclass ST_absimm<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cdnPt_nv_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
+            (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
             !strconcat("if ($src1.new)",
             !strconcat(OpcStr, "(#$src2) = $src3.new")),
             []>,
@@ -5659,7 +5662,7 @@ multiclass ST_absimm<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
-            (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
+            (ins PredRegs:$src1, u6Ext:$src2, IntRegs:$src3),
             !strconcat("if (!$src1.new)",
             !strconcat(OpcStr, "(#$src2) = $src3.new")),
             []>,
@@ -5671,16 +5674,16 @@ defm STrih_imm : ST_absimm<"memh">;
 defm STriw_imm : ST_absimm<"memw">;
 
 let Predicates = [HasV4T], AddedComplexity  = 30 in
-def : Pat<(truncstorei8 (i32 IntRegs:$src1), u6ImmPred:$src2),
-          (STrib_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
+def : Pat<(truncstorei8 (i32 IntRegs:$src1), u6ExtPred:$src2),
+          (STrib_imm_abs_V4 u6ExtPred:$src2, IntRegs: $src1)>;
 
 let Predicates = [HasV4T], AddedComplexity  = 30 in
-def : Pat<(truncstorei16 (i32 IntRegs:$src1), u6ImmPred:$src2),
-          (STrih_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
+def : Pat<(truncstorei16 (i32 IntRegs:$src1), u6ExtPred:$src2),
+          (STrih_imm_abs_V4 u6ExtPred:$src2, IntRegs: $src1)>;
 
 let Predicates = [HasV4T], AddedComplexity  = 30 in
-def : Pat<(store (i32 IntRegs:$src1), u6ImmPred:$src2),
-          (STriw_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
+def : Pat<(store (i32 IntRegs:$src1), u6ExtPred:$src2),
+          (STriw_imm_abs_V4 u6ExtPred:$src2, IntRegs: $src1)>;
 
 
 // Load - absolute addressing mode: These instruction take constant
@@ -5689,7 +5692,7 @@ def : Pat<(store (i32 IntRegs:$src1), u6ImmPred:$src2),
 multiclass LD_absimm<string OpcStr> {
   let isPredicable = 1 in
   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
-            (ins u6Imm:$src),
+            (ins u6Ext:$src),
             !strconcat("$dst = ",
             !strconcat(OpcStr, "(#$src)")),
             []>,
@@ -5697,7 +5700,7 @@ multiclass LD_absimm<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, u6Imm:$src2),
+            (ins PredRegs:$src1, u6Ext:$src2),
             !strconcat("if ($src1) $dst = ",
             !strconcat(OpcStr, "(#$src2)")),
             []>,
@@ -5705,7 +5708,7 @@ multiclass LD_absimm<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, u6Imm:$src2),
+            (ins PredRegs:$src1, u6Ext:$src2),
             !strconcat("if (!$src1) $dst = ",
             !strconcat(OpcStr, "(#$src2)")),
             []>,
@@ -5713,7 +5716,7 @@ multiclass LD_absimm<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, u6Imm:$src2),
+            (ins PredRegs:$src1, u6Ext:$src2),
             !strconcat("if ($src1.new) $dst = ",
             !strconcat(OpcStr, "(#$src2)")),
             []>,
@@ -5721,7 +5724,7 @@ multiclass LD_absimm<string OpcStr> {
 
   let isPredicated = 1 in
   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
-            (ins PredRegs:$src1, u6Imm:$src2),
+            (ins PredRegs:$src1, u6Ext:$src2),
             !strconcat("if (!$src1.new) $dst = ",
             !strconcat(OpcStr, "(#$src2)")),
             []>,
@@ -5735,31 +5738,31 @@ defm LDriuh_imm : LD_absimm<"memuh">;
 defm LDriw_imm : LD_absimm<"memw">;
 
 let Predicates = [HasV4T], AddedComplexity  = 30 in
-def : Pat<(i32 (load u6ImmPred:$src)),
-          (LDriw_imm_abs_V4 u6ImmPred:$src)>;
+def : Pat<(i32 (load u6ExtPred:$src)),
+          (LDriw_imm_abs_V4 u6ExtPred:$src)>;
 
 let Predicates = [HasV4T], AddedComplexity=30 in
-def : Pat<(i32 (sextloadi8 u6ImmPred:$src)),
-          (LDrib_imm_abs_V4 u6ImmPred:$src)>;
+def : Pat<(i32 (sextloadi8 u6ExtPred:$src)),
+          (LDrib_imm_abs_V4 u6ExtPred:$src)>;
 
 let Predicates = [HasV4T], AddedComplexity=30 in
-def : Pat<(i32 (zextloadi8 u6ImmPred:$src)),
-          (LDriub_imm_abs_V4 u6ImmPred:$src)>;
+def : Pat<(i32 (zextloadi8 u6ExtPred:$src)),
+          (LDriub_imm_abs_V4 u6ExtPred:$src)>;
 
 let Predicates = [HasV4T], AddedComplexity=30 in
-def : Pat<(i32 (sextloadi16 u6ImmPred:$src)),
-          (LDrih_imm_abs_V4 u6ImmPred:$src)>;
+def : Pat<(i32 (sextloadi16 u6ExtPred:$src)),
+          (LDrih_imm_abs_V4 u6ExtPred:$src)>;
 
 let Predicates = [HasV4T], AddedComplexity=30 in
-def : Pat<(i32 (zextloadi16 u6ImmPred:$src)),
-          (LDriuh_imm_abs_V4 u6ImmPred:$src)>;
+def : Pat<(i32 (zextloadi16 u6ExtPred:$src)),
+          (LDriuh_imm_abs_V4 u6ExtPred:$src)>;
 
 
 // Indexed store double word - global address.
 // memw(Rs+#u6:2)=#S8
 let AddedComplexity = 10 in
 def STriw_offset_ext_V4 : STInst<(outs),
-            (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
+            (ins IntRegs:$src1, u6_2Imm:$src2, globaladdressExt:$src3),
             "memw($src1+#$src2) = ##$src3",
             [(store (HexagonCONST32 tglobaladdr:$src3),
                     (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
@@ -5770,7 +5773,7 @@ def STriw_offset_ext_V4 : STInst<(outs),
 // memw(Rs+#u6:2)=#S8
 let AddedComplexity = 10 in
 def STrih_offset_ext_V4 : STInst<(outs),
-            (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
+            (ins IntRegs:$src1, u6_1Imm:$src2, globaladdressExt:$src3),
             "memh($src1+#$src2) = ##$src3",
             [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
                     (add IntRegs:$src1, u6_1ImmPred:$src2))]>,

diff --git a/lib/Target/Hexagon/HexagonInstrInfoV5.td b/lib/Target/Hexagon/HexagonInstrInfoV5.td
index 92d098cc04464dec7b5244369333ecdffadbecbb..15ca06f1fd3b1f517763592b6ceb0028c25cba7b 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfoV5.td
+++ b/lib/Target/Hexagon/HexagonInstrInfoV5.td
@@ -27,20 +27,20 @@ def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
 // For double precision, use CONST64_float_real, as 64bit transfer
 // can only hold 40-bit values - 32 from const ext + 8 bit immediate.
 let isMoveImm = 1, isReMaterializable = 1, isPredicable = 1 in
-def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32imm:$src1),
+def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
            "$dst = ##$src1",
            [(set IntRegs:$dst, fpimm:$src1)]>,
           Requires<[HasV5T]>;
 
 def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
-                          (ins PredRegs:$src1, f32imm:$src2),
+                          (ins PredRegs:$src1, f32Ext:$src2),
            "if ($src1) $dst = ##$src2",
            []>,
           Requires<[HasV5T]>;
 
 let isPredicated = 1 in
 def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst),
-                             (ins PredRegs:$src1, f32imm:$src2),
+                             (ins PredRegs:$src1, f32Ext:$src2),
            "if (!$src1) $dst = ##$src2",
            []>,
           Requires<[HasV5T]>;
@@ -67,10 +67,10 @@ def LDrid_f : LDInst<(outs DoubleRegs:$dst),
 
 let AddedComplexity = 20 in
 def LDrid_indexed_f : LDInst<(outs DoubleRegs:$dst),
-            (ins IntRegs:$src1, s11_3Imm:$offset),
+            (ins IntRegs:$src1, s11_3Ext:$offset),
             "$dst = memd($src1+#$offset)",
             [(set DoubleRegs:$dst, (f64 (load (add IntRegs:$src1,
-                                              s11_3ImmPred:$offset))))]>,
+                                              s11_3ExtPred:$offset))))]>,
           Requires<[HasV5T]>;
 
 def LDriw_f : LDInst<(outs IntRegs:$dst),
@@ -81,10 +81,10 @@ def LDriw_f : LDInst<(outs IntRegs:$dst),
 
 let AddedComplexity = 20 in
 def LDriw_indexed_f : LDInst<(outs IntRegs:$dst),
-            (ins IntRegs:$src1, s11_2Imm:$offset),
+            (ins IntRegs:$src1, s11_2Ext:$offset),
             "$dst = memw($src1+#$offset)",
             [(set IntRegs:$dst, (f32 (load (add IntRegs:$src1,
-                                           s11_2ImmPred:$offset))))]>,
+                                           s11_2ExtPred:$offset))))]>,
           Requires<[HasV5T]>;
 
 // Store.
@@ -96,10 +96,10 @@ def STriw_f : STInst<(outs),
 
 let AddedComplexity = 10 in
 def STriw_indexed_f : STInst<(outs),
-            (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
+            (ins IntRegs:$src1, s11_2Ext:$src2, IntRegs:$src3),
             "memw($src1+#$src2) = $src3",
             [(store (f32 IntRegs:$src3),
-                (add IntRegs:$src1, s11_2ImmPred:$src2))]>,
+                (add IntRegs:$src1, s11_2ExtPred:$src2))]>,
           Requires<[HasV5T]>;
 
 def STrid_f : STInst<(outs),
@@ -111,10 +111,10 @@ def STrid_f : STInst<(outs),
 // Indexed store double word.
 let AddedComplexity = 10 in
 def STrid_indexed_f : STInst<(outs),
-            (ins IntRegs:$src1, s11_3Imm:$src2,  DoubleRegs:$src3),
+            (ins IntRegs:$src1, s11_3Ext:$src2,  DoubleRegs:$src3),
             "memd($src1+#$src2) = $src3",
             [(store (f64 DoubleRegs:$src3),
-                                (add IntRegs:$src1, s11_3ImmPred:$src2))]>,
+                                (add IntRegs:$src1, s11_3ExtPred:$src2))]>,
           Requires<[HasV5T]>;
 
 

diff --git a/lib/Target/Hexagon/HexagonOptimizeConstExt.cpp b/lib/Target/Hexagon/HexagonOptimizeConstExt.cpp
new file mode 100644 (file)
index 0000000..91987a0
--- /dev/null
+++ b/lib/Target/Hexagon/HexagonOptimizeConstExt.cpp
@@ -0,0 +1,261 @@
+//===---- HexagonOptimizeConstExt.cpp - Optimize Constant Extender Use ----===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass traverses through all the basic blocks in a functions and replaces
+// constant extended instruction with their register equivalent if the same
+// constant is being used by more than two instructions.
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "xfer"
+#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "HexagonTargetMachine.h"
+#include "HexagonConstExtInfo.h"
+#include "llvm/CodeGen/MachineFunctionAnalysis.h"
+#include "llvm/Support/CommandLine.h"
+#define DEBUG_TYPE "xfer"
+
+using namespace llvm;
+
+namespace {
+
+class HexagonOptimizeConstExt : public MachineFunctionPass {
+  HexagonTargetMachine& QTM;
+  const HexagonSubtarget &QST;
+
+public:
+  static char ID;
+  HexagonOptimizeConstExt(HexagonTargetMachine& TM)
+    : MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {}
+
+  const char *getPassName() const {
+    return "Remove sub-optimal uses of constant extenders";
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const {
+    MachineFunctionPass::getAnalysisUsage(AU);
+    AU.addRequired<MachineDominatorTree>();
+    AU.addPreserved<MachineDominatorTree>();
+  }
+
+  bool runOnMachineFunction(MachineFunction &Fn);
+  void removeConstExtFromMI (const HexagonInstrInfo *TII, MachineInstr* oldMI,
+                             unsigned DestReg);
+};
+
+char HexagonOptimizeConstExt::ID = 0;
+
+// Remove constant extended instructions with the corresponding non-extended
+// instruction.
+void HexagonOptimizeConstExt::removeConstExtFromMI (const HexagonInstrInfo *TII,
+                                                    MachineInstr* oldMI,
+                                                    unsigned DestReg) {
+  assert(HexagonConstExt::NonExtEquivalentExists(oldMI->getOpcode()) &&
+         "Non-extended equivalent instruction doesn't exist");
+  MachineBasicBlock *MBB = oldMI->getParent ();
+  int oldOpCode = oldMI->getOpcode();
+  unsigned short CExtOpNum = HexagonConstExt::getCExtOpNum(oldOpCode);
+  unsigned numOperands = oldMI->getNumOperands();
+  MachineInstrBuilder MIB = BuildMI(*MBB, oldMI, oldMI->getDebugLoc(),
+                TII->get(HexagonConstExt::getNonExtOpcode(oldMI->getOpcode())));
+
+  for (unsigned i = 0; i < numOperands; ++i) {
+    if (i == CExtOpNum) {
+      MIB.addReg(DestReg);
+      if (oldMI->getDesc().mayLoad()) {
+        // As of now, only absolute addressing mode instructions can load from
+        // global addresses. Other addressing modes allow only constant
+        // literals. Load with absolute addressing mode gets replaced with the
+        // corresponding base+offset load.
+        if (oldMI->getOperand(i).isGlobal()) {
+          MIB.addImm(oldMI->getOperand(i).getOffset());
+        }
+        else
+          MIB.addImm(0);
+      }
+      else if (oldMI->getDesc().mayStore()){
+        if (oldMI->getOperand(i).isGlobal()) {
+          // If stored value is a global address and is extended, it is required
+          // to have 0 offset.
+          if (CExtOpNum == (numOperands-1))
+            assert((oldMI->getOperand(i).getOffset()==0) && "Invalid Offset");
+          else
+            MIB.addImm(oldMI->getOperand(i).getOffset());
+        }
+        else if (CExtOpNum != (numOperands-1))
+          MIB.addImm(0);
+      }
+    }
+    else {
+      const MachineOperand &op = oldMI->getOperand(i);
+      MIB.addOperand(op);
+    }
+  }
+  DEBUG(dbgs () << "Removing old instr: " << *oldMI << "\n");
+  DEBUG(dbgs() << "New instr: " << (*MIB) << "\n");
+  oldMI->eraseFromParent();
+}
+
+// Returns false for the following instructions, since it may not be profitable
+// to convert these instructions into a non-extended instruction if the offset
+// is non-zero.
+static bool canHaveAnyOffset(MachineInstr* MI) {
+  switch (MI->getOpcode()) {
+    case Hexagon::STriw_offset_ext_V4:
+    case Hexagon::STrih_offset_ext_V4:
+      return false;
+    default:
+      return true;
+  }
+}
+
+bool HexagonOptimizeConstExt::runOnMachineFunction(MachineFunction &Fn) {
+
+  const HexagonInstrInfo *TII = QTM.getInstrInfo();
+  MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
+
+  // CExtMap maintains a list of instructions for each constant extended value.
+  // It also keeps a flag for the value to indicate if it's a global address
+  // or a constant literal.
+  StringMap<std::pair<SmallVector<MachineInstr*, 8>, bool > > CExtMap;
+
+  // Loop over all the basic blocks
+  for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
+       MBBb != MBBe; ++MBBb) {
+    MachineBasicBlock* MBB = MBBb;
+
+    // Traverse the basic block and update a map of (ImmValue->MI)
+    MachineBasicBlock::iterator MII = MBB->begin();
+    MachineBasicBlock::iterator MIE = MBB->end ();
+
+    while (MII != MIE) {
+      MachineInstr *MI = MII;
+      // Check if the instruction has any constant extended operand and also has
+      //  a non-extended equivalent.
+      if (TII->isConstExtended(MI) &&
+          HexagonConstExt::NonExtEquivalentExists(MI->getOpcode())) {
+        short ExtOpNum = HexagonConstExt::getCExtOpNum(MI->getOpcode());
+        SmallString<256> TmpData;
+        if (MI->getOperand(ExtOpNum).isImm()) {
+          DEBUG(dbgs() << "Selected for replacement : " << *MI << "\n");
+          int ImmValue = MI->getOperand(ExtOpNum).getImm();
+          StringRef ExtValue = Twine(ImmValue).toStringRef(TmpData);
+          CExtMap[ExtValue].first.push_back(MI);
+          CExtMap[ExtValue].second = false;
+        }
+        else if (MI->getOperand(ExtOpNum).isGlobal()) {
+          StringRef ExtValue = MI->getOperand(ExtOpNum).getGlobal()->getName();
+          // If stored value is constant extended and has an offset, it's not
+          // profitable to replace these instructions with the non-extended
+          // version.
+          if (MI->getOperand(ExtOpNum).getOffset() == 0
+             || canHaveAnyOffset(MI)) {
+            DEBUG(dbgs() << "Selected for replacement : " << *MI << "\n");
+            CExtMap[ExtValue].first.push_back(MI);
+            CExtMap[ExtValue].second = true;
+          }
+        }
+      }
+      ++MII;
+    } // While ends
+  }
+
+  enum OpType {imm, GlobalAddr};
+  // Process the constants that have been extended.
+  for (StringMap<std::pair<SmallVector<MachineInstr*, 8>, bool> >::iterator II=
+         CExtMap.begin(), IE = CExtMap.end(); II != IE; ++II) {
+
+    SmallVector<MachineInstr*, 8> &MIList = (*II).second.first;
+
+    // Replace the constant extended instructions with the non-extended
+    // equivalent if more than 2 instructions extend the same constant value.
+    if (MIList.size() <= 2)
+      continue;
+
+    bool ExtOpType = (*II).second.second;
+    StringRef ExtValue = (*II).getKeyData();
+    const GlobalValue *GV = NULL;
+    unsigned char TargetFlags=0;
+    int ExtOpNum = HexagonConstExt::getCExtOpNum(MIList[0]->getOpcode());
+    SmallVector<MachineBasicBlock*, 8> MachineBlocks;
+
+    if (ExtOpType == GlobalAddr) {
+      GV = MIList[0]->getOperand(ExtOpNum).getGlobal();
+      TargetFlags = MIList[0]->getOperand(ExtOpNum).getTargetFlags();
+    }
+
+    // For each instruction in the list, record the block it belongs to.
+    for (SmallVector<MachineInstr*, 8>::iterator LB = MIList.begin(),
+           LE = MIList.end(); LB != LE; ++LB) {
+      MachineInstr *MI = (*LB);
+      MachineBlocks.push_back (MI->getParent());
+    }
+
+    MachineBasicBlock* CommDomBlock = MachineBlocks[0];
+    MachineBasicBlock* oldCommDomBlock = NULL;
+    // replaceMIs is the list of instructions to be replaced with a
+    // non-extended equivalent instruction.
+    // The idea here is that not all the instructions in the MIList will
+    // be replaced with a register.
+    SmallVector<MachineInstr*, 8> replaceMIs;
+    replaceMIs.push_back(MIList[0]);
+
+    for (unsigned i= 1; i < MachineBlocks.size(); ++i) {
+      oldCommDomBlock = CommDomBlock;
+      MachineBasicBlock *BB = MachineBlocks[i];
+      CommDomBlock = MDT.findNearestCommonDominator(&(*CommDomBlock),
+                                                    &(*BB));
+      if (!CommDomBlock) {
+        CommDomBlock = oldCommDomBlock;
+        break;
+      }
+      replaceMIs.push_back(MIList[i]);
+    }
+
+    // Insert into CommDomBlock.
+    if (CommDomBlock) {
+      unsigned DestReg = TII->createVR (CommDomBlock->getParent(), MVT::i32);
+      MachineInstr *firstMI = CommDomBlock->getFirstNonPHI();
+      if (ExtOpType == imm) {
+        int ImmValue = 0;
+        ExtValue.getAsInteger(10,ImmValue);
+        BuildMI (*CommDomBlock, firstMI, firstMI->getDebugLoc(),
+                                     TII->get(Hexagon::TFRI), DestReg)
+                                     .addImm(ImmValue);
+      }
+      else {
+        BuildMI (*CommDomBlock, firstMI, firstMI->getDebugLoc(),
+                                     TII->get(Hexagon::TFRI_V4), DestReg)
+                                     .addGlobalAddress(GV, 0, TargetFlags);
+      }
+      for (unsigned i= 0; i < replaceMIs.size(); i++) {
+        MachineInstr *oldMI = replaceMIs[i];
+        removeConstExtFromMI(TII, oldMI, DestReg);
+      }
+      replaceMIs.clear();
+    }
+  }
+  return true;
+}
+}
+
+//===----------------------------------------------------------------------===//
+//                         Public Constructor Functions
+//===----------------------------------------------------------------------===//
+
+FunctionPass *
+llvm::createHexagonOptimizeConstExt(HexagonTargetMachine &TM) {
+  return new HexagonOptimizeConstExt(TM);
+}
+

diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 8af95a9c206fa0d4854634e2b42822cdb5066d09..cad147398348fb0694fe6f7b91ca956a662b707d 100644 (file)
--- a/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -28,6 +28,10 @@ static cl::
 opt<bool> DisableHardwareLoops(
                         "disable-hexagon-hwloops", cl::Hidden,
                         cl::desc("Disable Hardware Loops for Hexagon target"));
+static cl::
+opt<bool> DisableCExtOpt(
+                        "disable-hexagon-cextopt", cl::Hidden,
+                        cl::desc("Disable Optimization of Constant Extenders"));
 
 /// HexagonTargetMachineModule - Note that this is used on hosts that
 /// cannot link in a library unless there are references into the
@@ -110,6 +114,9 @@ bool HexagonPassConfig::addInstSelector() {
 
 
 bool HexagonPassConfig::addPreRegAlloc() {
+  if (!DisableCExtOpt) {
+    PM->add(createHexagonOptimizeConstExt(getHexagonTargetMachine()));
+  }
   if (!DisableHardwareLoops) {
     PM->add(createHexagonHardwareLoops());
   }

diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index d4bca9fb5255105d80199168eb4d7f095961975f..fa1a969ea8750d20437a66f334d777ecf578ca9d 100644 (file)
--- a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -257,7 +257,7 @@ void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
 
 bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
   const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
-  assert(QII->isExtended(MI) &&
+  assert((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
          "Should only be called for constant extended instructions");
   MachineFunction *MF = MI->getParent()->getParent();
   MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT),
@@ -394,6 +394,16 @@ bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
     case Hexagon::POST_STbri_cdnPt_V4:
     case Hexagon::POST_STbri_cNotPt:
     case Hexagon::POST_STbri_cdnNotPt_V4:
+    case Hexagon::STrib_abs_V4:
+    case Hexagon::STrib_abs_cPt_V4:
+    case Hexagon::STrib_abs_cdnPt_V4:
+    case Hexagon::STrib_abs_cNotPt_V4:
+    case Hexagon::STrib_abs_cdnNotPt_V4:
+    case Hexagon::STrib_imm_abs_V4:
+    case Hexagon::STrib_imm_abs_cPt_V4:
+    case Hexagon::STrib_imm_abs_cdnPt_V4:
+    case Hexagon::STrib_imm_abs_cNotPt_V4:
+    case Hexagon::STrib_imm_abs_cdnNotPt_V4:
     case Hexagon::STb_GP_cPt_V4:
     case Hexagon::STb_GP_cNotPt_V4:
     case Hexagon::STb_GP_cdnPt_V4:
@@ -427,6 +437,16 @@ bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
     case Hexagon::POST_SThri_cdnPt_V4:
     case Hexagon::POST_SThri_cNotPt:
     case Hexagon::POST_SThri_cdnNotPt_V4:
+    case Hexagon::STrih_abs_V4:
+    case Hexagon::STrih_abs_cPt_V4:
+    case Hexagon::STrih_abs_cdnPt_V4:
+    case Hexagon::STrih_abs_cNotPt_V4:
+    case Hexagon::STrih_abs_cdnNotPt_V4:
+    case Hexagon::STrih_imm_abs_V4:
+    case Hexagon::STrih_imm_abs_cPt_V4:
+    case Hexagon::STrih_imm_abs_cdnPt_V4:
+    case Hexagon::STrih_imm_abs_cNotPt_V4:
+    case Hexagon::STrih_imm_abs_cdnNotPt_V4:
     case Hexagon::STh_GP_cPt_V4:
     case Hexagon::STh_GP_cNotPt_V4:
     case Hexagon::STh_GP_cdnPt_V4:
@@ -460,6 +480,16 @@ bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
     case Hexagon::POST_STwri_cdnPt_V4:
     case Hexagon::POST_STwri_cNotPt:
     case Hexagon::POST_STwri_cdnNotPt_V4:
+    case Hexagon::STriw_abs_V4:
+    case Hexagon::STriw_abs_cPt_V4:
+    case Hexagon::STriw_abs_cdnPt_V4:
+    case Hexagon::STriw_abs_cNotPt_V4:
+    case Hexagon::STriw_abs_cdnNotPt_V4:
+    case Hexagon::STriw_imm_abs_V4:
+    case Hexagon::STriw_imm_abs_cPt_V4:
+    case Hexagon::STriw_imm_abs_cdnPt_V4:
+    case Hexagon::STriw_imm_abs_cNotPt_V4:
+    case Hexagon::STriw_imm_abs_cdnNotPt_V4:
     case Hexagon::STw_GP_cPt_V4:
     case Hexagon::STw_GP_cNotPt_V4:
     case Hexagon::STw_GP_cdnPt_V4:
@@ -752,6 +782,98 @@ static int GetDotNewOp(const int opc) {
   case Hexagon::POST_STwri_cdnNotPt_V4:
     return Hexagon::POST_STwri_cdnNotPt_nv_V4;
 
+// Absolute addressing mode -- global address
+  case Hexagon::STrib_abs_V4:
+    return Hexagon::STrib_abs_nv_V4;
+
+  case Hexagon::STrib_abs_cPt_V4:
+    return Hexagon::STrib_abs_cPt_nv_V4;
+
+  case Hexagon::STrib_abs_cdnPt_V4:
+    return Hexagon::STrib_abs_cdnPt_nv_V4;
+
+  case Hexagon::STrib_abs_cNotPt_V4:
+    return Hexagon::STrib_abs_cNotPt_nv_V4;
+
+  case Hexagon::STrib_abs_cdnNotPt_V4:
+    return Hexagon::STrib_abs_cdnNotPt_nv_V4;
+
+  case Hexagon::STrih_abs_V4:
+    return Hexagon::STrih_abs_nv_V4;
+
+  case Hexagon::STrih_abs_cPt_V4:
+    return Hexagon::STrih_abs_cPt_nv_V4;
+
+  case Hexagon::STrih_abs_cdnPt_V4:
+    return Hexagon::STrih_abs_cdnPt_nv_V4;
+
+  case Hexagon::STrih_abs_cNotPt_V4:
+    return Hexagon::STrih_abs_cNotPt_nv_V4;
+
+  case Hexagon::STrih_abs_cdnNotPt_V4:
+    return Hexagon::STrih_abs_cdnNotPt_nv_V4;
+
+  case Hexagon::STriw_abs_V4:
+    return Hexagon::STriw_abs_nv_V4;
+
+  case Hexagon::STriw_abs_cPt_V4:
+    return Hexagon::STriw_abs_cPt_nv_V4;
+
+  case Hexagon::STriw_abs_cdnPt_V4:
+    return Hexagon::STriw_abs_cdnPt_nv_V4;
+
+  case Hexagon::STriw_abs_cNotPt_V4:
+    return Hexagon::STriw_abs_cNotPt_nv_V4;
+
+  case Hexagon::STriw_abs_cdnNotPt_V4:
+    return Hexagon::STriw_abs_cdnNotPt_nv_V4;
+
+// Absolute addressing mode -- immediate value
+  case Hexagon::STrib_imm_abs_V4:
+    return Hexagon::STrib_imm_abs_nv_V4;
+
+  case Hexagon::STrib_imm_abs_cPt_V4:
+    return Hexagon::STrib_imm_abs_cPt_nv_V4;
+
+  case Hexagon::STrib_imm_abs_cdnPt_V4:
+    return Hexagon::STrib_imm_abs_cdnPt_nv_V4;
+
+  case Hexagon::STrib_imm_abs_cNotPt_V4:
+    return Hexagon::STrib_imm_abs_cNotPt_nv_V4;
+
+  case Hexagon::STrib_imm_abs_cdnNotPt_V4:
+    return Hexagon::STrib_imm_abs_cdnNotPt_nv_V4;
+
+  case Hexagon::STrih_imm_abs_V4:
+    return Hexagon::STrih_imm_abs_nv_V4;
+
+  case Hexagon::STrih_imm_abs_cPt_V4:
+    return Hexagon::STrih_imm_abs_cPt_nv_V4;
+
+  case Hexagon::STrih_imm_abs_cdnPt_V4:
+    return Hexagon::STrih_imm_abs_cdnPt_nv_V4;
+
+  case Hexagon::STrih_imm_abs_cNotPt_V4:
+    return Hexagon::STrih_imm_abs_cNotPt_nv_V4;
+
+  case Hexagon::STrih_imm_abs_cdnNotPt_V4:
+    return Hexagon::STrih_imm_abs_cdnNotPt_nv_V4;
+
+  case Hexagon::STriw_imm_abs_V4:
+    return Hexagon::STriw_imm_abs_nv_V4;
+
+  case Hexagon::STriw_imm_abs_cPt_V4:
+    return Hexagon::STriw_imm_abs_cPt_nv_V4;
+
+  case Hexagon::STriw_imm_abs_cdnPt_V4:
+    return Hexagon::STriw_imm_abs_cdnPt_nv_V4;
+
+  case Hexagon::STriw_imm_abs_cNotPt_V4:
+    return Hexagon::STriw_imm_abs_cNotPt_nv_V4;
+
+  case Hexagon::STriw_imm_abs_cdnNotPt_V4:
+    return Hexagon::STriw_imm_abs_cdnNotPt_nv_V4;
+
   case Hexagon::STw_GP_cPt_V4:
     return Hexagon::STw_GP_cPt_nv_V4;
 
@@ -1404,6 +1526,103 @@ static int GetDotNewPredOp(const int opc) {
     return Hexagon::ZXTH_cdnPt_V4;
   case Hexagon::ZXTH_cNotPt_V4 :
     return Hexagon::ZXTH_cdnNotPt_V4;
+
+  // Load Absolute Addressing.
+  case Hexagon::LDrib_abs_cPt_V4 :
+    return Hexagon::LDrib_abs_cdnPt_V4;
+  case Hexagon::LDrib_abs_cNotPt_V4 :
+    return Hexagon::LDrib_abs_cdnNotPt_V4;
+
+  case Hexagon::LDriub_abs_cPt_V4 :
+    return Hexagon::LDriub_abs_cdnPt_V4;
+  case Hexagon::LDriub_abs_cNotPt_V4 :
+    return Hexagon::LDriub_abs_cdnNotPt_V4;
+
+  case Hexagon::LDrih_abs_cPt_V4 :
+    return Hexagon::LDrih_abs_cdnPt_V4;
+  case Hexagon::LDrih_abs_cNotPt_V4 :
+    return Hexagon::LDrih_abs_cdnNotPt_V4;
+
+  case Hexagon::LDriuh_abs_cPt_V4 :
+    return Hexagon::LDriuh_abs_cdnPt_V4;
+  case Hexagon::LDriuh_abs_cNotPt_V4 :
+    return Hexagon::LDriuh_abs_cdnNotPt_V4;
+
+  case Hexagon::LDriw_abs_cPt_V4 :
+    return Hexagon::LDriw_abs_cdnPt_V4;
+  case Hexagon::LDriw_abs_cNotPt_V4 :
+    return Hexagon::LDriw_abs_cdnNotPt_V4;
+
+  case Hexagon::LDrid_abs_cPt_V4 :
+    return Hexagon::LDrid_abs_cdnPt_V4;
+  case Hexagon::LDrid_abs_cNotPt_V4 :
+    return Hexagon::LDrid_abs_cdnNotPt_V4;
+
+  case Hexagon::LDrib_imm_abs_cPt_V4:
+    return Hexagon::LDrib_imm_abs_cdnPt_V4;
+  case Hexagon::LDrib_imm_abs_cNotPt_V4:
+    return Hexagon::LDrib_imm_abs_cdnNotPt_V4;
+
+  case Hexagon::LDriub_imm_abs_cPt_V4:
+    return Hexagon::LDriub_imm_abs_cdnPt_V4;
+  case Hexagon::LDriub_imm_abs_cNotPt_V4:
+    return Hexagon::LDriub_imm_abs_cdnNotPt_V4;
+
+  case Hexagon::LDrih_imm_abs_cPt_V4:
+    return Hexagon::LDrih_imm_abs_cdnPt_V4;
+  case Hexagon::LDrih_imm_abs_cNotPt_V4:
+    return Hexagon::LDrih_imm_abs_cdnNotPt_V4;
+
+  case Hexagon::LDriuh_imm_abs_cPt_V4:
+    return Hexagon::LDriuh_imm_abs_cdnPt_V4;
+  case Hexagon::LDriuh_imm_abs_cNotPt_V4:
+    return Hexagon::LDriuh_imm_abs_cdnNotPt_V4;
+
+  case Hexagon::LDriw_imm_abs_cPt_V4:
+    return Hexagon::LDriw_imm_abs_cdnPt_V4;
+  case Hexagon::LDriw_imm_abs_cNotPt_V4:
+    return Hexagon::LDriw_imm_abs_cdnNotPt_V4;
+
+  // Store Absolute Addressing.
+  case Hexagon::STrib_abs_cPt_V4 :
+    return Hexagon::STrib_abs_cdnPt_V4;
+  case Hexagon::STrib_abs_cNotPt_V4 :
+    return Hexagon::STrib_abs_cdnNotPt_V4;
+
+  case Hexagon::STrih_abs_cPt_V4 :
+    return Hexagon::STrih_abs_cdnPt_V4;
+  case Hexagon::STrih_abs_cNotPt_V4 :
+    return Hexagon::STrih_abs_cdnNotPt_V4;
+
+  case Hexagon::STriw_abs_cPt_V4 :
+    return Hexagon::STriw_abs_cdnPt_V4;
+  case Hexagon::STriw_abs_cNotPt_V4 :
+    return Hexagon::STriw_abs_cdnNotPt_V4;
+
+  case Hexagon::STrid_abs_cPt_V4 :
+    return Hexagon::STrid_abs_cdnPt_V4;
+  case Hexagon::STrid_abs_cNotPt_V4 :
+    return Hexagon::STrid_abs_cdnNotPt_V4;
+
+  case Hexagon::STrib_imm_abs_cPt_V4:
+    return Hexagon::STrib_imm_abs_cdnPt_V4;
+  case Hexagon::STrib_imm_abs_cNotPt_V4:
+    return Hexagon::STrib_imm_abs_cdnNotPt_V4;
+
+  case Hexagon::STrih_imm_abs_cPt_V4:
+    return Hexagon::STrih_imm_abs_cdnPt_V4;
+  case Hexagon::STrih_imm_abs_cNotPt_V4:
+    return Hexagon::STrih_imm_abs_cdnNotPt_V4;
+
+  case Hexagon::STriw_imm_abs_cPt_V4:
+    return Hexagon::STriw_imm_abs_cdnPt_V4;
+  case Hexagon::STriw_imm_abs_cNotPt_V4:
+    return Hexagon::STriw_imm_abs_cdnNotPt_V4;
+
+  case Hexagon::TFRI_cPt_V4:
+    return Hexagon::TFRI_cdnPt_V4;
+  case Hexagon::TFRI_cNotPt_V4:
+    return Hexagon::TFRI_cdnNotPt_V4;
   }
 }
 
@@ -1431,7 +1650,6 @@ bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
   return false;
 }
 
-
 // Promote an instructiont to its .new form.
 // At this time, we have already made a call to CanPromoteToDotNew
 // and made sure that it can *indeed* be promoted.
@@ -2140,6 +2358,159 @@ static int GetDotOldOp(const int opc) {
   case Hexagon::POST_STdri_cdnNotPt_V4 :
     return Hexagon::POST_STdri_cNotPt;
 
+// Absolute addressing mode - global address
+  case Hexagon::STrib_abs_nv_V4:
+    return Hexagon::STrib_abs_V4;
+
+  case Hexagon::STrib_abs_cdnPt_V4:
+  case Hexagon::STrib_abs_cPt_nv_V4:
+  case Hexagon::STrib_abs_cdnPt_nv_V4:
+    return Hexagon::STrib_abs_cPt_V4;
+
+  case Hexagon::STrib_abs_cdnNotPt_V4:
+  case Hexagon::STrib_abs_cNotPt_nv_V4:
+  case Hexagon::STrib_abs_cdnNotPt_nv_V4:
+    return Hexagon::STrib_abs_cNotPt_V4;
+
+  case Hexagon::STrih_abs_nv_V4:
+    return Hexagon::STrih_abs_V4;
+
+  case Hexagon::STrih_abs_cdnPt_V4:
+  case Hexagon::STrih_abs_cPt_nv_V4:
+  case Hexagon::STrih_abs_cdnPt_nv_V4:
+    return Hexagon::STrih_abs_cPt_V4;
+
+  case Hexagon::STrih_abs_cdnNotPt_V4:
+  case Hexagon::STrih_abs_cNotPt_nv_V4:
+  case Hexagon::STrih_abs_cdnNotPt_nv_V4:
+    return Hexagon::STrih_abs_cNotPt_V4;
+
+  case Hexagon::STriw_abs_nv_V4:
+    return Hexagon::STriw_abs_V4;
+
+  case Hexagon::STriw_abs_cdnPt_V4:
+  case Hexagon::STriw_abs_cPt_nv_V4:
+  case Hexagon::STriw_abs_cdnPt_nv_V4:
+    return Hexagon::STriw_abs_cPt_V4;
+
+  case Hexagon::STriw_abs_cdnNotPt_V4:
+  case Hexagon::STriw_abs_cNotPt_nv_V4:
+  case Hexagon::STriw_abs_cdnNotPt_nv_V4:
+    return Hexagon::STriw_abs_cNotPt_V4;
+
+  case Hexagon::STrid_abs_cdnPt_V4:
+    return Hexagon::STrid_abs_cPt_V4;
+
+  case Hexagon::STrid_abs_cdnNotPt_V4:
+    return Hexagon::STrid_abs_cNotPt_V4;
+
+// Absolute addressing mode - immediate values
+  case Hexagon::STrib_imm_abs_nv_V4:
+    return Hexagon::STrib_imm_abs_V4;
+
+  case Hexagon::STrib_imm_abs_cdnPt_V4:
+  case Hexagon::STrib_imm_abs_cPt_nv_V4:
+  case Hexagon::STrib_imm_abs_cdnPt_nv_V4:
+    return Hexagon::STrib_imm_abs_cPt_V4;
+
+  case Hexagon::STrib_imm_abs_cdnNotPt_V4:
+  case Hexagon::STrib_imm_abs_cNotPt_nv_V4:
+  case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4:
+    return Hexagon::STrib_imm_abs_cNotPt_V4;
+
+  case Hexagon::STrih_imm_abs_nv_V4:
+    return Hexagon::STrih_imm_abs_V4;
+
+  case Hexagon::STrih_imm_abs_cdnPt_V4:
+  case Hexagon::STrih_imm_abs_cPt_nv_V4:
+  case Hexagon::STrih_imm_abs_cdnPt_nv_V4:
+    return Hexagon::STrih_imm_abs_cPt_V4;
+
+  case Hexagon::STrih_imm_abs_cdnNotPt_V4:
+  case Hexagon::STrih_imm_abs_cNotPt_nv_V4:
+  case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4:
+    return Hexagon::STrih_imm_abs_cNotPt_V4;
+
+  case Hexagon::STriw_imm_abs_nv_V4:
+    return Hexagon::STriw_imm_abs_V4;
+
+  case Hexagon::STriw_imm_abs_cdnPt_V4:
+  case Hexagon::STriw_imm_abs_cPt_nv_V4:
+  case Hexagon::STriw_imm_abs_cdnPt_nv_V4:
+    return Hexagon::STriw_imm_abs_cPt_V4;
+
+  case Hexagon::STriw_imm_abs_cdnNotPt_V4:
+  case Hexagon::STriw_imm_abs_cNotPt_nv_V4:
+  case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4:
+    return Hexagon::STriw_imm_abs_cNotPt_V4;
+
+  // Load - absolute set addressing
+  case Hexagon::LDrib_abs_cdnPt_V4:
+    return Hexagon::LDrib_abs_cPt_V4;
+
+  case Hexagon::LDrib_abs_cdnNotPt_V4:
+    return Hexagon::LDrib_abs_cNotPt_V4;
+
+  case Hexagon::LDriub_abs_cdnPt_V4:
+    return Hexagon::LDriub_abs_cPt_V4;
+
+  case Hexagon::LDriub_abs_cdnNotPt_V4:
+    return Hexagon::LDriub_abs_cNotPt_V4;
+
+  case Hexagon::LDrih_abs_cdnPt_V4:
+    return Hexagon::LDrih_abs_cPt_V4;
+
+  case Hexagon::LDrih_abs_cdnNotPt_V4:
+    return Hexagon::LDrih_abs_cNotPt_V4;
+
+  case Hexagon::LDriuh_abs_cdnPt_V4:
+    return Hexagon::LDriuh_abs_cPt_V4;
+
+  case Hexagon::LDriuh_abs_cdnNotPt_V4:
+    return Hexagon::LDriuh_abs_cNotPt_V4;
+
+  case Hexagon::LDriw_abs_cdnPt_V4:
+    return Hexagon::LDriw_abs_cPt_V4;
+
+  case Hexagon::LDriw_abs_cdnNotPt_V4:
+    return Hexagon::LDriw_abs_cNotPt_V4;
+
+  case Hexagon::LDrid_abs_cdnPt_V4:
+    return Hexagon::LDrid_abs_cPt_V4;
+
+  case Hexagon::LDrid_abs_cdnNotPt_V4:
+    return Hexagon::LDrid_abs_cNotPt_V4;
+
+   case Hexagon::LDrib_imm_abs_cdnPt_V4:
+    return Hexagon::LDrib_imm_abs_cPt_V4;
+
+  case Hexagon::LDrib_imm_abs_cdnNotPt_V4:
+    return Hexagon::LDrib_imm_abs_cNotPt_V4;
+
+  case Hexagon::LDriub_imm_abs_cdnPt_V4:
+    return Hexagon::LDriub_imm_abs_cPt_V4;
+
+  case Hexagon::LDriub_imm_abs_cdnNotPt_V4:
+    return Hexagon::LDriub_imm_abs_cNotPt_V4;
+
+  case Hexagon::LDrih_imm_abs_cdnPt_V4:
+    return Hexagon::LDrih_imm_abs_cPt_V4;
+
+  case Hexagon::LDrih_imm_abs_cdnNotPt_V4:
+    return Hexagon::LDrih_imm_abs_cNotPt_V4;
+
+  case Hexagon::LDriuh_imm_abs_cdnPt_V4:
+    return Hexagon::LDriuh_imm_abs_cPt_V4;
+
+  case Hexagon::LDriuh_imm_abs_cdnNotPt_V4:
+    return Hexagon::LDriuh_imm_abs_cNotPt_V4;
+
+  case Hexagon::LDriw_imm_abs_cdnPt_V4:
+    return Hexagon::LDriw_imm_abs_cPt_V4;
+
+  case Hexagon::LDriw_imm_abs_cdnNotPt_V4:
+    return Hexagon::LDriw_imm_abs_cNotPt_V4;
+
   case Hexagon::STd_GP_cdnPt_V4 :
     return Hexagon::STd_GP_cPt_V4;
 
@@ -2298,6 +2669,46 @@ static bool GetPredicateSense(MachineInstr* MI,
   case Hexagon::ZXTB_cdnPt_V4 :
   case Hexagon::ZXTH_cPt_V4 :
   case Hexagon::ZXTH_cdnPt_V4 :
+
+  case Hexagon::LDrib_abs_cPt_V4 :
+  case Hexagon::LDrib_abs_cdnPt_V4:
+  case Hexagon::LDriub_abs_cPt_V4 :
+  case Hexagon::LDriub_abs_cdnPt_V4:
+  case Hexagon::LDrih_abs_cPt_V4 :
+  case Hexagon::LDrih_abs_cdnPt_V4:
+  case Hexagon::LDriuh_abs_cPt_V4 :
+  case Hexagon::LDriuh_abs_cdnPt_V4:
+  case Hexagon::LDriw_abs_cPt_V4 :
+  case Hexagon::LDriw_abs_cdnPt_V4:
+  case Hexagon::LDrid_abs_cPt_V4 :
+  case Hexagon::LDrid_abs_cdnPt_V4:
+
+  case Hexagon::LDrib_imm_abs_cPt_V4 :
+  case Hexagon::LDrib_imm_abs_cdnPt_V4:
+  case Hexagon::LDriub_imm_abs_cPt_V4 :
+  case Hexagon::LDriub_imm_abs_cdnPt_V4:
+  case Hexagon::LDrih_imm_abs_cPt_V4 :
+  case Hexagon::LDrih_imm_abs_cdnPt_V4:
+  case Hexagon::LDriuh_imm_abs_cPt_V4 :
+  case Hexagon::LDriuh_imm_abs_cdnPt_V4:
+  case Hexagon::LDriw_imm_abs_cPt_V4 :
+  case Hexagon::LDriw_imm_abs_cdnPt_V4:
+
+  case Hexagon::STrib_abs_cPt_V4:
+  case Hexagon::STrib_abs_cdnPt_V4:
+  case Hexagon::STrih_abs_cPt_V4:
+  case Hexagon::STrih_abs_cdnPt_V4:
+  case Hexagon::STriw_abs_cPt_V4:
+  case Hexagon::STriw_abs_cdnPt_V4:
+  case Hexagon::STrid_abs_cPt_V4:
+  case Hexagon::STrid_abs_cdnPt_V4:
+  case Hexagon::STrib_imm_abs_cPt_V4:
+  case Hexagon::STrib_imm_abs_cdnPt_V4:
+  case Hexagon::STrih_imm_abs_cPt_V4:
+  case Hexagon::STrih_imm_abs_cdnPt_V4:
+  case Hexagon::STriw_imm_abs_cPt_V4:
+  case Hexagon::STriw_imm_abs_cdnPt_V4:
+
   case Hexagon::LDrid_GP_cPt_V4 :
   case Hexagon::LDrib_GP_cPt_V4 :
   case Hexagon::LDriub_GP_cPt_V4 :
@@ -2470,6 +2881,45 @@ static bool GetPredicateSense(MachineInstr* MI,
   case Hexagon::ZXTH_cNotPt_V4 :
   case Hexagon::ZXTH_cdnNotPt_V4 :
 
+  case Hexagon::LDrib_abs_cNotPt_V4:
+  case Hexagon::LDrib_abs_cdnNotPt_V4:
+  case Hexagon::LDriub_abs_cNotPt_V4 :
+  case Hexagon::LDriub_abs_cdnNotPt_V4:
+  case Hexagon::LDrih_abs_cNotPt_V4 :
+  case Hexagon::LDrih_abs_cdnNotPt_V4:
+  case Hexagon::LDriuh_abs_cNotPt_V4 :
+  case Hexagon::LDriuh_abs_cdnNotPt_V4:
+  case Hexagon::LDriw_abs_cNotPt_V4 :
+  case Hexagon::LDriw_abs_cdnNotPt_V4:
+  case Hexagon::LDrid_abs_cNotPt_V4 :
+  case Hexagon::LDrid_abs_cdnNotPt_V4:
+
+  case Hexagon::LDrib_imm_abs_cNotPt_V4:
+  case Hexagon::LDrib_imm_abs_cdnNotPt_V4:
+  case Hexagon::LDriub_imm_abs_cNotPt_V4 :
+  case Hexagon::LDriub_imm_abs_cdnNotPt_V4:
+  case Hexagon::LDrih_imm_abs_cNotPt_V4 :
+  case Hexagon::LDrih_imm_abs_cdnNotPt_V4:
+  case Hexagon::LDriuh_imm_abs_cNotPt_V4 :
+  case Hexagon::LDriuh_imm_abs_cdnNotPt_V4:
+  case Hexagon::LDriw_imm_abs_cNotPt_V4 :
+  case Hexagon::LDriw_imm_abs_cdnNotPt_V4:
+
+  case Hexagon::STrib_abs_cNotPt_V4:
+  case Hexagon::STrib_abs_cdnNotPt_V4:
+  case Hexagon::STrih_abs_cNotPt_V4:
+  case Hexagon::STrih_abs_cdnNotPt_V4:
+  case Hexagon::STriw_abs_cNotPt_V4:
+  case Hexagon::STriw_abs_cdnNotPt_V4:
+  case Hexagon::STrid_abs_cNotPt_V4:
+  case Hexagon::STrid_abs_cdnNotPt_V4:
+  case Hexagon::STrib_imm_abs_cNotPt_V4:
+  case Hexagon::STrib_imm_abs_cdnNotPt_V4:
+  case Hexagon::STrih_imm_abs_cNotPt_V4:
+  case Hexagon::STrih_imm_abs_cdnNotPt_V4:
+  case Hexagon::STriw_imm_abs_cNotPt_V4:
+  case Hexagon::STriw_imm_abs_cdnNotPt_V4:
+
   case Hexagon::LDrid_GP_cNotPt_V4 :
   case Hexagon::LDrib_GP_cNotPt_V4 :
   case Hexagon::LDriub_GP_cNotPt_V4 :
@@ -3503,6 +3953,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
                && QRI->Subtarget.hasV4TOps()
                && J->getOpcode() == Hexagon::ALLOCFRAME
                && (I->getOpcode() == Hexagon::STrid
+                   || I->getOpcode() == Hexagon::STriw_indexed
                    || I->getOpcode() == Hexagon::STriw
                    || I->getOpcode() == Hexagon::STrib)
                && I->getOperand(0).getReg() == QRI->getStackRegister()
@@ -3580,7 +4031,7 @@ HexagonPacketizerList::addToPacket(MachineInstr *MI) {
       MachineInstr *nvjMI = MII;
       assert(ResourceTracker->canReserveResources(MI));
       ResourceTracker->reserveResources(MI);
-      if (QII->isExtended(MI) &&
+      if ((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
           !tryAllocateResourcesForConstExt(MI)) {
         endPacket(MBB, MI);
         ResourceTracker->reserveResources(MI);
@@ -3616,7 +4067,7 @@ HexagonPacketizerList::addToPacket(MachineInstr *MI) {
       CurrentPacketMIs.push_back(MI);
       CurrentPacketMIs.push_back(nvjMI);
     } else {
-      if (   QII->isExtended(MI)
+      if (   (QII->isExtended(MI) || QII->isConstExtended(MI))
           && (   !tryAllocateResourcesForConstExt(MI)
               || !ResourceTracker->canReserveResources(MI)))
       {

diff --git a/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp b/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp
index 035afe88d5bcec82a6d42698efb2ec5bd188388c..6d969619f76fb78e63dbe9ae9c397fcff590062f 100644 (file)
--- a/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp
+++ b/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp
@@ -13,6 +13,7 @@
 
 #define DEBUG_TYPE "asm-printer"
 #include "Hexagon.h"
+#include "HexagonConstExtInfo.h"
 #include "HexagonAsmPrinter.h"
 #include "HexagonInstPrinter.h"
 #include "HexagonMCInst.h"
@@ -107,7 +108,10 @@ void HexagonInstPrinter::printImmOperand(const MCInst *MI, unsigned OpNo,
 
 void HexagonInstPrinter::printExtOperand(const MCInst *MI, unsigned OpNo,
                                          raw_ostream &O) const {
-  O << MI->getOperand(OpNo).getImm();
+  if (isConstExtended(MI))
+    O << "#" << MI->getOperand(OpNo).getImm();
+  else
+    O << MI->getOperand(OpNo).getImm();
 }
 
 void HexagonInstPrinter::printUnsignedImmOperand(const MCInst *MI,
@@ -117,7 +121,7 @@ void HexagonInstPrinter::printUnsignedImmOperand(const MCInst *MI,
 
 void HexagonInstPrinter::printNegImmOperand(const MCInst *MI, unsigned OpNo,
                                             raw_ostream &O) const {
-  O << -MI->getOperand(OpNo).getImm();
+    O << -MI->getOperand(OpNo).getImm();
 }
 
 void HexagonInstPrinter::printNOneImmOperand(const MCInst *MI, unsigned OpNo,
@@ -131,7 +135,10 @@ void HexagonInstPrinter::printMEMriOperand(const MCInst *MI, unsigned OpNo,
   const MCOperand& MO1 = MI->getOperand(OpNo + 1);
 
   O << getRegisterName(MO0.getReg());
-  O << " + #" << MO1.getImm();
+  if (isConstExtended(MI))
+    O << " + ##" << MO1.getImm();
+  else
+    O << " + #" << MO1.getImm();
 }
 
 void HexagonInstPrinter::printFrameIndexOperand(const MCInst *MI, unsigned OpNo,
@@ -196,3 +203,17 @@ void HexagonInstPrinter::printSymbol(const MCInst *MI, unsigned OpNo,
   }
   O << ')';
 }
+
+bool HexagonInstPrinter::isConstExtended(const MCInst *MI) const{
+  unsigned short Opcode = MI->getOpcode();
+  short ExtOpNum = HexagonConstExt::getCExtOpNum(Opcode);
+  int MinValue = HexagonConstExt::getMinValue(Opcode);
+  int MaxValue = HexagonConstExt::getMaxValue(Opcode);
+
+  // Instruction has no constant extended operand
+  if (ExtOpNum == -1)
+    return false;
+
+  int ImmValue = MI->getOperand(ExtOpNum).getImm();
+  return (ImmValue < MinValue || ImmValue > MaxValue);
+}

diff --git a/test/CodeGen/Hexagon/constext.ll b/test/CodeGen/Hexagon/constext.ll
new file mode 100644 (file)
index 0000000..ef2e359
--- /dev/null
+++ b/test/CodeGen/Hexagon/constext.ll
@@ -0,0 +1,70 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; Make sure that constant extended instructions are generated.
+
+; Check if add and add-sub instructions are extended.
+define i32 @test1(i32 %b, i32* nocapture %c) nounwind {
+entry:
+%0 = load i32* %c, align 4
+%add1 = add nsw i32 %0, 44400
+; CHECK: add(r{{[0-9]+}}{{ *}},{{ *}}##44400)
+%add = add i32 %b, 33000
+%sub = sub i32 %add, %0
+; CHECK: add(r{{[0-9]+}},{{ *}}sub(##33000,{{ *}}r{{[0-9]+}})
+%add2 = add nsw i32 %add1, %0
+store i32 %add1, i32* %c, align 4
+  %mul = mul nsw i32 %add2, %sub
+  ret i32 %mul
+}
+
+; Check if load and store instructions are extended.
+define i32 @test2(i32* nocapture %b, i32 %c) nounwind {
+entry:
+  %arrayidx = getelementptr inbounds i32* %b, i32 7000
+  %0 = load i32* %arrayidx, align 4
+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}##28000) 
+  %sub = sub nsw i32 8000, %0
+; CHECK: sub(##8000{{ *}},{{ *}}r{{[0-9]+}})
+  %cmp = icmp sgt i32 %sub, 10
+  br i1 %cmp, label %if.then, label %if.else
+
+if.then:
+  %add = add nsw i32 %sub, %c
+  br label %return
+
+if.else:
+  %arrayidx1 = getelementptr inbounds i32* %b, i32 6000
+  store i32 %sub, i32* %arrayidx1, align 4
+; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}##24000){{ *}}={{ *}}r{{[0-9]+}}
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ %add, %if.then ], [ 0, %if.else ]
+  ret i32 %retval.0
+}
+
+; Check if the transfer, compare and mpyi instructions are extended.
+define i32 @test3() nounwind {
+entry:
+  %call = tail call i32 @b(i32 1235, i32 34567) nounwind
+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}##34567
+  %sext = shl i32 %call, 16
+  %conv1 = ashr exact i32 %sext, 16
+  %cmp = icmp slt i32 %sext, 65536
+  br i1 %cmp, label %if.then, label %if.else
+; CHECK: cmp.gt(r{{[0-9]+}}{{ *}},{{ *}}##65535)
+
+if.then:
+  %mul = mul nsw i32 %conv1, 34567
+  br label %if.end
+; CHECK: r{{[0-9]+}}{{ *}}=+{{ *}}mpyi(r{{[0-9]+}}{{ *}},{{ *}}##34567)
+
+if.else:
+  %mul5 = mul nsw i32 %conv1, 1235
+  br label %if.end
+
+if.end:
+  %a.0 = phi i32 [ %mul, %if.then ], [ %mul5, %if.else ]
+  ret i32 %a.0
+}
+
+declare i32 @b(i32, i32)

diff --git a/test/CodeGen/Hexagon/dualstore.ll b/test/CodeGen/Hexagon/dualstore.ll
index 9b27dda52c1d496724e89c103057f9e23f8eda4d..1e97d14e0bd793425ba59258df4bec2a951f3b62 100644 (file)
--- a/test/CodeGen/Hexagon/dualstore.ll
+++ b/test/CodeGen/Hexagon/dualstore.ll
@@ -6,12 +6,12 @@
 ; CHECK-NEXT: }
 
 @Reg = global i32 0, align 4
-define i32 @main() nounwind {
+define void @foo() nounwind {
 entry:
   %number= alloca i32, align 4
-  store i32 500000, i32* %number, align 4
+  store i32 500, i32* %number, align 4
   %number1= alloca i32, align 4
-  store i32 100000, i32* %number1, align 4
-  ret i32 0
+  store i32 100, i32* %number1, align 4
+  ret void
 }