[AVX512] Remove alternate data type versions of VALIGND, VALIGNQ, VMOVSHDUP and VMOVS...
[oota-llvm.git] / lib / Target / ARM / ARMScheduleA8.td
2012-08-08 Andrew TrickAdded MispredictPenalty to SchedMachineModel.
2012-07-07 Andrew TrickI'm introducing a new machine model to simultaneously...
2012-07-02 Andrew TrickReapply "Make NumMicroOps a variable in the subtarget...
2012-06-29 Andrew TrickRevert "Make NumMicroOps a variable in the subtarget...
2012-06-29 Andrew TrickMake NumMicroOps a variable in the subtarget's instruct...
2012-06-05 Andrew TrickARM itinerary properties.
2012-04-11 Evan ChengFix a number of problems with ARM fused multiply add...
2011-01-20 Evan ChengSorry, several patches in one.
2010-11-30 Bob WilsonAdd support for NEON VLD3-dup instructions.
2010-11-29 Bob WilsonAdd support for NEON VLD3-dup instructions.
2010-11-29 Bob WilsonFix copy-and-paste errors in VLD2-dup scheduling itiner...
2010-11-28 Bob WilsonAdd support for NEON VLD2-dup instructions.
2010-11-27 Bob WilsonAdd NEON VLD1-dup instructions (load 1 element to all...
2010-11-27 Bob WilsonFix incorrect scheduling itineraries for NEON vld1...
2010-11-13 Evan ChengConditional moves are slightly more expensive than...
2010-11-03 Evan ChengFix preload instruction isel. Only v7 supports pli...
2010-11-03 Evan ChengModify scheduling itineraries to correct instruction...
2010-11-02 Bob WilsonAdd NEON VST1-lane instructions. Partial fix for Radar...
2010-11-01 Bob WilsonAdd NEON VLD1-lane instructions. Partial fix for Radar...
2010-10-29 Evan ChengFix fpscr <-> GPR latency info.
2010-10-21 Andrew Trickputback r116983 and fix simple-fp-encoding.ll tests
2010-10-21 Owen AndersonRevert r116983, which is breaking all the buildbots.
2010-10-21 Evan ChengAdd missing scheduling itineraries for transfers betwee...
2010-10-11 Evan ChengMore ARM scheduling itinerary fixes.
2010-10-11 Evan ChengProper VST scheduling itineraries.
2010-10-09 Evan ChengAdd VLD4 scheduling itineraries.
2010-10-09 Evan ChengFinish vld3 and vld4.
2010-10-09 Evan ChengComplete vld2 instruction itineries.
2010-10-09 Evan ChengMultiply instructions are issued on pipeline 0. They...
2010-10-09 Evan ChengCorrect some load / store instruction itinerary mistakes:
2010-10-07 Evan ChengModel operand cycles of vldm / vstm; also fixes schedul...
2010-10-06 Evan Cheng- Add TargetInstrInfo::getOperandLatency() to compute...
2010-10-01 Evan ChengFix scheduling infor for vmovn and vshrn which I broke...
2010-10-01 Evan ChengAdd operand cycles for vldr / vstr.
2010-10-01 Evan ChengNEON scheduling info fix. vmov reg, reg are single...
2010-09-30 Evan ChengARM instruction itinerary fixes:
2010-09-29 Evan ChengModel Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC...
2010-09-29 Evan ChengSeparate itinerary classes for mvn from mov; for tst...
2010-09-29 Evan ChengAssign bitwise binary instructions different itinerary...
2010-09-28 Evan ChengAdd support to model pipeline bypass / forwarding.
2010-09-25 Evan ChengRemove a unused instruction itinerary class.
2010-09-25 Evan ChengFix zero and sign extension instructions scheduling...
2010-09-24 Evan ChengMore pseudo instruction scheduling itinerary fixes.
2010-09-24 Evan ChengFix scheduling itinerary for pseudo mov immediate instr...
2010-09-08 Evan ChengFix LDM_RET schedule itinery.
2010-06-28 Jim Grosbachminor housekeeping cleanup: 80-column, trailing whitesp...
2010-04-18 Anton KorobeynikovMake processor FUs unique for given itinerary. This...
2010-04-07 Anton KorobeynikovSplit A8/A9 itins - they already were too big.