Fix LDM_RET schedule itinery.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113435 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index e66f9b9ad0ac5653f03c881cd1ea688410fede12..372277858cee4b3dff4e2a69ab3e515800f698db 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -940,7 +940,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
     hasExtraDefRegAllocReq = 1 in
   def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
                                         reglist:$dsts, variable_ops),
-                       IndexModeUpd, LdStMulFrm, IIC_Br,
+                       IndexModeUpd, LdStMulFrm, IIC_iLoadmBr,
                        "ldm${addr:submode}${p}\t$addr!, $dsts",
                        "$addr.addr = $wb", []>;
 

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 096a8c7350ea482cca83dbb3092338ef60cc3929..5f88fbe8a2ea0b0f303c5bc68587b97b90d4c87c 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -2454,7 +2454,8 @@ let Defs =
 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
     hasExtraDefRegAllocReq = 1 in
   def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
-                                         reglist:$dsts, variable_ops), IIC_Br,
+                                         reglist:$dsts, variable_ops),
+                        IIC_iLoadmBr,
                         "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
                         "$addr.addr = $wb", []> {
   let Inst{31-27} = 0b11101;

diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td
index b60ccca46867aa10e7865735ab936c17229737ec..7566721577712168ee755b1b803278ad17d35142 100644 (file)
--- a/lib/Target/ARM/ARMSchedule.td
+++ b/lib/Target/ARM/ARMSchedule.td
@@ -43,6 +43,7 @@ def IIC_iLoadiu    : InstrItinClass;
 def IIC_iLoadru    : InstrItinClass;
 def IIC_iLoadsiu   : InstrItinClass;
 def IIC_iLoadm     : InstrItinClass;
+def IIC_iLoadmBr   : InstrItinClass;
 def IIC_iStorei    : InstrItinClass;
 def IIC_iStorer    : InstrItinClass;
 def IIC_iStoresi   : InstrItinClass;

diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td
index 282abca98803a65a5748ff777163e232b9cc68af..2902fbbad0f8d29d7ecfe9a3fd3a17ed7c7c99b2 100644 (file)
--- a/lib/Target/ARM/ARMScheduleA8.td
+++ b/lib/Target/ARM/ARMScheduleA8.td
@@ -122,6 +122,15 @@ def CortexA8Itineraries : ProcessorItineraries<
                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
                                 InstrStage<1, [A8_LdSt0]>]>,
 
+  //
+  // Load multiple plus branch
+  InstrItinData<IIC_iLoadmBr , [InstrStage<2, [A8_Issue], 0>,
+                                InstrStage<2, [A8_Pipe0], 0>,
+                                InstrStage<2, [A8_Pipe1]>,
+                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
+                                InstrStage<1, [A8_LdSt0]>,
+                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
+
   // Integer store pipeline
   //
   // use A8_Issue to enforce the 1 load/store per cycle limit

diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td
index df2f896a8d4b1cff09db8931022be366d87b25f0..4a764cc81176fa7decbe137d1092e74d08406aca 100644 (file)
--- a/lib/Target/ARM/ARMScheduleA9.td
+++ b/lib/Target/ARM/ARMScheduleA9.td
@@ -107,6 +107,12 @@ def CortexA9Itineraries : ProcessorItineraries<
   InstrItinData<IIC_iLoadm   , [InstrStage<1, [A9_Pipe1]>,
                                 InstrStage<1, [A9_LSPipe]>]>,
 
+  //
+  // Load multiple plus branch
+  InstrItinData<IIC_iLoadmBr , [InstrStage<1, [A9_Pipe1]>,
+                                InstrStage<1, [A9_LSPipe]>,
+                                InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>,
+
   // Integer store pipeline
   ///
   // Immediate offset