Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC...
[oota-llvm.git] / lib / Target / ARM / ARMSchedule.td
2012-02-18 Jia LiuEmacs-tag and some comment fix for all ARM, CellSPU...
2012-01-22 Anton KorobeynikovAdd fused multiple+add instructions from VFPv4.
2011-01-20 Evan ChengSorry, several patches in one.
2010-11-30 Bob WilsonAdd support for NEON VLD3-dup instructions.
2010-11-29 Bob WilsonAdd support for NEON VLD3-dup instructions.
2010-11-28 Bob WilsonAdd support for NEON VLD2-dup instructions.
2010-11-27 Bob WilsonAdd NEON VLD1-dup instructions (load 1 element to all...
2010-11-13 Evan ChengConditional moves are slightly more expensive than...
2010-11-03 Evan ChengFix preload instruction isel. Only v7 supports pli...
2010-11-02 Bob WilsonAdd NEON VST1-lane instructions. Partial fix for Radar...
2010-11-01 Bob WilsonAdd NEON VLD1-lane instructions. Partial fix for Radar...
2010-10-11 Evan ChengMore ARM scheduling itinerary fixes.
2010-10-11 Evan ChengProper VST scheduling itineraries.
2010-10-09 Evan ChengAdd VLD4 scheduling itineraries.
2010-10-09 Evan ChengFinish vld3 and vld4.
2010-10-09 Evan ChengCorrect some load / store instruction itinerary mistakes:
2010-10-07 Evan ChengModel operand cycles of vldm / vstm; also fixes schedul...
2010-10-06 Evan Cheng- Add TargetInstrInfo::getOperandLatency() to compute...
2010-10-01 Evan ChengNEON scheduling info fix. vmov reg, reg are single...
2010-09-30 Evan ChengARM instruction itinerary fixes:
2010-09-29 Evan ChengModel Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC...
2010-09-29 Evan ChengSeparate itinerary classes for mvn from mov; for tst...
2010-09-29 Evan ChengAssign bitwise binary instructions different itinerary...
2010-09-28 Evan ChengAdd support to model pipeline bypass / forwarding.
2010-09-25 Evan ChengRemove a unused instruction itinerary class.
2010-09-25 Evan ChengFix zero and sign extension instructions scheduling...
2010-09-24 Evan ChengMore pseudo instruction scheduling itinerary fixes.
2010-09-24 Evan ChengFix scheduling itinerary for pseudo mov immediate instr...
2010-09-09 Evan ChengFor each instruction itinerary class, specify the numbe...
2010-09-08 Evan ChengFix LDM_RET schedule itinery.
2010-04-18 Anton KorobeynikovMake processor FUs unique for given itinerary. This...
2010-04-07 Anton KorobeynikovSplit A8/A9 itins - they already were too big.
2010-04-07 Anton KorobeynikovFix itins for VABA
2010-04-07 Anton KorobeynikovVHADD differs from VHSUB at least on A9 - the former...
2010-04-07 Anton KorobeynikovDefine new itin classes for ARM <-> VFP reg moves to...
2010-04-07 Anton KorobeynikovAdd new itin classes for FP16 <-> FP32 conversions...
2010-04-07 Anton KorobeynikovMake use of new reserved/required scheduling stuff...
2009-09-25 David GoodwinFinish scheduling itineraries for NEON.
2009-09-24 David GoodwinMake the end-of-itinerary mark explicit. Some cleanup.
2009-09-23 David GoodwinCheckpoint NEON scheduling itineraries.
2009-09-21 David GoodwinAdd Cortex-A8 VFP model.
2009-08-19 David GoodwinUpdate Cortex-A8 instruction itineraries for integer...
2009-08-15 Evan ChengTurn on if-conversion for thumb2.
2009-08-13 David GoodwinFinalize itineraries for cortex-a8 integer multiply
2009-08-11 David GoodwinAllow a zero cycle stage to reserve/require a FU withou...
2009-08-10 David GoodwinCheckpoint scheduling itinerary changes.
2009-07-21 Evan ChengAdd fake v7 itineraries for now.
2009-06-19 Evan ChengLatency information for ARM v6. It's rough and not...