Fix a thinko: When lowering fneg with xor, bitcast the operands

from floating-point to integer first, and bitcast the result
back to floating-point. Previously, this test was passing by
falling back to SelectionDAG lowering. The resulting code isn't
as nice, but it's correct and CodeGen now stays on the fast path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81171 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index f0c7086184330326a9a008c740bc6bcec9c9b27b..8550ea9813dd272812b6c262b27ca59d64a73952 100644 (file)
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -615,12 +615,25 @@ FastISel::SelectFNeg(User *I) {
   unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
   if (OpReg == 0) return false;
 
   unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
   if (OpReg == 0) return false;
 

-  // Twiddle the sign bit with xor.
+  // Bitcast the value to integer, twiddle the sign bit with xor,
+  // and then bitcast it back to floating-point.

   EVT VT = TLI.getValueType(I->getType());
   if (VT.getSizeInBits() > 64) return false;
   EVT VT = TLI.getValueType(I->getType());
   if (VT.getSizeInBits() > 64) return false;

-  unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISD::XOR, OpReg,
-                                    UINT64_C(1) << (VT.getSizeInBits()-1),
-                                    VT.getSimpleVT());
+  EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
+
+  unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
+                               ISD::BIT_CONVERT, OpReg);
+  if (IntReg == 0)
+    return false;
+
+  unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg,
+                                       UINT64_C(1) << (VT.getSizeInBits()-1),
+                                       IntVT.getSimpleVT());
+  if (IntResultReg == 0)
+    return false;
+
+  unsigned ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
+                                  ISD::BIT_CONVERT, IntResultReg);

   if (ResultReg == 0)
     return false;
 
   if (ResultReg == 0)
     return false;
 

diff --git a/test/CodeGen/X86/fast-isel-fneg.ll b/test/CodeGen/X86/fast-isel-fneg.ll
index 41b288ba1de4c6c6dcb7dcb284b240f0615df9fa..02c5e4e2299bcab413ec324e0468544103f30e46 100644 (file)
--- a/test/CodeGen/X86/fast-isel-fneg.ll
+++ b/test/CodeGen/X86/fast-isel-fneg.ll
@@ -1,14 +1,14 @@
-; RUN: llvm-as < %s | llc -fast-isel -march=x86-64 | FileCheck %s
+; RUN: llvm-as < %s | llc -fast-isel -fast-isel-abort -march=x86-64 | FileCheck %s

 
 ; CHECK: doo:
 
 ; CHECK: doo:

-; CHECK: xorpd
+; CHECK: xor

 define double @doo(double %x) nounwind {
   %y = fsub double -0.0, %x
   ret double %y
 }
 
 ; CHECK: foo:
 define double @doo(double %x) nounwind {
   %y = fsub double -0.0, %x
   ret double %y
 }
 
 ; CHECK: foo:

-; CHECK: xorps
+; CHECK: xor

 define float @foo(float %x) nounwind {
   %y = fsub float -0.0, %x
   ret float %y
 define float @foo(float %x) nounwind {
   %y = fsub float -0.0, %x
   ret float %y