[AArch64] Fix problems in decoding generic MSR instructions

Bitpatterns rejected by the decoder method of `MSR (immediate)` should be
decoded as the `extended MSR (register)` instruction.

Differential Revision: http://reviews.llvm.org/D7174

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242276 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td
index 3f2e772a90c45e487150acafec349d889c408528..badc72040765ae9bb427fdb0c700f50011b64033 100644 (file)
--- a/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/lib/Target/AArch64/AArch64InstrFormats.td
@@ -913,6 +913,9 @@ class MSRpstateI
   let Inst{7-5} = pstatefield{2-0};
 
   let DecoderMethod = "DecodeSystemPStateInstruction";
+  // MSRpstateI aliases with MSRI. When the MSRpstateI decoder method returns
+  // Fail the decoder should attempt to decode the instruction as MSRI.
+  let hasCompleteDecoder = 0;
 }
 
 // SYS and SYSL generic system instructions.

diff --git a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
index 615d9ba19ca8ef6da63dd8deb0a5a39ab5a54ed6..089fc821097b8076e6c86a7d31bd1878c7fe41a6 100644 (file)
--- a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
+++ b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -4172,12 +4172,16 @@
 
 # CHECK: mrs     x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}}
 # CHECK: mrs     x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}}
+# CHECK: mrs     xzr, {{s0_0_c4_c0_0|S0_0_C4_C0_0}}
 # CHECK: msr     {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12
 # CHECK: msr     {{s3_7_c11_c13_7|S3_7_C11_C13_7}}, x5
+# CHECK: msr     {{s0_0_c4_c0_0|S0_0_C4_C0_0}}, xzr
 0xac 0xf1 0x3f 0xd5
 0xed 0xbf 0x3a 0xd5
+0x1f 0x40 0x20 0xd5
 0x0c 0xf0 0x18 0xd5
 0xe5 0xbd 0x1f 0xd5
+0x1f 0x40 0x00 0xd5
 
 #------------------------------------------------------------------------------
 # Test and branch (immediate)