Remove some instructions that seem to only exist to trick the filtering checks in...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192090 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index b2310c70cec67f88f2544abbf3db74fbf188e1d3..3c660d17a92d3095244c40988e33cb0e6076d94a 100644 (file)
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -4774,18 +4774,6 @@ def VMOVQd64rr_alt : VS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
                           IIC_SSE_MOVDQ>, VEX, VEX_W;
 } // SchedRW
 
                           IIC_SSE_MOVDQ>, VEX, VEX_W;
 } // SchedRW
 

-// Instructions for the disassembler
-// xr = XMM register
-// xm = mem64
-
-let SchedRW = [WriteMove] in {
-let Predicates = [UseAVX] in
-def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
-                 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
-def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
-                 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
-} // SchedRW
-

 //===---------------------------------------------------------------------===//
 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
 //===---------------------------------------------------------------------===//
 //===---------------------------------------------------------------------===//
 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
 //===---------------------------------------------------------------------===//

diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt
index 2d2b3351de60ccf4d36cbdad6062942ac62a948a..b6a62c4f697515a42910ab747195396d2ae56838 100644 (file)
--- a/test/MC/Disassembler/X86/x86-32.txt
+++ b/test/MC/Disassembler/X86/x86-32.txt
@@ -690,3 +690,9 @@
 
 # CHECK: decl %ecx
 0x49
 
 # CHECK: decl %ecx
 0x49

+
+# CHECK: movq %xmm0, %xmm0
+0xf3 0x0f 0x7e 0xc0
+
+# CHECK: vmovq %xmm0, %xmm0
+0xc5 0xfa 0x7e 0xc0

diff --git a/test/MC/Disassembler/X86/x86-64.txt b/test/MC/Disassembler/X86/x86-64.txt
index 8c3e4fdf4fc041b3c4837c3cf540e74ad3c84fa6..f7e71fd15d66ae3289484523093982959fb8066b 100644 (file)
--- a/test/MC/Disassembler/X86/x86-64.txt
+++ b/test/MC/Disassembler/X86/x86-64.txt
@@ -223,3 +223,9 @@
 
 # CHECK: decq %rcx
 0x48 0xff 0xc9
 
 # CHECK: decq %rcx
 0x48 0xff 0xc9

+
+# CHECK: movq %xmm0, %xmm0
+0xf3 0x0f 0x7e 0xc0
+
+# CHECK: vmovq %xmm0, %xmm0
+0xc5 0xfa 0x7e 0xc0

diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index fed3f7758edcd89935a080e03e7e6bb090f84b33..d3427207b3cd71842d0a6c9ba08f5f619b3547fd 100644 (file)
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -538,7 +538,8 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const {
 
   if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
     return FILTER_WEAK;
 
   if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
     return FILTER_WEAK;

-  if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
+  if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos &&
+      Name != "MOVZPQILo2PQIrr")

     return FILTER_WEAK;
   if (Name.find("Fs") != Name.npos)
     return FILTER_WEAK;
     return FILTER_WEAK;
   if (Name.find("Fs") != Name.npos)
     return FILTER_WEAK;