Register list operands are not allowed to contain only a single register. Alternate...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143552 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 6927d2d053ce2e022c7659829e1be38af4216362..8dab153132108317eec2f669bbe97e13a1b20547 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -1111,7 +1111,11 @@ static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
   }
 
   // Empty register lists are not allowed.
-  if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
+  uint32_t popcnt = CountPopulation_32(Val);
+  if (popcnt == 0) return MCDisassembler::Fail;
+  // and one-register lists are unpredictable.
+  else if (popcnt == 1) Check(S, MCDisassembler::SoftFail);
+
   for (unsigned i = 0; i < 16; ++i) {
     if (Val & (1 << i)) {
       if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))