Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool IsLittleEndian);
+ using LLVMTargetMachine::getSubtargetImpl;
const AArch64Subtarget *getSubtargetImpl() const override {
return &Subtarget;
}
CodeGenOpt::Level OL,
bool isLittle);
+ using LLVMTargetMachine::getSubtargetImpl;
const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
/// \brief Register ARM analysis passes with a pass manager.
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
+ using LLVMTargetMachine::getSubtargetImpl;
const HexagonSubtarget *getSubtargetImpl() const override {
return &Subtarget;
}
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
+ using LLVMTargetMachine::getSubtargetImpl;
const MSP430Subtarget *getSubtargetImpl() const override {
return &Subtarget;
}
void addAnalysisPasses(PassManagerBase &PM) override;
+ using LLVMTargetMachine::getSubtargetImpl;
const MipsSubtarget *getSubtargetImpl() const override {
if (Subtarget)
return Subtarget;
const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit);
+ using LLVMTargetMachine::getSubtargetImpl;
const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; }
ManagedStringPool *getManagedStrPool() const {
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
+ using LLVMTargetMachine::getSubtargetImpl;
const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; }
// Pass Pipeline Configuration
StringRef CPU, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL);
~AMDGPUTargetMachine();
+
+ using LLVMTargetMachine::getSubtargetImpl;
const AMDGPUSubtarget *getSubtargetImpl() const override {
return &Subtarget;
}
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64bit);
+ using LLVMTargetMachine::getSubtargetImpl;
const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; }
// Pass Pipeline Configuration
CodeGenOpt::Level OL);
// Override TargetMachine.
+ using LLVMTargetMachine::getSubtargetImpl;
const SystemZSubtarget *getSubtargetImpl() const override {
return &Subtarget;
}
StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
+
+ using LLVMTargetMachine::getSubtargetImpl;
const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
/// \brief Register X86 analysis passes with a pass manager.
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
+ using LLVMTargetMachine::getSubtargetImpl;
const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; }
// Pass Pipeline Configuration