1 //==-- AArch64TargetMachine.h - Define TargetMachine for AArch64 -*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the AArch64 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETMACHINE_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETMACHINE_H
17 #include "AArch64InstrInfo.h"
18 #include "AArch64Subtarget.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/Target/TargetMachine.h"
24 class AArch64TargetMachine : public LLVMTargetMachine {
26 AArch64Subtarget Subtarget;
29 AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU,
30 StringRef FS, const TargetOptions &Options,
31 Reloc::Model RM, CodeModel::Model CM,
32 CodeGenOpt::Level OL, bool IsLittleEndian);
34 using LLVMTargetMachine::getSubtargetImpl;
35 const AArch64Subtarget *getSubtargetImpl() const override {
39 // Pass Pipeline Configuration
40 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
42 /// \brief Register AArch64 analysis passes with a pass manager.
43 void addAnalysisPasses(PassManagerBase &PM) override;
45 /// \brief Query if the PBQP register allocator is being used
46 bool isPBQPUsed() const { return usingPBQP; }
52 // AArch64leTargetMachine - AArch64 little endian target machine.
54 class AArch64leTargetMachine : public AArch64TargetMachine {
55 virtual void anchor();
57 AArch64leTargetMachine(const Target &T, StringRef TT, StringRef CPU,
58 StringRef FS, const TargetOptions &Options,
59 Reloc::Model RM, CodeModel::Model CM,
60 CodeGenOpt::Level OL);
63 // AArch64beTargetMachine - AArch64 big endian target machine.
65 class AArch64beTargetMachine : public AArch64TargetMachine {
66 virtual void anchor();
68 AArch64beTargetMachine(const Target &T, StringRef TT, StringRef CPU,
69 StringRef FS, const TargetOptions &Options,
70 Reloc::Model RM, CodeModel::Model CM,
71 CodeGenOpt::Level OL);
74 } // end namespace llvm