ARM assembly parsing and encoding of SMLAL instruction.

Fix parsing of carry-setting variant SMLALS and add tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135797 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index ef611b21e72d87d95033bd65ad58a66520273f6d..1455389ce61ec991961d009298bd516f0d07af14 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -2153,7 +2153,7 @@ StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic,
   // First, split out any predication code. Ignore mnemonics we know aren't
   // predicated but do have a carry-set and so weren't caught above.
   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
-      Mnemonic != "muls") {
+      Mnemonic != "muls" && Mnemonic != "smlals") {
     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
       .Case("eq", ARMCC::EQ)
       .Case("ne", ARMCC::NE)

diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 1bd2eacad6a4768c1d7ee3b0fad49f8070530ab5..16b6ff53fc20494165a55126855a4ab6ebf1ec40 100644 (file)
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -1403,6 +1403,20 @@ _func:
 @ CHECK: smladxhi      r2, r3, r5, r8  @ encoding: [0x33,0x85,0x02,0x87]
 
 
+@------------------------------------------------------------------------------
+@ SMLAD/SMLADX
+@------------------------------------------------------------------------------
+        smlal r2, r3, r5, r8
+        smlals r2, r3, r5, r8
+        smlaleq r2, r3, r5, r8
+        smlalshi r2, r3, r5, r8
+
+@ CHECK: smlal r2, r3, r5, r8          @ encoding: [0x95,0x28,0xe3,0xe0]
+@ CHECK: smlals        r2, r3, r5, r8          @ encoding: [0x95,0x28,0xf3,0xe0]
+@ CHECK: smlaleq       r2, r3, r5, r8  @ encoding: [0x95,0x28,0xe3,0x00]
+@ CHECK: smlalshi      r2, r3, r5, r8  @ encoding: [0x95,0x28,0xf3,0x80]
+
+
 @------------------------------------------------------------------------------
 @ STM*
 @------------------------------------------------------------------------------