ARM encoding and assembly parsing of SMLAD{X} instructions.

Fix encoding of destination register. Add tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135796 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index fb822355cd68999a3619e662d50623bb47a489d5..009f7add00e6e39204c7eb524b4e59740586acf8 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -3209,14 +3209,14 @@ class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
   : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
   bits<4> Rn;
   bits<4> Rm;
-  let Inst{4}     = 1;
-  let Inst{5}     = swap;
-  let Inst{6}     = sub;
-  let Inst{7}     = 0;
-  let Inst{21-20} = 0b00;
-  let Inst{22}    = long;
   let Inst{27-23} = 0b01110;
+  let Inst{22}    = long;
+  let Inst{21-20} = 0b00;
   let Inst{11-8}  = Rm;
+  let Inst{7}     = 0;
+  let Inst{6}     = sub;
+  let Inst{5}     = swap;
+  let Inst{4}     = 1;
   let Inst{3-0}   = Rn;
 }
 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
@@ -3230,6 +3230,8 @@ class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
                 InstrItinClass itin, string opc, string asm>
   : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
   bits<4> Ra;
+  bits<4> Rd;
+  let Inst{19-16} = Rd;
   let Inst{15-12} = Ra;
 }
 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,

diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 0697ce0639a75d7572477522fcb64c4f48a8ad43..1bd2eacad6a4768c1d7ee3b0fad49f8070530ab5 100644 (file)
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -1389,6 +1389,19 @@ _func:
 @ CHECK: smlatbne      r4, r2, r3, r2  @ encoding: [0xa2,0x23,0x04,0x11]
 @ CHECK: smlatteq      r8, r3, r8, r4  @ encoding: [0xe3,0x48,0x08,0x01]
 
+@------------------------------------------------------------------------------
+@ SMLAD/SMLADX
+@------------------------------------------------------------------------------
+        smlad r2, r3, r5, r8
+        smladx r2, r3, r5, r8
+        smladeq r2, r3, r5, r8
+        smladxhi r2, r3, r5, r8
+
+@ CHECK: smlad r2, r3, r5, r8          @ encoding: [0x13,0x85,0x02,0xe7]
+@ CHECK: smladx        r2, r3, r5, r8          @ encoding: [0x33,0x85,0x02,0xe7]
+@ CHECK: smladeq       r2, r3, r5, r8  @ encoding: [0x13,0x85,0x02,0x07]
+@ CHECK: smladxhi      r2, r3, r5, r8  @ encoding: [0x33,0x85,0x02,0x87]
+
 
 @------------------------------------------------------------------------------
 @ STM*